JPH0363259B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is directed to converting an audio signal, etc. into a PCM code, and correcting erroneous data for which a correction command is instructed in a correction circuit when digitally reproducing the same. The present invention relates to a data transmission system correction device for outputting data.

[Technical background of the invention]

Recently, devices have been developed that convert audio signals into PCM codes and record and reproduce them. this
A PCM code is a sampled, quantized, and encoded audio signal, and redundant bits are added to correct digital signal dropouts that occur in the transmission system, especially the recording system, during playback during encoding. are doing. It is desirable to reduce the number of redundant bits as much as possible so that the correction ability is high.

Here, a digital signal obtained by sampling and quantizing an audio signal is assumed to be one information symbol. Then, arithmetic processing is performed on several of these information symbols, and redundant bits for correction called parity symbols are added. These information symbols and parity symbols are collectively called one block.

Conventionally, the ability of a correction circuit to correct errors in information symbols using parity symbols is limited to at most four errors in one block, and it is not possible to correct more errors than that. If correction cannot be made in this way, if the erroneous information symbol is output as is, it will become noise, so it is output after being corrected into a signal close to the original waveform through a correction circuit.

In other words, if the correction ability is limited to two information symbols in one block, not only will it be impossible to correct when there are three or more errors, but it will also be impossible to determine which information symbols are incorrect and how many in one block. It is normal to correct the entire block. Therefore, the correction circuit adds a correction flag indicating a correction command to all information symbols of a block containing three or more errors and outputs them to the correction circuit.

Then, the correction circuit corrects all the information symbols with the correction flag to a signal close to the original waveform by means of average value correction or pre-holding and outputs the signal.

[Problems with background technology]

However, since it is impossible to determine which information symbol should be corrected with the correction flag added by the above correction circuit, the correction flag becomes the same as the one attached to all information symbols in the block, and the correction flag added by the correction circuit described above is in the same state as the one attached to all information symbols in the block. Even the symbols will be corrected. Therefore, if the number of erroneous information symbols due to dropouts in the transmission system increases and the number of information symbols with correction flags increases, the number of corrections will increase and the sound quality will deteriorate.

[Purpose of the invention]

The present invention improves the above-mentioned drawbacks, and even when, for example, a correction flag is attached to all the information symbols of a block in which three or more information symbols are erroneous, only one of the information symbols to which the correction flag is attached will be corrected. To provide a data transmission system correction device that outputs correct information symbols without errors as they are and corrects only erroneous information symbols, thereby improving the sound quality of audio playback, for example. .

[Summary of the Invention] That is, the data transmission system correction device according to the present invention determines the correction range based on a predicted value such as an average value or a pre-held value calculated from data before and after an input information symbol to be corrected. The information symbols to be corrected that fall within this range are determined to be correct and output as they are, and those that fall outside the range are determined to be errors and a correction value calculated as a predicted value is output.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 shows the basic configuration of a PCM digital recording and playback device.The sound to be collected is detected by the microphone 11, and the electrically converted signal corresponding to the detected sound is sent to the input terminal. After the signal is amplified by an amplifier circuit 13 via a band compression circuit 12, the level of the signal is compressed into a signal within a predetermined frequency band by a band compression circuit 14, and the signal is supplied to an encoding circuit 15. This encoding circuit 15 includes, for example, a low-pass filter (not shown),
It is composed of a sample hold circuit, a multiplexer circuit, an A/D conversion circuit, etc., and samples the output signal from the band compression circuit 14 at a predetermined period (sampling), and converts this sampled pulse-like signal into its level. It converts (quantizes) the digital signal corresponding to the information symbol into an information symbol and outputs it. This encoding circuit 15
The information symbols outputted from the circuit 16 are added with parity symbols, which are redundant bits for correction, for each block in the error detection and correction code addition circuit 16, and then outputted and recorded in the recording device 17. .

Next, when reproducing the contents recorded in the recording device 17 as described above, the information symbols read out from the recording device 17 are corrected and corrected by the data transmission system correction device 18 and sent to the decoding circuit 19. Supplied. This decoding circuit 19 is composed of, for example, a D/A converter circuit, a demultiplexer circuit, a low-pass filter, etc. (not shown), and converts the input information symbol into a pulse-like signal of a level corresponding to its value. The level of this pulsed signal is made continuous, converted into an analog signal, and output. The analog signal output from the decoding circuit 19 is level-expanded by a band expansion circuit 20 within a predetermined frequency band whose level has been compressed by the band compression circuit 14, and then amplified by an amplifier circuit 21. , and is supplied to a speaker 23 via an output terminal 22, where the audio signal is reproduced.

FIG. 2 shows the configuration of the data transmission system correction device 18 in the reproduction system.
The information symbols transmitted from 7 are supplied to a correction circuit 24. This correction circuit 24 detects and corrects errors for each block using the parity symbols added by the error detection and correction code addition circuit 16, and outputs the detected errors to the next stage decoding circuit 19 (not shown). However, as mentioned above, there is a limit to this correction ability, for example, the correction ability is limited to 2 out of 1 block.
If three or more errors occur, it is impossible to determine which information symbol is an error. Therefore,
A correction flag 26 is added to each information symbol 25 of a block with three or more errors,
For example, information symbols D(n-1), D(n), D(n
+1) . . . and transmitted to the correction circuit 27.

This correction circuit 27 includes an input selector 28,
This input selector 28 receives information symbols from the correction circuit 24, and an output selector 29 to be described later.
Information symbols from which the correction process has already been performed are provided. Here, assuming that the information symbol from the correction circuit 24 is D(n) and the information symbol from the output selector 29 is D(n-1),
The input selector 28 switches between information symbols D(n) and D(n-1) in response to the control signal S1 and sends the selected information symbols to the memory 30. This memory 30 includes memory areas M1 and M2 that each store one information symbol and a correction flag added to the information symbol D(n-
1) is stored and set in the memory area M1, and D(n) is stored in the memory area M2. Then, the information symbol D(n-1) which has been corrected and stored in the memory area M1 is read out and stored in the latch 31 and the output latch 32, and the latch information symbol D(n-1) of the output latch 32 is read out and stored in the latch 31 and the output latch 32. is sent to a decoding circuit 19 (not shown) in response to a control clock CP1.

At the same time, the correction circuit 24 outputs the information symbol D.
Information symbol D(n+1) following information symbol D(n) is supplied to the input selector 28, and this information symbol D(n
+1) is stored and set in the memory area M1 of the memory 30. And this information symbol D(n+1)
is supplied to the correction value calculation circuit 33. The latch information symbol D(n-1) of the latch 31 is also supplied to this correction value calculation circuit 33, and the information symbols D(n-1) on both sides of the information symbol D(n) are supplied.
The average value of and D(n+1) is calculated. That is,
The correction value calculation circuit 33 performs an average value calculation of D(n-1)+D(n+1)/2=H(n), and the predicted value H(n) resulting from this calculation is supplied to the subtraction circuit 34. The information symbol D(n) stored in the memory area M2 of the memory 30 is also supplied to the subtraction circuit 34, and the calculation H(n)-D(n)=S(n) is performed, and the difference information is obtained. S(n) (absolute value) is supplied to the gate circuit 35 as a control signal.

This gate circuit 35 is configured as shown in FIG. 3, for example, and includes a NOR circuit 36 and an AND circuit 37. For example, 8-bit information S(n) (MSB is the sign bit)
The upper five bits of the circuits 36 and 37 are supplied in parallel, and the outputs of the respective circuits 36 and 37 are connected to the NOR circuit 38.
That is, this gate circuit 35 uses a complementary code with two's complement representation, and sets the predicted value H(n) as a reference to 0, and sets the range from -8 to +7. In other words, when the information S(n) of the difference between H(n) and D(n) inputted from the subtraction circuit 34 is -8<S(n)≦+7, the information symbol D(n) is corrected. When S(n)≦-8,+7<S(n), it judges the information symbol D(n) to be an error and sends a high-level H signal. The signals are each outputted from the NOR circuit 38 as a control signal S2. Then, the output control signal S from this gate circuit 35
2 is supplied to the output selector 29 described above.

This output selector 29 is connected to the memory area M2.
, and the predicted value H(n) from the correction value calculation circuit 33, and according to the control signal S2 from the gate circuit 35, D(n) and H
(n) is switched and output. For example, when the command from the gate circuit 35 is an L signal, the information symbol D(n) of the data to be corrected is determined to be correct;
(n) is output as is, and when the signal is H, the information symbol D(n) of the data to be corrected is determined to be an error, so the predicted value H(n) is output as a correction value, and the corrected information is It is sent to the input selector 28 as a symbol D(n).

That is, a digital signal with a parity symbol added to each block input from the recording device 17 is transmitted to the correction circuit 24, blocks that have been corrected are output to the next stage decoding circuit, and blocks that cannot be corrected are output to the correction circuit 24. A correction flag 26 is added to all information symbols 25 in the block and sent to a correction circuit 27. Then, the information symbol 25 with this correction flag 26 is sent to the memory 3 via the input selector 28.
0, and the subtraction circuit 34 and gate circuit 35
is compared with the predicted value from the correction value calculation circuit 33 to determine whether or not it is a correct information symbol.
Then, from the output selector 29 into which the information symbol to be corrected and the predicted value are input, if the information is determined to be correct according to the control signal from the gate circuit 35, it is output as is, and if it is an error, the predicted value is output as a correction value. input selector 28, memory 3
0 to the output latch 32, and is sent to the next stage decoding circuit (not shown).

FIG. 4 shows the correction for a certain sampling value n points in the above correction circuit. −
1) and (n+1) are assumed to be D(n-1) and D(n+1), respectively. Also,
The average value created at points (n-1) and (n+1) is defined as the predicted value H(n), the upper limit range based on this H(n) is H+(n), and the lower limit range is H-(n). shall be. At this time, if the n-point information symbol D(n) is between H+(n) and H-(n), D
(n) is output as is, and H+(n) and H-
(n), the information symbol is truncated and the predicted value H(n) is used as a correction value.
Output. If the width of this range is made smaller, the amount of average value correction will increase, making it difficult for normal information symbols with correction flags to be saved.On the other hand, if the width of the range is made larger, the amount of average value correction will be reduced, making it difficult for normal information symbols with correction flags to be saved. Normal information symbols attached are easier to save, but the difference from the original waveform becomes large, so
This range is determined by considering the error rate of information symbols with correction flags.

Therefore, if the range is determined based on the predicted value and the correctness of the information symbol with the correction flag input to the correction circuit is determined, the correct information symbol can be passed through and the erroneous information symbol can be corrected to the correction value. will be output.

〔Effect of the invention〕

As described above, according to the present invention, a certain range is set based on a predicted value such as an average value or a pre-held value calculated from data before and after an information symbol with a correction flag that is input to a correction circuit. However, by determining information symbols that fall within this range as correct data and outputting them as is, and determining those outside the range as errors and outputting predicted values as correction values, errors due to dropouts in the transmission system occur frequently. Even if the number of information symbols with correction flags sent from the correction circuit to the correction circuit increases, only the correct information symbols can be saved and the amount of correction is reduced, so that deterioration in sound quality can be reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating the basic configuration of a PCM digital recording/playback device, FIG. 2 is a diagram illustrating the configuration of a data transmission system correction device according to the present invention, and FIG. 3 is a diagram illustrating the configuration of a gate circuit. FIG. 4 is a diagram illustrating correction for n-point sampling values. 11... Microphone, 12... Input terminal,
13...Amplification circuit, 14...Band compression circuit, 15
... Encoding circuit, 16 ... Error detection and correction code addition circuit, 17 ... Recording device, 18 ... Data transmission system correction device, 19 ... Decoding circuit, 20 ... Bandwidth expansion circuit, 21 ... Amplification circuit , 22...output terminal,
23... Speaker, 24... Correction circuit, 25...
...Information symbol, 26...Correction flag, 27...
Correction circuit, 28...Input selector, 29...Output selector, 30...Memory, 31...Latch, 3
2... Output latch, 33... Correction value calculation circuit,
34... Subtraction circuit, 35... Gate circuit, 36,
38...NOR circuit, 37...AND circuit, D(n)
...Corrected information symbol, H(n)...Predicted value,
S(n)...Difference information between D(n) and H(n), S
1, S2, CP1, CP2...control signal.

Claims (1)

[Claims] 1 Error correction is performed for each block of multiple information symbols that are continuously transmitted, and if this correction is not possible, a correction flag is set on all information symbols within the block regardless of whether each information symbol is correct or incorrect. In a correction device used in a data transmission system for correcting and outputting an information symbol to which the correction flag has been added, means for detecting an information symbol D(n) to which the correction flag has been added; means for detecting the information symbols D(n-1) and D(n+1) before and after n), and means for calling the information symbols D(n-1) and D(n+1) to calculate the predicted value H( a correction value calculation circuit that calculates n);
Means for calculating the difference S(n) by comparing the predicted value H(n) calculated by the correction value calculation circuit with the information symbol D(n), and A reference range is specified that includes the difference S(n) and is estimated to not include the difference S(n) if the information symbol D(n) is incorrect. means for determining whether or not exists within the above reference range;
A means for transmitting the information symbol D(n) as it is in a state where the difference S(n) is determined to be within the reference range by the discriminating means;
A data transmission system correction device comprising means for replacing the information symbol D(n) with the predicted value H(n) and transmitting the predicted value H(n) in a state in which the information symbol D(n) is determined to be outside the reference range.