JPH0358485A - Manufacturing method of vertical MOSFET device - Google Patents

Abstract

PURPOSE:To dispense with an alignment margin and to make an element small in size by a method wherein a diffusion layer serving as a source region and a contact hole are formed in a self-aligned manner taking advantage of bird beaks which occur when a polycrystalline semiconductor layer is selectively oxidized using an acid resistant film such as a nitride film or the like as a mask. CONSTITUTION:After a first and second polycrystalline semiconductor layer, 24 and 30, are selectively oxidized using an acid resistant film 25 as a mask, a second diffusion layer 33 is formed in a self-aligned manner on a first diffusion layer 23 around a groove 28 through a removing process of a selective oxide film 31 and a process in which an impurity doped insulating film layer 34 is formed on the whole face and then thermally treated. After the formation of the second diffusion layer 33, the impurity doped insulating layer 34 is removed, then an oxide film layer 32 is formed using the acid resistant film 25 as a mask again, and the acid resistant film 25 and the residual first polycrystalline semiconductor layer 24 are removed, whereby a contact hole 35 is formed in a self-aligned manner. As mentioned above, the second diffusion layer 33 and the contact hole 35 are formed in a self-aligned manner. By this setup, an alignment margin can be dispensed with and an element can be made small in size.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a vertical MOS FET device. (Prior Art) A conventional method for manufacturing a vertical MOS FET device is shown in Figure 2 (a).
) to (ω. This conventional method is described in the document “IEEE TRANSACTIONS ON ELECTRON DEVICES (IEEE TRANSACTIONS)”.
SON ELECTRON DELICBS)JLLI
I (11) (19B?-11) P2329-23
34 J. First, a specific resistance of 1
．． An N-type epitaxial layer 2 with a resistance of 5Ω is formed.
A junction depth of 3 pm is formed on the surface of the mold epitaxial layer 2.
A P-type diffusion layer 3 with a sheet resistance of 500 to 1000 Ω/hole is formed. Next, thermal oxidation is performed to form a first oxide film layer 4 with a thickness of 250 nm on the surface of the P-type diffusion layer 3, and then a Si3N4 layer 5 is formed thereon by the CVD method. Then, a second oxide film layer 6 was formed on 10,000 people by the CVD method. Note that the first oxide film layer 4 is made of the Si3N
It is provided to relieve the stress caused by the four layers 5. (Second
(a)) Next, the second oxide film layer 6, s+. l1. The layer 5 and the first oxide film layer 4 are selectively removed using a resist (not shown) as a mask, and a width of 3 is formed.
Form an opening 7 of n. Subsequently, the P-type diffusion layer 3 is etched through the opening 7 by the PIE method using the remaining second oxide film layer 6 as a mask.
A groove 8 is formed so as to reach the N-type epitaxial layer 2. (FIG. 2 (bl). After that, the second oxide film layer 6 is removed by etching. Next, by performing selective oxidation using the Si3Ni layer 5 as a mask, the inner wall of the trench 8 is coated with a gate of 1000 mm thick. An oxide film layer 9 is formed. Thereafter, an N-type doped polysilicon layer 10 is formed on the entire surface to a thickness of about 7 mm by CVD, and the groove 8 is completely filled with this polysilicon layer 10.
(FIG. 2(c)) Then, by etching back the polysilicon layer 10 using the SrJa layer 5 as a stopper,
This polysilicon layer 10 is left only in the groove 8 (see Fig. 2 (
d)). Thereafter, the StJ4 layer 5 and the first oxide film layer 4 are removed by etching (FIG. 2(e)). Next, P around the groove
On the surface of the mold diffusion layer 3, the junction depth is 2n and the sheet resistance is 20~
An N-type diffusion layer 11 of approximately 30Ω/hole is formed by ion implantation using a resist mask and heat treatment (see Fig. 2(f)).
))． Next, the surface of polysilicon I1i10 in the groove and P
A third oxide film layer 12 is formed to a thickness of about 5000 by thermal oxidation on the entire surface of the N-type and N-type diffusion layers 3.11 (
Figure 2 (g)). After that, a part of the third oxide film layer 12 is removed by photolithography, and the P-type and N-type diffusion Ji3,
A contact hole 13 is formed to expose the top of the contact hole 11. Next, a layer with a thickness of 2n is connected to the P-type and N-type diffusion layers 3 and 11 through the contact hole l3.
An aluminum ξ wiring layer l4 is formed by vapor deposition (see FIG. 2 (
h)). Through the above steps, the N-type diffusion layer 11 is formed into a source region. The P-type diffusion layer 3 is used as a body region, and the polysilicon layer 10 in the groove portion is used as a gate electrode. N-type epitaxial layer 2 is used as a drain region. Vertical MOS F [! T is obtained.

(Issue I to Solve by the Invention!) However, in the conventional manufacturing method as described above, a photolithography process is required when forming the N-type diffusion layer 11 and forming the contact hole 13. Therefore, if the alignment margin in each photolithography process is defined as 'l ps, a total margin of 4n or more is required, which poses a problem in that the device size increases significantly. This invention was made in view of the above points, and is a vertical type M that can reduce element dimensions without requiring alignment margin.
The purpose is to provide a method for manufacturing an OS PET device. (Means for Solving the Problems) This invention solves the problem of bird's beaks that occur when selectively oxidizing a polycrystalline semiconductor layer (for example, a polysilicon layer) using an oxidation-resistant film such as a nitride film layer (Si3N layer) as a mask. In this method, a diffusion layer (second diffusion layer) as a source region and a contact hole are formed using self-alignment lines.The manufacturing method is as follows.First, the first conductive layer is After forming a first diffusion layer of a second conductivity type opposite to the first conductivity type on the surface of the type semiconductor substrate or the surface of the first conductivity type epitaxial layer, a first polycrystalline semiconductor layer is formed thereon. .Oxidation-resistant films are stacked and formed in this order.After selectively forming an opening in the oxidation-resistant film and the first polycrystalline semiconductor layer, the semiconductor layer is formed into the first diffusion layer through the opening. A trench is formed to reach the substrate or the epitaxial layer. After forming a gate insulating film layer on the inner wall of the trench, the trench is filled with a second polycrystalline semiconductor layer. After that, the oxidation-resistant film is formed. By selectively oxidizing the first polycrystalline semiconductor layer and the second polycrystalline semiconductor layer as a mask, the selective oxide film in which a bird's beak has occurred between the oxidation-resistant film and the first diffusion layer around the groove portion is removed from the second polycrystalline semiconductor layer. At the same time as it is formed on the surface of the crystalline semiconductor layer, the end of the first polycrystalline semiconductor layer is retreated from the trench sidewall.Then, the selective oxide film is removed.The first diffusion layer around the trench exposed by this removal process is removed. An insulating film layer containing impurities of the first conductivity type is formed on the entire surface including the surface.Then, by performing heat treatment to diffuse the impurities from the insulating film layer, a first diffusion layer portion around the groove portion is formed. A second diffusion layer of the first conductivity type is formed by extending under the remaining first polycrystalline semiconductor layer whose end portion has receded from the trench sidewall portion.After that, after removing the impurity-doped insulating film layer, An oxide film layer is formed on the exposed surfaces of the second polycrystalline semiconductor layer and the second diffusion layer using the oxidation-resistant film as a mask.Then, the oxidation-resistant film is removed, and the remaining first
By removing the polycrystalline semiconductor layer, the first. A contact hole is opened on the second diffusion layer. (Function) In the present invention, after selectively oxidizing the first and second polycrystalline semiconductor layers using the oxidation-resistant film as a mask, the process of removing the selective oxide film, forming the entire surface of the insulating film doped with impurities, and Through the heat treatment process, a second diffusion layer is formed in a self-aligned manner in the first diffusion layer portion around the groove. After forming this second diffusion layer, after removing the impurity-doped green film layer, an oxide film layer is formed again using the oxidation-resistant film as a mask, and then the oxidation-resistant film and the remaining first polycrystalline semiconductor are removed. By removing the layer, a contact hole is formed in the self-line. Since the second diffusion layer and the contact hole are formed in a self-aligned manner as described above, the mask alignment allowance when forming them using a photolithography process is omitted. (Example) An example of the present invention will be described below with reference to FIGS. 1(a) to (e). First, an N-type semiconductor substrate 2 with a specific resistance of about 0.004Ω・0
1 and resistivity l. 5Ω・N type Ebitaxi medium layer 22
A P-type diffusion layer 23 is formed on the surface of the N-type epitaxial layer 22 with a junction depth of 3-3 and a sheet resistance of 500 Ω/hole. Next, a first polysilicon layer 24 with a thickness of 2,000 layers is formed on the surface of the P-type diffusion layer 23 by CVD, and a SiJa layer 25 with a thickness of 5,000 layers is further formed thereon by CVD. moreover,
A first oxide film layer 26 with a thickness of 10,000 layers is formed on the SisNa layer 25 by the CVD method. Thereafter, the first oxide film layer 2 6 , S
isNn 11 2 5 and first polysilicon layer 24
An opening 27 having a width of 3- is selectively formed. (Figure 1 (
a)) Next, using the IM layer 26 as a mask, the P-type diffusion layer 23 is etched by RIE through the opening 27 to form a 5 tl depth in the P-type diffusion layer 23.
A vertical groove 28 reaching the N-type epitaxial layer 22 of m
(Fig. 1 Q))). After that, the first oxide film layer 2
6 is removed by etching. Next, a gate oxide film layer 29 with a thickness of 1000 mm is formed on the inner wall of the trench 28 by selective oxidation using the SIsNa layer 25 as a mask (FIG. 1 (cl)).
Next, a second polysilicon layer 30 doped with N-type impurities is formed on the entire surface to a thickness of about 71 mm by CVD to completely fill the trench 28 (FIG. 1(d)). After that, Si3
By etching the second polysilicon layer 30 using the N4 layer 25 as a stopper, the second polysilicon layer 30 is left only in the groove 28 and the surface is planarized (FIG. 1(e)).

Next, using the Si3Na layer 25 as a mask again, the first polysilicon layer 24 and the second polysilicon layer 30 are selectively oxidized. This selective oxidation oxidizes the surface portion of the first polysilicon layer 24 and oxidizes the second polysilicon layer 30 in the lateral direction. As a result, the S:Ja layer 2 around the groove portion
A selective oxide film 3l is formed on the surface of the first polysilicon layer 24, in which a bird's beak with a width IIlm is formed between the polysilicon layer 5 and the P-type diffusion N23. Furthermore, the end of the first polysilicon layer 24 is set back from the inner wall of the groove by the width of the bird's beak (FIG. 1(f)). Next, the selective oxide film 31 is removed by etching (
Figure 1 (g)). Thereafter, an oxide film layer 32 doped with N-type impurities is formed by CVD on the entire surface including the surface of the P-type diffusion layer 23 around the trench exposed by removing the selective oxide film. Then, heat treatment is performed at, for example, 1000° C. for 30 minutes. Through this heat treatment, the N-type impurity is diffused from the oxide film layer 32 into the P-type diffusion layer 23 around the groove, and the N-type diffusion layer 33 is formed to a depth of about 21 mm. At this time, the N-type diffusion layer 33 is formed so that its end part recedes from the inner wall of the trench and extends 2n below the first polysilicon layer 24 remaining on the P-type diffusion layer 23 (first Figure (h)).

Next, the N-type impurity-doped oxide film layer 32 is removed (FIG. 1(i)). Thereafter, selective oxidation is performed three times using the SizNa layer 25 as a mask to form a layer with a thickness of 5000 mm on the surface of the remaining second polysilicon layer 30 in the trench and the surface of the N-type diffusion layer 33 around the trench.
An insulating oxide film layer 34 of A is formed.

At this time, the first polysilicon layer 24 is also 50 mm from the end thereof.
00 is greatly oxidized (Fig. 1 (j)).

Next, CF. +0. The SIsN4 layer 25 and the first polysilicon layer 24 are removed by isotropic dry etching using gas.
is removed, and a contact hole 35 is selectively formed on the P-type diffusion layer 23 and the N-type diffusion layer 33 (see FIG. 1(G)).
, (1)). At this time, the insulating oxide film layer 34 is also etched, but since the etching rate is very small compared to that of the SixNa layer 25 and the first silicon layer 24, a film thickness of more than 4000 nm remains. Finally, the P-type and N-type diffusion layers 23.33 are connected through the contact hole 35 to a thickness of 2 1zm.
An aluminum wiring layer 36 is formed by vapor deposition (Fig. 1 (m)
) ).

Through the above steps, the N-type diffusion layer 33 becomes a source region, and the P-type diffusion layer 23 becomes a body region. The second polysilicon in the groove [3
0 is the gate electrode. A vertical type in which the N-type epitaxial N22 is used as the drain region 2 and the side surface of the bay 28 of the P-type diffusion layer 23 is used as the channel region? An IOS FET is obtained.

According to this vertical MOS FET, since the N-type diffusion layer 33 and the contact hole 35 are formed by self-line as described above, the mask alignment margin (2 tm 2 =
4 4 ) can be removed, and the element size can be reduced by 4 μm.

In the above embodiment, the epitaxial layer 22 is deposited on the semiconductor substrate 21 and elements are formed on this epitaxial layer 22, but the epitaxial layer 22 is omitted and elements are formed directly on the semiconductor substrate 21. You can also do (Effects of the Invention) As explained above in detail, according to the manufacturing method of the present invention, the diffusion layer (second diffusion layer) as a source region and the contact hole are formed by self-alignment. It is possible to eliminate the mask alignment margin (2 x 2 = 4 n ) when forming using a photolithography process,
The element size can be reduced by 4n. therefore,
A vertical MOS FET device with a small chip area can be manufactured.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing an embodiment of the method for manufacturing a vertical MOS PET device of the present invention, and FIG. 2 is a cross-sectional view of a conventional vertical MOS PET device.
FIG. 3 is a process cross-sectional view showing a method for manufacturing an S FET device. 21... N type semiconductor substrate, 22... N type epitaxial layer, 23... P type spreading layer, 24... first polysilicon layer, 25... SiJa layer, 26... th 1 oxide film layer, 27... opening, 28... trench, 29... gate oxide film layer, 30... second polysilicon layer, 31...
... selective oxide film, 32... oxide film layer, 33... N-type spreading layer, 34... insulating oxide film layer, 35... contact hole, 36... aluminum wiring layer. An embodiment of the present invention An embodiment of the present invention No. 1! Figure Conventional manufacturing method Figure 2 Conventional manufacturing method Figure 2

Claims (1)

[Scope of Claims] (a) A second conductivity type opposite to the first conductivity type is provided on the surface portion of the first conductivity type semiconductor substrate or the surface portion of the first conductivity type epitaxial layer.
After forming a conductive type first diffusion layer, forming a first polycrystalline semiconductor layer and an oxidation-resistant film thereon in this order; (b) forming the oxidation-resistant film and the first polycrystalline semiconductor layer; (c) forming a groove in the first diffusion layer so as to reach the semiconductor substrate or the epitaxial layer through the opening after selectively forming an opening in the semiconductor layer; (d) after forming a gate insulating film layer on the inner wall, filling the trench with a second polycrystalline semiconductor layer; By selectively oxidizing the semiconductor layer, a selective oxide film in which a bird's beak is generated between the oxidation-resistant film around the trench and the first diffusion layer is formed on the surface of the second polycrystalline semiconductor layer, and at the same time, the first polycrystalline semiconductor layer is oxidized. (e) removing the selective oxide film; and (f) removing the entire surface including the surface of the first diffusion layer around the trench exposed by this removal step. (g) Thereafter, heat treatment is performed to diffuse impurities from the insulating film layer into the first diffusion layer portion around the groove. (h) forming a second diffusion layer of the first conductivity type by extending it under the remaining first polycrystalline semiconductor layer whose end portion has receded from the trench sidewall; (h) then, forming the impurity-doped insulating film; After removing the layer, forming an oxide layer on the exposed surfaces of the second polycrystalline semiconductor layer and the second diffusion layer using the oxidation-resistant film as a mask; forming a contact hole on the first and second diffusion layers by removing the film and further removing the remaining first polycrystalline semiconductor layer; (j) opening the first and second diffusion layers through the contact hole; A method for manufacturing a vertical MOSFET device, comprising the step of forming a metal wiring layer connected to a second diffusion layer.