JPH0356942A - Liquid crystal display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a liquid crystal display device, and particularly to an active matrix type liquid crystal display device using thin film transistors and the like.

[Prior Art 1] An active matrix type liquid crystal display device is one in which a nonlinear element (switching element) is provided corresponding to each of a plurality of pixel electrodes arranged in a matrix. Theoretically, the liquid crystal in each pixel is always in motion (duty ratio 1.0), so compared to the so-called simple matrix method, which uses a time-division drive method, the active method has better co-contrast, especially in color. It is becoming an indispensable technology. A typical switching element is a thin film transistor (TPT). Recently, active matrix type liquid crystal display devices have become larger, and as the size of the liquid crystal display device increases, the resistance of the common transparent pixel electrode is large, making it impossible to obtain an image according to the video signal, resulting in image deterioration. , display quality is poor. Therefore, in conventional active matrix type liquid crystal display devices, the film thickness of the common transparent pixel electrode is increased in order to reduce the resistance of the common transparent pixel electrode. Active matrix liquid crystal display devices using TPT include, for example, "12.5-inch active matrix color liquid crystal display with redundant configuration",
It is known from Nikkei Electronics, pages 193-210, December 15, 1986, published by Nikkei McGraw-Hill. [Problems to be Solved by the Invention] However, when the thickness of the common transparent pixel electrode is increased, the light transmittance of the common transparent pixel electrode decreases, the display screen becomes dark, and display quality deteriorates. This invention was made to solve the above-mentioned problems, and an object thereof is to provide a liquid crystal display device with good display quality. [Means for Solving the Problems] In order to achieve the above object, in the present invention, a lattice-shaped opaque conductive film is provided, and the opaque conductive film and the transparent conductive film are connected. Moreover, in order to achieve the above object, in this invention,
In an active matrix liquid crystal display device in which a thin film transistor and a pixel electrode constitute one element of a pixel, an opaque conductive film is provided to shield the semiconductor layer of the thin film transistor from light, and the opaque conductive film and the transparent conductive film are connected. . [Function] In this liquid crystal display device, a lattice-shaped opaque conductive film is provided to connect the opaque conductive film and the transparent conductive film, and an opaque conductive film that shields the semiconductor layer of the thin film transistor from light is provided. Since it is connected to the conductive film, even if the thickness of the transparent conductive film is reduced, the effective resistance of the transparent conductive film can be reduced.

[Embodiments] Hereinafter, the structure of the present invention will be described together with an embodiment in which the present invention is applied to an active matrix color liquid crystal display device. In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted. FIG. 1 is a plan view showing one pixel and its surroundings of an active matrix color liquid crystal display device to which the present invention is applied, and FIG. 2A is a cross section taken along the line B-JIB in FIG. 1 and the display panel. FIG. 2B is a cross-sectional view taken along the NC-NC cutting line of the construction drawing. Moreover, FIG. 3 (main part plan view) shows a plan view when a plurality of pixels shown in FIG. 1 are arranged. <Pixel Arrangement> As shown in Figure 1, each pixel is connected to two adjacent scanning signal lines (gate signal line or horizontal signal line) GL and two adjacent video signal lines (drain signal line or horizontal signal line). Vertical signal line)D
It is arranged within the area of intersection with L (within the area surrounded by the four signal lines). Each pixel includes a thin film transistor TPT, a pixel electrode ITOL, and an additional capacitor C add. The scanning signal lines GL extend in the column direction, and a plurality of scanning signal lines GL are arranged in the row direction. The video signal lines DL extend in the row direction, and a plurality of video signal lines DL are arranged in the column direction. <Overall Structure of Panel Cross Section> As shown in Figure 2A, a thin film transistor TPT and a transparent pixel electrode ITO1 are formed on the lower transparent glass substrate SUBI side with the liquid crystal ILc as a reference, and a color filter is formed on the upper transparent glass substrate SUB2 side. FIL and black matrix pattern BM for light shielding are prescribed. The lower transparent glass substrate SUBl side has a thickness of, for example, 1.1 [mm]
It is constructed with a certain thickness. The central part of Figure 2A shows a cross section of one pixel,
The left side shows a cross section of the left side forest portion of the transparent glass substrates SOB1 and SUB2 where external lead wiring is present. The right side shows a cross section of the right side portion of the transparent glass substrates SUBI and SUB2 where no external lead wiring is present. The sealing material SL shown on the left and right sides of FIG. 2A is configured to seal the liquid crystal LC, and is around the edges of the transparent glass substrates SUBI and SUB2 excluding the liquid crystal sealing opening (not shown). It is formed along the whole. The sealing material SL is made of, for example, epoxy resin. The common transparent pixel electrode IT○2 on the side of the upper transparent glass substrate FisUB2 is connected at least in one place to an external lead wiring formed on the side of the lower transparent glass substrate SUBI by a silver paste material SIL. This external lead wiring is connected to the gate electrode GT. source electrode SDI,
Drain'I1! It is formed using the same manufacturing process as each of the SD2. Orientation films ORIl and ORI2, transparent pixels @ polar ITO,
Common transparent pixel electrode ITO, protective film psv1 and PSV
2. Each layer of wA marginal membrane GI is formed inside the sealant SL. The polarizing plate POL is formed on the outer surface of each of the lower transparent glass substrate SUBI and the upper transparent glass substrate SUB2. Liquid crystal LC has a 1,000-part alignment film OR that sets the orientation of liquid crystal molecules.
II and the upper alignment film RI2, and sealed by a sealing portion SL. The lower alignment film ORII has a lower transparent glass base FfflS
A protective film PSVI is formed on the IJBI side. A light shielding film BM, a color filter FIL. Protective film PSV
2. A common transparent pixel electrode (COM) IT○2 and an upper alignment film ORI2 are sequentially laminated. In this liquid crystal display device, the layers on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side are formed separately, and then the upper and lower transparent glass substrates SUB1 and SUB2 are overlapped, and the liquid crystal LC is sealed between them. It is assembled by <Thin film transistor TPT> The thin film transistor TPT is connected to the gate 1. When a positive bias is applied to the electrode GT, the channel resistance between the source and the drain decreases, and when the bias is reduced to zero, the channel resistance increases. The thin film transistor TPT of each pixel has three
The thin film transistors (divided thin film transistors) TFT1, TFT2 and TFT3
It consists of Thin film transistor TPT1~TFT
Each of the three channels has substantially the same size (channel length and width are the same). Each of the divided thin film transistors TPTI to TFT3 mainly includes a gate electrode GT, a gate M edge film GI, and an i-type (intrinsic, int)
rinsic, i-type semiconductor RAS consisting of non-quality silicon (Si) (not doped with conductivity type-determining impurities);
It is composed of a pair of source electrode SDI and drain electrode SD2. Note that the source and drain are originally determined by the bias polarity between them, and in the circuit of this display device, the polarity is reversed during operation, so it should be understood that the source and drain are interchanged during operation. However, in the explanation below,
For convenience, one is expressed as a source and the other as a drain. <Gate Electrode GT> As shown in detail in FIG. 4 (a plan view depicting only layers g1, g2, and AS in FIG. 1), the gate electrode GT is formed in a vertical direction (in FIG. 1 and It is structured in a shape that protrudes upward (in Fig. 4) (branched into a T-shape). The gate electrode GT is configured to protrude to the respective shaped regions of the thin film transistors TPTI to TFT3. Thin film transistor TFTl-
Each gate 7M7 of TFT3. [i GT is arranged integrally (as a common gate electrode) and is formed continuously in the scanning <M line OL. The gate electrode GT is composed of a single-layer ↓th conductive film g1 so as not to form a large step in the formation region of the thin film transistor TPT. The first conductive film g1 is formed using, for example, a chromium (Cr) film formed by sputtering, and has a thickness of about 1000 mm. As shown in FIGS. 2A, 2A, and 4, the gate electrode GT is made thicker than the semiconductor WJAS so as to completely cover it (as viewed from below). Therefore, when a backlight BL such as a fluorescent lamp is installed below the substrate SUB 1, this opaque Cr gate electrode G
T forms a shadow, and the semiconductor layer AS is not irradiated with backlight light, making it difficult for the conductive phenomenon, that is, deterioration of the off-characteristics of the TPT, to occur due to light irradiation. Note that the original size of the gate electrode GT is the minimum width required to span between the source/drain electrodes SDI and SDz (including the alignment margin between the gate electrode and the source/train electrode), and the width is the minimum width needed to span between the source/drain electrodes SDI and SDz, Is the depth and length that determines W source/drain?
! It is determined by the ratio of the distance between poles (channel length) L, that is, the factor W/L that determines the mutual conductance gm. The size of the gate electrode in this embodiment is of course larger than the original size mentioned above. Considering only the gate and light shielding functions of the gate electrode GT, the gate electrode GT and the scanning signal line OL may be integrally formed in a single layer, and in this case, Si may be contained as an opaque conductive material. A1, pure Al. A1 or the like containing Pd can be selected. <<Scanning Signal Line GL>> The scanning signal line OL is composed of a composite film including a first conductive film g1 and a second conductive film g2 provided on the first conductive film g1. The first conductive film g↓ of the scanning signal line GL is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is integrally constructed. The second conductive film g2 is
For example, sputtered aluminum (AQ)
A film is used to form a film with a thickness of about 1000 to 5500 [people]. The second conductive film g2 is configured to reduce the resistance value of the scanning signal line GL and increase the signal transmission speed (improve the writing characteristics of pixel information). Further, in the scanning signal line OL, the width of the second conductive film g2 is smaller than the width of the first conductive film g1. That is, the scanning signal line GL has a gradual step shape on its side wall. <<Gate Insulating Film GI)) The insulating film GI is used as a gate insulating film of each of the thin film transistors TPTI to TFT3. Insulating film GI
is formed in the upper layer of the gate electrode GT and the scanning signal line GL. The insulating film GI is formed by, for example, plasma CVD.
Using a silicon nitride film formed by 3,000 mm thick, the film is formed to a thickness of approximately 3000 mm. <<Semiconductor Layer AS>> As shown in FIG. 4, the i-type semiconductor IAs is used as a channel forming region for each of thin film transistors TPTI to TFT3 divided into a plurality of parts. i-type semiconductor layer A
S is formed of an amorphous silicon film or a polycrystalline silicon film, and has a film thickness of about 100 g. This i-type semiconductor layer AS is made of Si by changing the supply gas.
, N4 gate is absolutely an! Continuing with the formation of IGI, it is formed in the same plasma CVD apparatus without being exposed to the outside from the apparatus. In addition, P-doped N''JldO (Figure 2A) for ohmic contact is similarly continuously formed to a thickness of about 400 [A].The lower substrate SUBI is then removed from the CvD device. The N+ layer DO and the i layer AS are taken out and photographed using photoprocessing techniques as shown in Figure ■.
It is patterned into independent islands as shown in FIGS. 2A and 4. As shown in detail in FIGS. 1 and 4, the i-type semiconductor layer AS is located at the intersection of the scanning signal line GL and the video signal line DL (
The cross-over section) is also provided between the two. This intersection i-type semiconductor layer AS receives a scanning signal Ii at the intersection.
It is designed to reduce short circuits between AGL, video signals, and IDL. <<Source/drain electrode SDI. SD2)) The source electrode SDI and drain electrode SD2 of each of the thin film transistors TPTI to TFT3 divided into a plurality of parts are shown in Fig. As shown in detail in FIG. 2, they are provided on the semiconductor layer AS at a distance from each other. Each of the source electrode SDI and drain electrode SD2 is
A first conductive film d1, a second conductive film d2, and a third conductive film d3 are sequentially stacked one on top of the other from the lower layer side in contact with the N+ type semiconductor ldo. First conductive film d of source electrode SDI
1. The second conductive film d2 and the third conductive film d3 are formed in the same manufacturing process as the drain electrode SD2. The first conductive film d1 is a chromium film formed by sputtering, and has a film thickness of 500 to 1000 [in this embodiment, 60
The film thickness is approximately 0 [A]. The thicker the chromium film, the greater the stress.
Form the film within a range that does not exceed the film thickness of A. The chromium film has good contact with the N+ type semiconductor WJ'dO. The chromium film is the second conductive film d2 described later. A so-called barrier layer is constructed to prevent aluminum from spreading to the N+ type semiconductor 1fFdO. As the Y-th conductive film d1, in addition to the chromium film, high-melting-point full-scale films (Mo.Ti, Ta.W) are used.
) film, refractory metal silicide (MoSi2, TiSi2
, TaSi2, WSi2) film. After patterning the first conductive film d1 by photo processing, N''ldO is removed using the same photo processing mask or using the first conductive film d1 as a mask.In other words, the N+ layer dO remaining on the upper layer AS is removed. The parts other than the first conductive film d1 are removed by self-line. At this time, since N"ldO is etched so that its entire thickness is removed, i/j5A,S is also etched to some extent on its surface. However, the extent can be controlled by the etch time. Thereafter, the second conductive film d2 is formed by sputtering aluminum to a thickness of 3000 to 5500 [A] (in this embodiment, a thickness of about 3500 [A]). The aluminum film has less stress than the chromium film, and can be formed to a large thickness, so that it can be used for the source electrode SDI. It is configured to reduce the resistance values of the drain electrode SD2 and the video signal line DL. The second conductive film d2 may be formed of an aluminum film containing silicon (Si) or M (CLI) as an additive, in addition to the aluminum film. After patterning the second conductive film d2 using a photoprocessing technique, a third conductive film d3 is formed. This third conductive film d3 is a transparent conductive film (Induim-T) formed by sputtering.
consists of in-Oxide ITO: Nesa membrane),
1000 to 2000 [human film thickness (in this example.
The film thickness is approximately 1200 [λ]. This third conductive film d3 constitutes a source electrode SDI, a train electrode SD2, and a video signal aDL, and also constitutes a transparent pixel electrode I.
It is designed to constitute the TOI. First conductive film d1 of source electrode SDI, train electrode SD
Each of the two first conductive films IJffdl extends further inward (into the channel region) than the upper second conductive film d2 and third conductive film d3. That is, the {th conductive film d1 in these parts is the layer d2 . The structure is such that the gate length L of the thin film transistor TPT can be defined independently of d3. Source 1! As described above, the pole SD1 is the transparent pixel electrode I.
Connected to TOI. The source electrode SD1 has a step shape in the i-type semiconductor layer AS (a step corresponding to the sum of the thickness of the first conductive film g1, the thickness of the N1 layer do, and the thickness of the i-type semiconductor layer AS). It is structured along the Specifically, the source electrode SDI is connected to a first conductive film d1 formed along the step shape of the i-type semiconductor WJAS, and a transparent pixel electrode ITO↓ above the first conductive film d1. The second conductive film d2 has a smaller size on the side to be exposed.
and a third conductive film d3 connected to the l-th conductive film d1 exposed from the second conductive film. source m
The second conductive film d2 of the pole S D 1 cannot be formed thickly due to the increase in stress because the chromium film of the first conductive film d1 cannot overcome the stepped shape of the type 1 semiconductor layer AS. It is designed to overcome the In other words, the step coverage is improved by forming the second conductive film d2 thickly. Since the second conductive film d2 can be formed thickly, it greatly contributes to reducing the resistance value of the source electrode SDI (the same applies to the drain electrode SD2 and the video signal line DL). Since the third conductive film d3 cannot overcome the step shape caused by the i-type semiconductor layer As of the second conductive film d2, by reducing the size of the second conductive film d2, the exposed first conductive film d1 is configured to connect. The first conductive film d1 and the third conductive film d3 not only have good adhesion but also have a small step shape at the connecting portion between them, so that they can be reliably connected. <<Pixel Electrode IT○1>> The transparent pixel electrode ITOI is provided for each pixel and constitutes one of the pixel electrodes of the liquid crystal display section. The transparent pixel electrode ITO1 is divided into three transparent pixel electrodes (divided transparent pixel electrodes) El, E2, and E3 corresponding to each of the thin film transistors TPTI to TFT3 divided into a plurality of pixels. Each of the transparent pixel electrodes E1 to E3 is a thin film transistor TPT.
Each of the transparent pixel electrodes E1 to E3 connected to the source electrode SDI is patterned to have substantially the same area. In this way, the thin film transistor TPT of one pixel is divided into a plurality of thin film transistors TFT↓ to TFT3, and the thin film transistor TPT1 divided into the plurality of
~Transparent pixel electrode E divided into multiple parts for each of TFT3
By connecting each of 1 to E3, even if a divided part (for example, TFTl) becomes a point defect, it is no longer a point defect when viewed from the perspective of the entire pixel (T P T 2 and T F T3 are not defective). ), it is possible to reduce the probability of point defects, and it is also possible to make defects difficult to see. Furthermore, the transparent pixel voltages hmE1 to E3 of the pixels are divided.
By configuring each of them with substantially the same area,
Each liquid crystal capacitance (C
pix ) can be made uniform. 《Protective film psv↓》 Thin I 1 helangistor TPT and transparent pixel electric Fm I
A protective film PSVI is provided on T01. The protective film PSV1 is mainly formed to protect the barrier film transistor TPT from moisture, etc., and a film with high transparency and good moisture resistance is used. The protective film PSVI is formed by, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD.
It is formed with a film thickness of about 00 [A]. <Shading 1 Sample BM> A light shielding film is provided on the upper substrate SUB Z side to prevent external light (light from above in FIG. 2A) from entering the i-type semicircular layer AS used as a channel-shaped region. A BM is provided, and the pattern is as shown by the hunting in FIG. In addition, FIG. 6 shows the IT○ film layer d3 in FIG.
FIG. 3 is a plan view depicting only a filter layer FIL and a light shielding film BM. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film, which has a high light-shielding property, and in this embodiment, the chromium film is formed by sputtering to a thickness of about 1300 μm. . Therefore, the common semiconductor IAs of TPTI~3 is sandwiched between the upper and lower light shielding films BM and the thick gate electrode GT, and that portion is not exposed to external natural light or backlight light. The light shielding film BM is formed around the pixel as shown by the hatched area in FIG. The area is partitioned. Therefore, the outline of each pixel becomes clear due to the light shielding film BM, and the contrast is improved. In other words, the light shielding film BM is
It has two functions: blocking light for the l-type semiconductor IAs and serving as a black matrix. In addition, attach the backlight to the SUB2 side, and
1 can also be set to the wl detection side (external exposure side). <<Common transparent pixel electrode IT○2>> The common transparent pixel electrode IT○2 is connected to the lower transparent glass substrate SU
Opposing the transparent pixel electrode ITOI provided for each pixel on the B1 side, the optical state of the liquid crystal changes in response to the potential difference (electric field) between each pixel electrode ITOI and the common transparent pixel electrode IT○2. A common voltage cOII1 is applied to this common transparent pixel electrode IT○2. The common voltage V can is an intermediate potential between the low level heel #J voltage V d min and the high level swelling voltage V d IIIax applied to the video signal IDL. As shown in FIGS. 2A and 6, the common transparent pixel fJ. % I T O 2 is connected to a light shielding film BM made of an opaque conductive film at a connecting portion CTT. For this reason, even if the film thickness of the common transparent pixel electrode IT○2 is reduced, the effective resistance of the common transparent pixel electrode ti 1 T O 2 can be reduced, so that the size of the liquid crystal display device can be reduced. Even so, it is possible to obtain an image according to the video signal, the image is good, and the light transmittance of the common transparent pixel electrode IT○2 does not decrease.
The display screen is bright and the display quality is good. <<Color Finoletta F Engineering L>> The color filter FIL is constructed by adding a dye to a dyed base material formed from a resin material such as Aku IJ/I/L resin. The color filter F I L is formed in a dot shape in each pixel at a position facing the pixel (Fig. 7), and is dyed differently (Fig. 7 shows the third conductive film layer d3 and the color filter in Fig. 3). It depicts only the layers F I L, R, G
, B are 45°, 135°, and cross-hatched, respectively). The color filter FIL is connected to the pixel electrode ITOI (El-E3) as shown in FIG.
It is formed thick so as to cover all of the light shielding +1i B
M is formed inside the periphery of the pixel electrode ITOI so as to overlap with the color filter FIL and the edge portion of the pixel electrode ITOI. The color filter FIL can be shaped as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter-shaped area is removed using photolithography technology. Thereafter, the dyed base material is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing similar steps. The protective film PSV2 is provided to prevent the dyes used to dye the color filter F I L into different colors from leaking into the liquid crystal LC. The protective film PSV2 is made of, for example, a transparent resin material such as acrylic resin or epoxy resin. <<Pixel Arrangement>> As shown in FIGS. 3 and 7, a plurality of pixels of the liquid crystal display section are arranged in the same column direction as the direction in which the scanning signal line GL extends, and are arranged in pixel columns XI, X2, X3. ,X4,...
It consists of each of the following. Each pixel column Xi, X2, X3
, X4, . . . have thin film transistors TFTI to TFT3 and transparent pixel electrodes E1 to E3 arranged in the same position. In other words, odd pixel row Xi
, X3, .
The arrangement positions of AE1 to E3 are arranged on the right side. Each pixel in the even numbered pixel columns X2, X4, . . . adjacent to each of the odd numbered pixel columns Xi, X3, . It is composed of pixels that are line-symmetrically repeated with respect to the extending direction of the video signal line DL. That is, pixel rows X2,
Each pixel of 4,... is a thin film transistor TF.
The arrangement position of TI-TFT3 is on the right side, transparent pixel electrode E1~
Place E3 on the left side. I am concerned about this. Then, each pixel in the pixel rows X2, X'l, . . . corresponds to the respective pixels in the pixel rows Xi, X3, .
They are shifted (shifted) by half a pixel interval in the column direction. In other words, the interval between each pixel in the pixel row X is set to 1.0 (1.0
pitch), the next pixel row X has a pixel interval of 1
．． 0, and is shifted by 0.5 pixel interval (0.5 pitch) in the column direction with respect to the previous pixel column X. The video signal line DL extending in the row direction between each pixel is configured to extend in the column direction by a half pixel interval (0.5 pitch) between each pixel column X. As a result, as shown in FIG. 7, the pixels in the previous pixel row X
The pixels on which the same color filter is formed (for example, the pixel on which the red filter R of pixel row X4 is formed) are separated by 1.5 pixel intervals (1.5 pitch), and the RGB color filter FIL It will be a triangular arrangement. The RGB triangular arrangement structure of the color filter FIL can improve the mixing of each color, and therefore can improve the resolution of a color image. Moreover, since the video signal IDL extends in the column direction by only half a pixel interval between each pixel column X, it does not intersect with the adjacent video signal IDL. Therefore, video signal line D
It is possible to eliminate the routing of L and reduce its occupied area, and it is also possible to eliminate the detour of the video signal line DL and eliminate the multilayer wiring structure. <<Equivalent circuit of entire display panel>> The equivalent circuit of this liquid crystal display device is shown in FIG. X IG + X i+ I G +... is a video signal line DL connected to the pixel in which the green filter G is formed.
It is. X x B + X i + I B +... is the video signal line D connected to the pixel in which the blue filter B is formed.
It is L. Xi+IR, Xi+2R, . . . are video signal lines DL connected to the pixels in which the red filter R is formed. These video signal lines DL are selected by the video signal 1 motion circuit. Y1 is a scanning signal line GL that selects the pixel column X1 shown in FIGS. 3 and 7. Similarly, each of Yi+1, Yi+2, . . . is a scanning signal line GL that selects each of the pixel columns X2, X3, . These scanning lines GL 13 are connected to a vertical scanning circuit. <<Structure of additional capacitance C add>> At the end of each of the transparent pixel electrodes E1 to E3 opposite to the end connected to the 1-film 1-transistor TFT,
It is bent into an L-shape so as to overlap with the adjacent scanning signal line GL. As is clear from FIG. 2B, this superposition is achieved by using a storage capacitive element (static capacitive element) C
Add to vt. The dielectric film of this storage capacitor element C add is an insulating film G used as a gate insulating film of the thin film transistor TPT.
It is constructed on the same layer as I. As is clear from FIG. 4, the storage capacitor Cadd is formed in the widened portion of the first layer g1 of the gate line GL. Note that the portion of the layer g1 that intersects with the drain line DL is made thin in order to reduce the probability of short circuit with the drain line. Each of the transparent pixel electrodes E1 to E3 and the capacitor electrode line (g
1), similarly to the source electrode %iSD1, a first conductive film d1 and a second conductive film d are provided to prevent the transparent pixel electrode IT○1 from being disconnected when going over the step shape.
An island area composed of 2 is provided. This island region is designed to be as small as possible so as not to reduce the area (aperture ratio) of the transparent pixel electrode ITO structure. <<Equivalent circuit of additional capacitance C add and its operation>> An equivalent circuit of the pixel shown in FIG. 1 is shown in FIG. 9. In FIG. 9, Cgs is the gate electrode GT of the thin film transistor TPT.
and a parasitic capacitance formed between the source electrode SDI. The dielectric film of the parasitic capacitance Cgs is an insulating film Gl. Cp
ix is a liquid crystal capacitance formed between the transparent pixel electrode IT○1 (PIX) and the common transparent pixel electrode [2IT○2 (COM)]. The dielectric film of liquid crystal capacitance C pix is liquid crystal L
C, protective film psv1 and alignment films ORII, ○RI2. Vlc is a midpoint potential. The storage capacitor element C add works to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the TFT switches. Expressing this situation using the formula, ΔV lc = {Cgs/ (Cgs+Cadd+C
pix)} becomes XΔVg. Here, ΔVlc is ΔVg
It represents the change in the midpoint position due to . This change ΔVia
causes a certain amount of direct current applied to the liquid crystal, but the retention capacity Ca
The larger +Id is, the smaller its value can be. The holding capacitor FiCadd also has the effect of lengthening the discharge time, so that video information is stored for a long time after the TPT is turned off. A certain reduction in the direct current applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce so-called burn-in, in which the previous image remains when switching liquid crystal display screens. As mentioned above, since the gate electrode GT is made large enough to completely cover the semiconductor IAS, the source/drain electrodes SDI. The overlapping area with SD2 increases, the parasitic capacitance Cgs increases, and the reverse effect occurs that the midpoint potential Vlc becomes more susceptible to the influence of the gate (scanning) signal Vg. However, by providing the holding container JiCadd, this disadvantage can also be eliminated. The storage capacitance of the storage capacitance element C add is 4 to 8 times (4.
Cpix<Cadd<8・Cpix), overlap capacitance c
8 to 32 times that of gs (LCgs<Cadd<32・
Set to a value of about Cgs>. <Connection method of additional capacitance C add electrode line> As shown in FIG. ) Connect to ITO2. As shown in FIG. 2A, the common transparent pixel electrode IT○2 is connected to an external wiring at the peripheral edge of the liquid crystal display device by means of a silver paste material SL. Moreover, the conductive MCgl and g2), which are part of the external lead wiring, are constructed in the same manufacturing process as the scanning signal line OL. As a result, the final stage capacitor electrode line GL can be easily connected to the common transparent pixel electrode TO2. Alternatively, as shown by the dotted line in FIG. 8, the final stage (first stage) capacitor electrode line OL may be connected to the first stage (final stage) scanning signal gGL. Note that this connection can be made by internal wiring within the liquid crystal display section or external wiring. <DC offset by additional capacitance C add scanning signal> This liquid product display device uses the DC offset method (D
As shown in FIG. 10 (time chart), the direct current applied to the liquid crystal LC can be further reduced by controlling the parking voltage of the scanning signal line DL. In FIG. 10, Vi is the active voltage of an arbitrary scanning signal line GL, and V i +1 is the dynamic voltage of the scanning signal line GL at the next stage. Vee is a low-level active voltage Vdmin applied to the scanning signal line GL, and Vdcl is the scanning signal v.
High level I! applied to AGL! in voltage V'dm
It is ax. Midpoint potential V at each time t=t1 to t4
The voltage change amount ΔVe~Δ■ of IC (see FIG. 9) is as follows. △V L = (C gs/C )・V 2△V
2=+(Cgs/C) {V1+V2)=(Cadd/
C)・V 2 ΔV,=-(Cgs/C)・V1 + (C add/C )' (V 1 + V 2
) ΔV, = 1 (Cadd/C)・V 1,
Total pixel capacitance: C = Cgs+ Cpix+Ca
dd Here, if the dynamic voltage applied to the scanning signal line GL is sufficient (see Note below), the DC voltage applied to the liquid crystal LC is △v3+ΔV4= (Cadd-V 2 - Cgs-
Vt)/C, so Cadd-v2=Cgs-
When v1 is set, the DC voltage applied to the liquid crystal LC is O. [Note] Is the change in scanning line Vi between times t1 and t2 the midpoint? During the period from t2 to t, the midpoint potential Vlc is set to the same potential as the video signal potential through the signal line Xi (sufficient writing of the video signal). The potential applied to the liquid crystal is almost determined by the potential immediately after the TPT is turned off (the TPT off period is overwhelmingly longer than the on period). Therefore, when calculating the DC component applied to the liquid crystal, the period t■ to t3 can be almost ignored, and the potential immediately after the TPT is turned off,
That is, it is sufficient to consider the influence during the transition at time t, L4. Note that the polarity of the video signal Vi is inverted for each frame or line, and the DC component due to the video signal itself is zero. In other words, in the DC cancellation method, the decrease due to the drawing of the midpoint potential Vlc by the superimposed capacitance Cgs is applied to the storage capacitance element C add and the next stage scanning signal line GL (capacitance electrode line).
It is possible to push up the DC current applied to the liquid crystal LC by the rotating voltage applied to the liquid crystal LC and to make it extremely small. As a result, the life of the liquid crystal LC of the liquid crystal display device can be improved. Of course, if the gate GT is increased in size to improve the light shielding effect, the value of the storage capacitor C add may be increased accordingly. As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but this invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course. For example, in this example, an inverted staggered structure is shown in which the gate electrode shape is changed to the gate insulating film shape to the semiconductor layer type or the source/drain electrode type is used. The invention is valid. [Effect of the invention 1 As explained above, in the liquid crystal display device according to the present invention, a grid-like opaque conductive film is provided, the opaque conductive film and the transparent conductive film are connected, and the semiconductor layer of the thin film transistor is shielded from light. Since an opaque 2g conductive film is provided to connect the opaque conductive film and the transparent conductive film, even if the thickness of the transparent conductive film is reduced, the effective resistance of the transparent conductive film can be reduced, so that images can be In addition to being good, the display screen is bright and the display quality is good. in this way,
The effects of this invention are remarkable.

[Brief explanation of drawings]

Fig. 2A is a plan view of a main part showing one pixel of the liquid crystal display section of an active matrix type color liquid crystal display device according to the present invention, and Fig. 2A is a section taken along the line IIB-IIB in Fig. 1. FIG. 2B is a cross-sectional view of the surrounding area of the seal portion, and FIG. 2B is a cross-sectional view taken along the NC-NC cutting line in FIG. 1. FIG. Figures 4 to 6 are plan views depicting only the predetermined layers of the pixel shown in Figure ↓ above, and Figure 7 is a superimposition of only the pixel electrode layer and color filter layer shown in Figure 3 above. FIG. 8 is an equivalent circuit diagram showing the liquid crystal display section of an active matrix color liquid crystal display device; FIG. 9 is an equivalent circuit diagram of the pixel shown in FIG. 1; FIG. 10 is a time chart showing disturbance voltage of the scanning signal line by the DC cancellation method. SUB...Transparent glass substrate GL...Scanning signal line DL...Video signal line GI...Insulating film GT...Gate electrode AS...I-type semiconductor layer SD...Source electrode or drain electrode psv ...
Protective film BM...Light shielding film LC...Liquid crystal TPT...Thin film transistor IT○...Transparent electrodes g, d...Conductive film C add...Holding capacitor element Cgs...Superposition capacitance Cpix・・LCD capacity

Claims (1)

[Scope of Claims] 1. A liquid crystal display device, characterized in that a grid-like opaque conductive film is provided, and the opaque conductive film and the transparent conductive film are connected. 2. In an active matrix liquid crystal display device in which a thin film transistor and a pixel electrode are constituent elements of a pixel, an opaque conductive film is provided to shield the semiconductor layer of the thin film transistor from light, and the opaque conductive film and the transparent conductive film are connected. A liquid crystal display device characterized by: