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JPH0353569A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0353569A
JPH0353569A JP1189622A JP18962289A JPH0353569A JP H0353569 A JPH0353569 A JP H0353569A JP 1189622 A JP1189622 A JP 1189622A JP 18962289 A JP18962289 A JP 18962289A JP H0353569 A JPH0353569 A JP H0353569A
Authority
JP
Japan
Prior art keywords
semiconductor crystal
layer
semiconductor
crystal substrate
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1189622A
Other languages
Japanese (ja)
Inventor
Susumu Yoshida
進 吉田
Hideo Matsumoto
松本 秀雄
Takao Oda
織田 隆雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1189622A priority Critical patent/JPH0353569A/en
Publication of JPH0353569A publication Critical patent/JPH0353569A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Photovoltaic Devices (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、信頼性の高い高品質な半導体結晶構造を備
えた半導体装置に関するものである.〔従来の技術〕 第3図は従来のSt半導体結晶基板上にGaAsの薄膜
を備えた半導体ウェハの断面図である.この図において
、1は厚み200μmを有するSi結晶基板等の半導体
結晶基板(熱膨張係数2.4x 1 0−’/t),2
はこの半導体結晶基板1上に形成された5μmの厚みを
有するGaAs層(熱膨張係数8.9xlO−’/t)
である。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor device having a highly reliable and high quality semiconductor crystal structure. [Prior Art] FIG. 3 is a cross-sectional view of a conventional semiconductor wafer having a GaAs thin film on a St semiconductor crystal substrate. In this figure, 1 is a semiconductor crystal substrate such as a Si crystal substrate having a thickness of 200 μm (thermal expansion coefficient 2.4 x 1 0-'/t), 2
is a GaAs layer (thermal expansion coefficient 8.9xlO-'/t) having a thickness of 5 μm formed on this semiconductor crystal substrate 1.
It is.

第4図は充電変換機能を有する半導体装置を示す断面図
である。この図において、1.2は第3図と同じもので
あり、GaAs層2は導電性の異なる2層、例えばn形
GaAs層21,動作層であるp形GaAs層22によ
り形成されている。
FIG. 4 is a sectional view showing a semiconductor device having a charge conversion function. In this figure, reference numeral 1.2 is the same as in FIG. 3, and the GaAs layer 2 is formed of two layers having different conductivity, for example, an n-type GaAs layer 21 and a p-type GaAs layer 22 which is an active layer.

動作層であるp形GaAs層22の上面および半導体結
晶基板1の裏面には電極5.6が形成されている.この
電極5.6の両端に順方向に電流を流すことにより光を
発生することができる。
Electrodes 5.6 are formed on the upper surface of the p-type GaAs layer 22, which is the active layer, and on the back surface of the semiconductor crystal substrate 1. Light can be generated by passing a current in the forward direction across both ends of this electrode 5.6.

(発明が解決しようとする課題) 上記のような熱膨張係数が約2.4X10−’/℃の半
導体結晶基板1上に、熱膨張係数が6.9xlO−’/
tのGaAs層2を備えた上記従来の半導体結晶ウェハ
では、熱膨張係数の差異により半導体結晶ウェハに応力
がかかり、反りが生じる。例えば50mmX50mmの
大きさの100μmの厚みの半導体結晶基板1上に、5
μmの厚みを有するGaAsの半導体層を形成すると、
最大2.7ma+程度の反りが発生し、GaAs結晶に
大きな応力がかかり、クラックが発生する等の問題点が
あった。
(Problem to be Solved by the Invention) On the semiconductor crystal substrate 1 having a thermal expansion coefficient of approximately 2.4×10−′/° C. as described above, a thermal expansion coefficient of 6.9×10−′/° C.
In the above-mentioned conventional semiconductor crystal wafer including the GaAs layer 2 of t, stress is applied to the semiconductor crystal wafer due to the difference in thermal expansion coefficients, causing warping. For example, on a semiconductor crystal substrate 1 with a size of 50 mm x 50 mm and a thickness of 100 μm, 5
When a GaAs semiconductor layer with a thickness of μm is formed,
There were problems such as a maximum warpage of about 2.7 ma+, a large stress being applied to the GaAs crystal, and cracks occurring.

この発明は、かかる問題点を解決するためになされたも
ので、半導体結晶ウェハの反りをなくし応力を軽減せし
め、半導体結晶基板上に形成された半導体層へのクラツ
クの発生を防止し、高品質で、かつ高信頼性の半導体装
置を得ることを目的としている。
This invention was made to solve these problems, and it eliminates warpage of semiconductor crystal wafers and reduces stress, prevents cracks from occurring in the semiconductor layer formed on the semiconductor crystal substrate, and improves quality. The objective is to obtain a highly reliable semiconductor device.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置は、半導体結晶層と同一もし
くはこれに近い熱膨張係数をもち、かつ半導体結晶層と
同一ま、たはこれと近い厚みを有する半導体層もしくは
金属層を半導体結晶基板の裏面に設けたものである。
A semiconductor device according to the present invention includes a semiconductor layer or a metal layer having a coefficient of thermal expansion that is the same as or close to that of the semiconductor crystal layer and a thickness that is the same as or close to that of the semiconductor crystal layer. It was established in

(作用) この発明においては、半導体結晶基板上に、形成された
半導体結晶層と同一またはこれに近い熱膨張係数をもち
、かつ前記半導体結晶層と同一またはこれに近い厚みを
有する半導体層もしくは金属層を前記半導体結晶基板の
裏面に形成したことから、熱膨張係数の差異による熱応
力,反りの発生が抑えられる。
(Function) In the present invention, a semiconductor layer or metal having a coefficient of thermal expansion that is the same as or close to that of the formed semiconductor crystal layer and a thickness that is the same or close to that of the semiconductor crystal layer is formed on the semiconductor crystal substrate. Since the layer is formed on the back surface of the semiconductor crystal substrate, occurrence of thermal stress and warpage due to differences in thermal expansion coefficients can be suppressed.

〔実施例〕〔Example〕

第1図はこの発明による半導体結晶ウェハの断面図を示
す。この図で、1は200μmの厚みを有するSt単結
晶基板等の半導体結晶基板であり、2は有機金属エビタ
キシャル法(Metal Org−anic Chem
ical Vapor Deposition;M O
 C V D ) ,液相エピタキシャル法あるいは気
相エビタキシャル法等によって半導体結晶基板1上に形
成されたGaAs層である。3は前記半導体結晶基板1
の裏面に形成された前記GaAs層2と同一またはこれ
に近い熱膨張係数と厚みを有するGe層である. 半導体結晶基板1の裏面にGaAs層2と同一またはこ
れに近い熱膨張係数と厚みを有するGe層3を、真空蒸
着あるいはゲルマン(GeH4)の熱分解法あるいはG
eのハロゲン化合物の水素還元法(電気化学協会、電子
材料委員会編、半導体材料)によって形成する。次に、
Ge層3を備えた半導体結晶基板1の表面にトリメチル
ガリウムとアルシンの反応 Ga (CH3) ,+ A.H,→GaAs + 3
CH4を用いたMOCVD法によって約750℃の成長
温度でGaAs層2を5μm形成する.従来例では、半
導体結晶基板1上にGaAs層2を3μm以上形成する
と、GaAsとSiの熱膨張係数の差異(GaAs :
 6.9x 1 0−”/’e,S i : 2.6X
 1 0−’/’e)によりGaAs層2に大きな熱応
力が発生し、反り.クランクが生じる問題点があったが
、この発明Cよる半導体結晶基板1の裏面に形成された
Ge層3は、熱膨張係数が5.9X10−″6/−cと
GaAsに近く、半導体結晶基板1上のGaAs層2の
反りは大きく減少しほぼ平坦になり、半導体結晶基板1
上のGaAs層2のクラックを防ぎ、高品質で、かつ信
頼性の高い半導体結晶ウェハを得ることができる。
FIG. 1 shows a cross-sectional view of a semiconductor crystal wafer according to the invention. In this figure, 1 is a semiconductor crystal substrate such as an St single crystal substrate having a thickness of 200 μm, and 2 is a semiconductor crystal substrate such as a St single crystal substrate having a thickness of 200 μm, and 2 is a semiconductor crystal substrate using an organic metal epitaxial method (Metal Org-anic Chem
ical Vapor Deposition; M O
This is a GaAs layer formed on the semiconductor crystal substrate 1 by C V D ), liquid phase epitaxial method, gas phase epitaxial method, or the like. 3 is the semiconductor crystal substrate 1
This is a Ge layer having the same or similar thermal expansion coefficient and thickness as the GaAs layer 2 formed on the back surface of the . A Ge layer 3 having the same or similar thermal expansion coefficient and thickness as the GaAs layer 2 is formed on the back surface of the semiconductor crystal substrate 1 by vacuum evaporation, germane (GeH4) thermal decomposition method, or G
It is formed by the hydrogen reduction method of halogen compounds (Electrochemical Society of Japan, Electronic Materials Committee, Semiconductor Materials). next,
A reaction between trimethyl gallium and arsine Ga (CH3) , + A. H,→GaAs + 3
A GaAs layer 2 of 5 μm thickness is formed at a growth temperature of about 750° C. by MOCVD using CH4. In the conventional example, when a GaAs layer 2 of 3 μm or more is formed on a semiconductor crystal substrate 1, the difference in thermal expansion coefficient between GaAs and Si (GaAs:
6.9x 1 0-”/'e, S i : 2.6X
10-'/'e), a large thermal stress is generated in the GaAs layer 2, causing warping. Although there was a problem that cranking occurred, the Ge layer 3 formed on the back surface of the semiconductor crystal substrate 1 according to invention C has a thermal expansion coefficient of 5.9X10-''6/-c, which is close to GaAs, and the semiconductor crystal substrate The warpage of the GaAs layer 2 on the semiconductor crystal substrate 1 is greatly reduced and becomes almost flat.
Cracks in the upper GaAs layer 2 can be prevented, and a high quality and highly reliable semiconductor crystal wafer can be obtained.

第2図はこの発明の一実施例を示す半導体装置の断面図
で、第1図の半導体結晶ウェハを用いたGaAsのpn
接合を有する発光ダイオードの断面構造を示すものであ
る。
FIG. 2 is a sectional view of a semiconductor device showing an embodiment of the present invention, in which a GaAs pn using the semiconductor crystal wafer of FIG. 1 is shown.
1 shows a cross-sectional structure of a light emitting diode having a junction.

第2図において、半導体結晶基板1はn形の(100)
面方位を有する200μmの厚みを有する。GaAs層
2は、例えばMOCVD法によって形成された5μmの
厚みを有する。また、n形の不純物濃度は1 x 1 
0 ”cm−3である。4は前記GaAs層2に亜鉛(
Zn)の封止拡散によって形成された1.5μmの拡散
深さを有するp−GaAsの拡散層である。3は前記n
−GaAs層2と同じ膜厚を有するGe層であり、5.
6は電極を示す。
In FIG. 2, the semiconductor crystal substrate 1 is an n-type (100)
It has a thickness of 200 μm and has a plane orientation. The GaAs layer 2 has a thickness of 5 μm and is formed by MOCVD, for example. Also, the n-type impurity concentration is 1 x 1
0"cm-3. 4 is the amount of zinc (
This is a p-GaAs diffusion layer with a diffusion depth of 1.5 μm formed by sealing diffusion of Zn). 3 is the above n
- a Ge layer having the same thickness as the GaAs layer 2; 5.
6 indicates an electrode.

この発明による半導体結晶基板1上に形成された発光ダ
イオードの機能を有する半導体装置は、半導体結晶ウェ
ハに反りが発生せず平坦であるため、発光ダイオードの
ウェハ内の輝度のばらつきが小さくなり、高品質の半導
体装置を得ることができる。また、反りによる工程中で
のクラックの発生がなくなり、高信頼性の半導体装置を
得ることができる。
In the semiconductor device having the function of a light emitting diode formed on the semiconductor crystal substrate 1 according to the present invention, since the semiconductor crystal wafer is flat without warping, variations in brightness within the wafer of the light emitting diode are reduced and high A high quality semiconductor device can be obtained. Furthermore, cracks during the process due to warping are eliminated, and a highly reliable semiconductor device can be obtained.

なお、上記実施例では、半導体結晶基板1の裏面にGe
層3を備えた半導体結晶基板1上に、GaAs層2を有
する半導体結晶ウェハおよびその半導体装置の一例とし
て発光ダイオードの場合について述べたが、半導体装置
としてはFET(電界効果形トランジスタ)をはじめと
する電子デバイスや、太陽電池.レーザダイオードなど
受光・発光ダイオードにとどまらず、GaAs I C
や光集積回路等があげられる。
Note that in the above embodiment, Ge is deposited on the back surface of the semiconductor crystal substrate 1.
A light emitting diode has been described as an example of a semiconductor crystal wafer having a GaAs layer 2 on a semiconductor crystal substrate 1 having a layer 3 and a semiconductor device thereof. electronic devices and solar cells. In addition to light-receiving and light-emitting diodes such as laser diodes, GaAs IC
and optical integrated circuits.

また、半導体結晶基板1の裏面材料としてGeの場合に
ついて述べたが,GeでなくGaAS層2と熱膨張係数
の類似した金属、例えばタングステン.カーボン.タン
タル等の金属であってもよい。もちろん、同一厚みのG
aAs層をつけても効果のあることはもちろんである。
In addition, although the case where Ge is used as the back surface material of the semiconductor crystal substrate 1 has been described, instead of Ge, a metal having a coefficient of thermal expansion similar to that of the GaAS layer 2, such as tungsten, is used. carbon. It may also be a metal such as tantalum. Of course, G with the same thickness
Of course, adding an aAs layer is also effective.

さらに、半導体結晶基板1上の半導体結晶層としてGa
As層2を形成する場合について述べたが、GaAs以
外の化合物半導体であるInP,GaP,あるいはGa
Asの混晶化合物半導体.GaAjlAs,GaAsP
等についても適用できることはいうまでもない。
Furthermore, Ga is used as a semiconductor crystal layer on the semiconductor crystal substrate 1.
Although the case of forming the As layer 2 has been described, compound semiconductors other than GaAs such as InP, GaP, or Ga
As mixed crystal compound semiconductor. GaAs, GaAsP
Needless to say, this can also be applied to other matters.

〔発明の効果〕〔Effect of the invention〕

この発明は、以上説明したように、半導体結晶層と同一
もしくはこれに近い熱膨張係数をもち、かつ半導体結晶
層と同一またはこれと近い厚みを有する半導体層もしく
は金属層を半導体結晶基板の裏面に設けたので、半導体
結晶ウェハの反りをなくし、半導体結晶基板上に形成さ
れた半導体結晶層のクラック発生を防止し、高品質、か
つ高信頼性の半導体装置を得ることができる効果がある
As explained above, the present invention provides a semiconductor layer or a metal layer having the same or similar thermal expansion coefficient as the semiconductor crystal layer and the same or similar thickness as the semiconductor crystal layer on the back surface of the semiconductor crystal substrate. This has the effect of eliminating warping of the semiconductor crystal wafer, preventing cracks in the semiconductor crystal layer formed on the semiconductor crystal substrate, and obtaining a high quality and highly reliable semiconductor device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明に適用する半導体結晶ウェハの断面図
、第2図は、第1図の半導体結晶ウェハを用いたこの発
明の半導体装置の一実施例を示す断面図、第3図.第4
図は従来の半導体結晶ウェハおよび半導体装置の断面図
をそれぞれ示す。 図において、1は半導体結晶基板、2はGaAs層、3
はGe層、4は拡散層、5.6は電極である。 なお、各図中の同一符号は同一または相当部分を示す。
1 is a cross-sectional view of a semiconductor crystal wafer to which the present invention is applied, FIG. 2 is a cross-sectional view showing an embodiment of a semiconductor device of the present invention using the semiconductor crystal wafer of FIG. 1, and FIG. Fourth
The figures show cross-sectional views of a conventional semiconductor crystal wafer and a conventional semiconductor device, respectively. In the figure, 1 is a semiconductor crystal substrate, 2 is a GaAs layer, and 3 is a semiconductor crystal substrate.
is a Ge layer, 4 is a diffusion layer, and 5.6 is an electrode. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims]  半導体結晶基板上にこの半導体結晶基板と熱膨張係数
の異なる半導体結晶層を有する半導体結晶ウェハを用い
た半導体装置において、前記半導体結晶ウェハの半導体
結晶層と同一もしくはこれに近い熱膨張係数をもち、か
つ前記半導体結晶層と同一またはこれと近い厚みを有す
る半導体層もしくは金属層を前記半導体結晶基板の裏面
に設けたことを特徴とする半導体装置。
In a semiconductor device using a semiconductor crystal wafer having, on a semiconductor crystal substrate, a semiconductor crystal layer having a coefficient of thermal expansion different from that of the semiconductor crystal substrate, having a coefficient of thermal expansion that is the same as or close to that of the semiconductor crystal layer of the semiconductor crystal wafer, A semiconductor device further comprising: a semiconductor layer or a metal layer having a thickness the same as or close to that of the semiconductor crystal layer, provided on the back surface of the semiconductor crystal substrate.
JP1189622A 1989-07-20 1989-07-20 Semiconductor device Pending JPH0353569A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1189622A JPH0353569A (en) 1989-07-20 1989-07-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1189622A JPH0353569A (en) 1989-07-20 1989-07-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0353569A true JPH0353569A (en) 1991-03-07

Family

ID=16244381

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1189622A Pending JPH0353569A (en) 1989-07-20 1989-07-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0353569A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010099544A3 (en) * 2009-02-27 2011-01-13 Alta Devices, Inc. Tiled substrates for deposition and epitaxial lift off processes
JP2012044115A (en) * 2010-08-23 2012-03-01 Fujitsu Ltd Method of manufacturing semiconductor device, and semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010099544A3 (en) * 2009-02-27 2011-01-13 Alta Devices, Inc. Tiled substrates for deposition and epitaxial lift off processes
JP2012044115A (en) * 2010-08-23 2012-03-01 Fujitsu Ltd Method of manufacturing semiconductor device, and semiconductor device

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