JPH03502389A - Integrated circuits with means to reduce electrostatic damage - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Mouth that caused Hair Emperor 11 1. Field of invention The invention includes a substrate carrying a large number of transistors and similar circuit elements. related to integrated circuits.

In particular, the invention provides an integrated circuit having means for reducing damage as a result of electrostatic discharge. Regarding.

2. Conventional technology It is well known that integrated circuits can be seriously damaged or destroyed as a result of electrostatic discharge. It is. Electrostatic voltages associated with electrical discharges can occur from many sources such as lightning or synthetic fabric coverings. This may occur due to friction between insulators such as insulation. Electrostatic discharge voltage is even Naturally, when combined with one circuit terminal, and therefore part of the metal interconnect layer of an integrated circuit, Damage occurs.

Metal interconnects are typically aluminum formed on an oxide layer on top of the semiconductor. layer. Electrostatic discharge voltage transfers current from the gold layer to the normally non-conducting oxide. It flows through the film to the semiconductor underneath. This current is then collected through other circuit terminals. exit from the product circuit. This current is in particular caused by making the oxide permanently conductive. is strong enough to often cause significant damage to the oxide. As a result All shunts often result in circuit failure.

Various attempts have been made to prevent damage from electrostatic discharge. For example, MOS transistor Semiconductor elements that require thin oxides, such as MOS capacitors and MOS capacitors, Often by an additional device that bypasses the discharge current and protects the semiconductor element. Often protected. Generally, separate bypass devices are used to achieve the desired protection for each element. must be used for. However, in certain special cases such guarantees may A protection device can share the desired protection of one or more elements. In any case However, the provision of protective devices to prevent damage from electrostatic discharge is a In addition to the complexity of the circuit, it requires additional integrated circuit area and is generally not at all desirable. This is a bad method.

Many integrated circuits use bipolar transistors, for example, as opposed to MOS transistors. Made of semiconductor elements that do not require thin oxides such as transistors. Regardless of that Instead, these integrated circuits go through special processing steps that result in a thin oxide in place. normal or completely or nearly completely removed Having a thermal oxide makes it susceptible to damage from electrostatic discharge. The present invention The need to use certain protection devices by conventional means while using product circuits This excludes

Excretion B November An important characteristic of the present invention is that the overall thickness of the dielectric coating between the substrate and metal interconnects is The breakdown voltage passing through the insulator is more reliable than the breakdown voltage at the junction formed within the substrate. The idea is to make it large enough to actually grow. By doing this, you can When an electric discharge occurs with sufficient strength to cause breakdown, this breakdown occurs in the insulation coating. occurs at the junction without passing through. Since damage to the joint is self-healing, Damage to the integrated circuit may be caused by It's not permanent.

A second important characteristic of the invention is that the thick insulating coating on the substrate is at least partially bonded. A low temperature (LT) dielectric material is deposited after the formation of the part. relatively low temperature The adhesion of moss does not cause any harmful changes to the joints that have already been formed.

In one preferred embodiment of the invention, detailed below, the insulating coating of the substrate is made of gold. An integrated circuit structure is provided that consists of two adjacent layers directly below a genus interconnect. . The first layer film is a conventional processing film formed at relatively high temperatures during conventional integrated circuit processing. It is thermally grown silicon dioxide. The second layer is silicon dioxide deposition obtained at a relatively low temperature. layer where the temperature is low enough that the junctions already formed in the integrated circuit are No harmful changes occur during deposition of the oxide.

In another embodiment of the invention, a thermally grown acid formed during conventional integrated circuit processing is used. The compound is a low temperature insulating coating of a thickness that sufficiently minimizes the potential for electrostatic discharge damage of the present invention. partially or completely in at least selected areas of the substrate before it is deposited. removed.

Other objects, features and advantages of the invention may be found in part in the following detailed description taken in conjunction with the drawings. as will be pointed out and partially clarified from such detailed description.

51 Tomo Figure 1 is a vertical cross-sectional view of an integrated circuit chip, but is not drawn to scale (although some Characteristics are illustrated pictorially, and Figure 2 shows various elements of the integrated circuit chip in Figure 1. A schematic diagram, FIG. 3 is a graph that helps explain the invention in detail.

A memorable 9th day First, in FIG. 1, the substrate is typically made of silicon and is illustrated as a p-type substrate. An integrated circuit (IC) is shown that includes lo. This substrate can be manufactured using chemical vapor deposition (CVD) or is provided with n-type impurities by conventional techniques, such as ion implantation. these impurities The material is placed in the substrate so as to create an n-shaded area 12 forming a junction 14 with the p-type substrate material. Injected (spread). Diode symbol 16 illustrates the electrical characteristics of the junction This is illustrated in the joint for this purpose.

Diodes that share circuit elements with specific IC devices as well as typical ICs and a number of other junctions (not shown) forming the transistor. these Other joints are not shown here for the sake of brevity.

While forming the various junctions across the substrate IO, a silicon dioxide material such as 20 is used. A protective insulating dielectric layer such as this is thermally grown on the surface of the substrate in a known manner. This layer is good Preferably, it is formed at a relatively high temperature of 700°C or higher. In such growth, pure 02 (oxygen) in gaseous form or as part of water vapor (H2O) is present on the substrate It combines with silicon atoms from to form silicon dioxide (S102). This addition Thermal grown oxide portions are implanted and/or diffused during the fabrication of many IC junctions. This oxide layer 20 may need to be removed in various cases as part of the process. The final thickness varies widely from location to location, as shown in FIG.

According to the prior art, a metallization layer, typically shown at 22, is deposited on selected surfaces of the substrate. It is coated directly onto the heated oxide 20 to make electrical connection to the region. This way For devices formed in this way, the electrostatic discharge (E SD) Excessive sensitivity to voltage is experienced. This ESD voltage 1 by a voltage source 24, indicated by the symbol, with one terminal connected to is shown connected to metallization layer 22 with the other terminal connected to ground. .

Excessive susceptibility to ESD in such conventional IC configurations has led to novel IC configurations, and suppressed or significantly reduced by IC manufacturing methods such as those described below. Reduced. In this novel configuration, an additional layer of oxide 26 is added to the metallization 22. It is deposited directly below and, in this example, above the thermally grown layer 20 . but However, unlike the first layer 20, this additional layer is formed at a relatively low temperature (below 700°C). be done. The significance of this difference is that by adding low temperature (LT) oxides, Ensure that the addition of this layer does not adversely affect the joints already formed on the board. Ru.

The additional layer 2G has a thickness such that the total thickness of the oxides (20, 26) is sufficient. The breakdown voltage of the dielectric material between the substrate and the metallization layer 22 is VD8KD) is the IC junction breakdown voltage (VJ9KD), in this example, the junction breakdown voltage (VJ9KD) 14. Figure 2 shows that the ESD source 24 is virtually minimally destructive. Voltage dielectric region (i.e. when the dielectric is very thin like capacitor 30) and a minimum breakdown voltage junction (for example, diode 16) in parallel combination. Illustrating how it is done. ESD reaches sufficient levels to cause destruction In this case, the breakdown in the present invention occurs at the junction (for example, diode 1G) and the capacitor This does not occur in the dielectric material (20, 2G) of the sensor 30.

This can be illustrated graphically with reference to Figure 3, which shows the current-voltage (I-V) coordinates. and solid curve 36 as shown by combination coating 20.2G. Corresponding to the dielectric material layer, the dotted curve 38 corresponds to a junction such as the diode 16. Ru.

As shown by the solid curve 36, the current in the dielectric increases with the breakdown voltage V It gradually increases as the voltage increases until reaching D B K is overrepresented). At this point, the current increases rapidly and the voltage is very low (represents something close to a short circuit exhibited by the dielectric material after breakdown) .

By providing an addition oxide film (i.e., the low temperature oxide adhesion layer described above) (2B)), the magnitude of the dielectric breakdown voltage V D B K D increases compared to the breakdown voltage due to only the thermally grown layer (20). Actual dielectric breakdown The voltage is given (somewhat conservatively) by the following relation:

■D8゜=　(0,0B　Nert/Onk° Strom) (Onk° Strom) Therefore, a thickness of 10,000 angstroms is approximately 600 volts thick. Protect against ESD. As a rare exception, all IC junctions are rated at 600 volts. Destroys at voltage below .

The breakdown voltage Vnexn of the final dielectric film (20,2G) is shown in the graph in Figure 3. Junction breakdown voltage V J II K D shown by the vertical dotted line in the first quadrant of Preferably, it is made thick enough to be larger than the Thus, positive E When the SD voltage is applied, breakdown occurs first at the junction (e.g. junction 14) and then This prevents breakdowns from occurring in the dielectric material. Failure of such joints is self-healing. (i.e., this breakdown returns to working condition after a short time) Damage to the IC is not permanent due to the discharge. When a negative ESD voltage is applied, the diode A voltage is applied to the node 16 in the forward direction, and the voltage is much lower than the dielectric breakdown voltage of the oxide. conducts current and thus protects the oxide in the same way.

The low temperature oxide coating can be applied in a variety of ways prior to forming the metallization.

Typically chemical vapor deposition (CVD) is used. For example, silane gas (SI) HJ) is flowed over the wafer with oxygen to form silicon dioxide.

Sputtering can also be used. other material sources and oxidants, For example, tetraethylorthosilicate and nitrous oxide can be used. Ru. In each case, the silicon for the low temperature 5i02 coating is supplied externally, i.e. Silicon cannot be obtained from the substrate because it is grown together with thermally grown (high temperature) oxides. . Additional layers prevent junctions in already formed ICs from being adversely affected due to additional processing. It is deposited at temperatures below 700°C to avoid damage.

In the particularly preferred embodiments described above, the substrate comprises multiple oxide coatings and one The layer is a high temperature (HT) layer adjacent to the substrate, and the other layers are immediately below the metallization layer. It is a low temperature (LT) layer. However, the concept of the present invention reduces the overall breakdown voltage. A low and high dielectric insulator on the substrate with sufficient thickness that the voltage is greater than the junction breakdown voltage. It should be understood that the purpose is to attach the In some cases, low temperature (LT) insulation coatings The high temperature oxide may be partially or completely removed in at least some locations prior to deposition of the In this case, the LT film must be thick enough to obtain the required dielectric breakdown voltage. No.

Thus, while particularly preferred embodiments of the invention have been described in detail, the foregoing description has been illustrative of the invention. However, without departing from the scope of the invention, one skilled in the art will be able to It should not necessarily be construed in a restrictive manner, as many modifications are possible.

FIG. 2 international search report

Claims (8)

[Claims] 1. Semiconductor substrate with selected regions having impurities forming at least one junction a plate, with metal interconnects affixed to the at least one substrate; a dielectric insulator between the metal interconnect and a surface of the substrate; In order to reduce damage to said integrated circuit due to electrostatic discharge, In order to an improved integrated circuit containing at least one layer of low temperature dielectric material of sufficient thickness to . 2. the dielectric insulator is in two layers, one a hot-grown layer and the other a cold-deposited layer; 2. An integrated circuit as claimed in claim 1, comprising: 3. Claim 1, wherein the substrate is made of silicon and the dielectric is silicon dioxide. The integrated circuit described in . 4. A method of manufacturing an integrated circuit that resists damage from electrostatic discharge, supplying impurities to the semiconductor substrate to form at least one junction; growing a high temperature dielectric on the substrate as part of an integrated circuit formation process; The substrate has a dielectric breakdown voltage greater than the breakdown voltage of the junction. depositing a low temperature dielectric layer of sufficient thickness to provide a dielectric material having a A layer of metal interconnects is formed on the electrical layer to connect the junctions and other parts of the IC. A method of manufacturing an integrated circuit comprising the step of making an electrical connection with a region. 5. The dielectric material on the substrate has two layers, one a high temperature dielectric layer and the other a high temperature dielectric layer. a low temperature dielectric layer formed on a high temperature dielectric layer, wherein the two layers Claims having a total thickness sufficient to produce a dielectric breakdown voltage greater than the voltage The method according to scope 4. 6. The first layer is grown by heating at a temperature of 700°C or higher, and the second layer is grown at a temperature of 700°C or higher. 6. The method of claim 5, wherein the method is deposited at a temperature of: 7. 5. The method of claim 4, wherein the low temperature dielectric is deposited by chemical vapor deposition. . 8. 5. The method of claim 4, wherein the low temperature dielectric is deposited by sputtering. Method.