JPH0349482Y2 - - Google Patents
Info
- Publication number
- JPH0349482Y2 JPH0349482Y2 JP2317085U JP2317085U JPH0349482Y2 JP H0349482 Y2 JPH0349482 Y2 JP H0349482Y2 JP 2317085 U JP2317085 U JP 2317085U JP 2317085 U JP2317085 U JP 2317085U JP H0349482 Y2 JPH0349482 Y2 JP H0349482Y2
- Authority
- JP
- Japan
- Prior art keywords
- tuning circuit
- circuit
- input
- agc
- capacitance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005684 electric field Effects 0.000 claims description 15
- 230000009977 dual effect Effects 0.000 claims description 3
- 230000003321 amplification Effects 0.000 claims description 2
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 description 13
- 230000007423 decrease Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
Landscapes
- Television Receiver Circuits (AREA)
- Superheterodyne Receivers (AREA)
- Noise Elimination (AREA)
- Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
Description
【考案の詳細な説明】
(イ) 産業上の利用分野
本考案はテレビジヨン受像機等に使用される電
子チユーナに関する。[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to an electronic tuner used in television receivers and the like.
(ロ) 従来の技術
テレビジヨン受像機には一般に高周波のAGC
増幅回路を有し入力同調型と称される第2図の如
き構成の電子チユーナが従来より賞用されてい
る。即ち、第2図に於いて、1は入力端子、2は
入力フイルタ回路、3は同調素子に可変容量ダイ
オードD1を使用した入力同調回路、4は増幅素
子にデユアルゲートFET(T)を使用したAGC
(自動利得制御)増幅回路、5は可変容量ダイオ
ードD2,D3を使用した段間同調回路、6は局部
発振回路、7は混合回路、8はIF(中間周波数)
同調用の可変インダクタンスLとコンデンサC4
及び受像機内のVIF(映像中間周波数)段へのマ
ツチング用のコンデンサC5,C6と抵抗R6からな
る出力同調回路、9は出力端子である。(b) Conventional technology Television receivers generally use high-frequency AGC.
2. Description of the Related Art An electronic tuner having an amplifying circuit and having a configuration as shown in FIG. 2, which is called an input tuning type, has been used in the past. That is, in Figure 2, 1 is an input terminal, 2 is an input filter circuit, 3 is an input tuning circuit using a variable capacitance diode D1 as a tuning element, and 4 is a dual gate FET (T) used as an amplification element. AGC
(Automatic gain control) amplifier circuit, 5 is an interstage tuning circuit using variable capacitance diodes D2 and D3, 6 is a local oscillation circuit, 7 is a mixing circuit, 8 is IF (intermediate frequency)
Variable inductance L and capacitor C4 for tuning
and an output tuning circuit consisting of capacitors C5 and C6 and a resistor R6 for matching to the VIF (video intermediate frequency) stage in the receiver; 9 is an output terminal.
前記AGC増幅回路4はFET(T)の第1ゲート
G1に前記入力同調回路5で選択された受信信号
が印加され、第2ゲートG2には制御端子9に与
えられるAGC制御電圧が抵抗R3を介して印加さ
れ、ドレインDからの出力信号が結合コンデンサ
C3を介して前記段間同調回路5に与えられるよ
うになつている。なお、R1,R2は第1ゲートG1
のバイアス抵抗、C1は第1ゲートG1の入力容量
補正用コンデンサ、C2は第2ゲートG2のバイパ
スコンデンサ、R4はドレイン負荷抵抗、R5,C8
はソース抵抗及びそのバイパスコンデンサ、10
は電源(+VCC)端子である。 The AGC amplifier circuit 4 is the first gate of FET (T)
The received signal selected by the input tuning circuit 5 is applied to G1, the AGC control voltage given to the control terminal 9 is applied to the second gate G2 via the resistor R3, and the output signal from the drain D is applied to the coupling capacitor.
The signal is applied to the interstage tuning circuit 5 via C3. Note that R1 and R2 are the first gate G1
bias resistor, C1 is the input capacitance correction capacitor for the first gate G1, C2 is the bypass capacitor for the second gate G2, R4 is the drain load resistor, R5, C8
is the source resistance and its bypass capacitor, 10
is the power supply (+VCC) terminal.
ここで、FET(T)の第2ゲートG2へのAGC
制御電圧VGは、通常、約0.5V(強電界受信時)
〜7V(弱電界受信時)程度の範囲で変化するよう
になつているが、一般に知られているようにゲー
トへの印加電圧に応じてFETの入力容量が変化
するので、第2図の回路では上記第1ゲートG1
と接地点間に等価的に示される入力容量Coが変
化することになる。即ち、本考案者の実測に依れ
ば、上記容量Coの値はAGC制御電圧VGが7V時
は約4PFであるのに対して0.5V時は約3.2PFであ
つた。このように入力容量Coが変化すると、こ
の容量は入力同調回路3の可変容量ダイオード
D1(変化範囲2〜12PF程度)に並列に入つてい
るので、上記同調回路3の周波数特性を大きく変
させることになる。 Here, AGC to the second gate G2 of FET (T)
Control voltage VG is usually about 0.5V (when receiving strong electric field)
It is designed to vary in the range of ~7V (when receiving a weak electric field), but as is generally known, the input capacitance of the FET changes depending on the voltage applied to the gate, so the circuit shown in Figure 2 Now, the first gate G1 above.
The input capacitance Co equivalently shown between and the ground point will change. That is, according to actual measurements by the present inventor, the value of the capacitance Co was about 4PF when the AGC control voltage VG was 7V, but about 3.2PF when the AGC control voltage VG was 0.5V. When the input capacitance Co changes in this way, this capacitance changes to the variable capacitance diode of the input tuning circuit 3.
Since it is connected in parallel to D1 (variation range of about 2 to 12 PF), the frequency characteristics of the tuning circuit 3 will be greatly changed.
例えば、弱電界受信時(VG=7V時)には上記
入力同調回路3の周波数特性は第3図aのように
なり、同図bに示す中電界受信状態での正常な場
合に比較すると、映像キヤリア周波数点Pでの利
得が音声キヤリア周波数点S及びカラーサブキヤ
リア周波数点Cでのそれよりも相当大きくなる。 For example, when receiving a weak electric field (when VG = 7V), the frequency characteristics of the input tuning circuit 3 become as shown in Figure 3a, and when compared with the normal case in the medium electric field receiving state shown in Figure 3b, The gain at the video carrier frequency point P is considerably larger than that at the audio carrier frequency point S and the color subcarrier frequency point C.
逆に強電界受信時(VG=0.5V時)には同図c
のようになつて、上記P.S点での利得の大小関係
(P,S点の利得の比を以後P/S比と称する)
が逆転する。そして、この第3図a又はcの特性
の信号が、混合回路7でIF信号に変換されて出
力同調回路8を通つても略元のP/S比を保つた
まゝ、受像機内のVIF回路に与えられる場合に
は、次のような問題が生じることになる。即ち、
一般の受像機ではインタキヤリア方式の音声復調
を採用しているため、第3図aの場合には映像信
号の影響が大きくなつて音声信号中にバズが発生
しやすくなり、逆に同図cの場合には音声キヤリ
ア信号の影響が大きくなつて映像信号に対して音
声ビートやカラビート等のビート妨害を与えるこ
とになる。 On the other hand, when receiving a strong electric field (when VG = 0.5V), the same figure c
The magnitude relationship of the gains at the PS point is as follows (the ratio of the gains at the P and S points is hereinafter referred to as the P/S ratio)
is reversed. Then, the signal having the characteristics shown in FIG. If it is given, the following problems will arise. That is,
Since general TV receivers use intercarrier audio demodulation, in the case shown in Figure 3a, the influence of the video signal becomes large and buzz is likely to occur in the audio signal, and conversely, in the case shown in Figure 3c In this case, the influence of the audio carrier signal becomes large, causing beat interference such as audio beats and color beats to the video signal.
そこで、従来は例えば実開昭48−35252号公報
に示されるように、前述の入力容量補正用コンデ
ンサc1(5PF程度)を設けることによつて、入力
容量Coの変化を等価的に小さくするようにして
いた。その際、この補正用コンデンサC1の容量
値を大くすればするほど補正効果を大きくできる
が、その場合には入力同調回路3の可変同調範囲
が著しく狭くなると云う欠点があつた。 Therefore, as shown in Japanese Utility Model Application Publication No. 48-35252, conventional methods have been used to equivalently reduce the change in input capacitance Co by providing the aforementioned input capacitance correction capacitor c1 (approximately 5PF). I was doing it. At this time, the larger the capacitance value of the correction capacitor C1, the greater the correction effect, but in that case there was a drawback that the variable tuning range of the input tuning circuit 3 was significantly narrowed.
(ハ) 考案が解決しようとする問題点
本考案は上記の点を考慮してなされたものであ
り、チユーナのAGC増幅回路に起因するIF出力
信号のP/S比変化を確実に補正でき、しかも、
それによつて入力同調回路の可変同調範囲が何等
変更されないようにすることを目的とする。(c) Problems to be solved by the invention The present invention was made in consideration of the above points, and can reliably correct the P/S ratio change of the IF output signal caused by the tuner's AGC amplifier circuit. Moreover,
The purpose is to prevent the variable tuning range of the input tuning circuit from being changed in any way.
(ニ) 問題点を解決するための手段
本考案では、IF出力信号を導出するチユーナ
の出力同調回路の同調素子に可変容量素子を使用
し、この素子の容量をチユーナ内のAGC増幅回
路に印加するAGC制御信号に応じて変化させる
ようにしている。(d) Means for solving the problem In this invention, a variable capacitance element is used as the tuning element of the output tuning circuit of the tuner that derives the IF output signal, and the capacitance of this element is applied to the AGC amplifier circuit in the tuner. It is designed to change according to the AGC control signal.
(ホ) 作用
上記構成に於いて、出力同調回路の周波数特性
が入力同調回路の周波数特性の変化方向と逆方向
に変化するように、前記可変容量素子の容量を変
化させることによつて、チユーナ出力のP/S比
が受信電界強度に拘わらず略一定になるよう制御
されるる。(E) Effect In the above configuration, the tuner is controlled by changing the capacitance of the variable capacitance element so that the frequency characteristics of the output tuning circuit change in the opposite direction to the changing direction of the frequency characteristics of the input tuning circuit. The output P/S ratio is controlled to be substantially constant regardless of the received electric field strength.
(ヘ) 実施例
第1図は本考案チユーナの一実施例を示してお
り、第2図の従来例と同一部分には同一図番を付
して説明を省略するが、この実施例では第2図お
入力容量補正用コンデンサC1を削除すると共に、
出力同調回路8内の同調用コンデンサC4に対し
て可変容量ダイオードD4と直流阻止コンデンサ
C7を図示の如く接続し、その両者の接続中点に
端子9に印加されるAGC制御電圧VGをトランジ
スタQで反転させ且つ電流制限抵抗R7を介して
印加するようにしたことを特徴としている。(F) Embodiment FIG. 1 shows an embodiment of the tuner of the present invention, and the same parts as the conventional example shown in FIG. In Figure 2, remove the input capacitance correction capacitor C1 and
Variable capacitance diode D4 and DC blocking capacitor for tuning capacitor C4 in output tuning circuit 8
C7 is connected as shown in the figure, and the AGC control voltage VG applied to the terminal 9 is inverted by a transistor Q and applied to the midpoint between the two connections through a current limiting resistor R7.
斯る実施例に於いて、弱電界受信時即ちAGC
制御電圧がVG=7Vの場合には、可変容量ダイオ
ードD4への印加電圧が中電界受信時よりも低く
なるから、その容量値が大きくなつてコンデンサ
C7,C4との合成容量値も大きくなる。従つて、
このときの出力同調回路8の同調周波数は第4図
に示す中電界受信状態での正規の状態から破線の
如く周波数の低い方向に若干ずれることになる。
これは出力同調回路8でのP/S比が小さくなる
ことを意味し、従つて、このときの入力同調回路
3の周波数特性(第3図a)に於けるP/S比の
増大分を相殺することになる。 In such an embodiment, when receiving a weak electric field, that is, AGC
When the control voltage is VG = 7V, the voltage applied to the variable capacitance diode D4 is lower than when receiving a medium electric field, so its capacitance value increases and the capacitor
The combined capacitance value with C7 and C4 also increases. Therefore,
At this time, the tuning frequency of the output tuning circuit 8 will deviate slightly from the normal state in the medium electric field reception state shown in FIG. 4 in the direction of lower frequencies as shown by the broken line.
This means that the P/S ratio in the output tuning circuit 8 becomes smaller, and therefore, the increase in the P/S ratio in the frequency characteristics (Fig. 3a) of the input tuning circuit 3 at this time is It will cancel out.
また、強電界受信状態即ちVG=0.5Vの場合に
は、可変容量ダイオードD4への印加電圧が大き
くなつて容量値が小さくなり、従つて、前述の合
成容量値も小さくなるので、このときの出力同調
回路8の同調周波数は第4図の実線の状態から一
点鎖線の如く周波数の高い方向に若干ずれP/S
比が大きくなる。従つて、この場合も前述と同様
にこのときの入力同調回路3の周波数特性(第3
図c)に於けるP/S比の減少分が相殺される。
それゆえ、出力同調回路8内のコンデンサC4,
C7、可変インダクタンスL及び可変容量ダイオ
ードD4を適切に選定することによつて、入力同
調回路3と出力同調回路8での各P/S比の変化
分が常に過不足なく相殺されるようにして、出力
端子9に導出するIF出力信号のP/S比を受信
電界強度に拘わらず常に所定の値に保持できるこ
とになる。 Furthermore, in the case of strong electric field reception, that is, VG = 0.5V, the voltage applied to the variable capacitance diode D4 increases and the capacitance value decreases, and therefore the above-mentioned combined capacitance value also decreases. The tuning frequency of the output tuning circuit 8 deviates slightly from the state shown by the solid line in Fig. 4 to the higher frequency direction as shown by the dashed line P/S.
The ratio becomes larger. Therefore, in this case as well, the frequency characteristics of the input tuning circuit 3 at this time (third
The decrease in the P/S ratio in Figure c) is offset.
Therefore, capacitor C4 in the output tuning circuit 8,
By appropriately selecting C7, the variable inductance L, and the variable capacitance diode D4, the changes in the P/S ratios in the input tuning circuit 3 and the output tuning circuit 8 can always be canceled out without excess or deficiency. , the P/S ratio of the IF output signal derived to the output terminal 9 can always be maintained at a predetermined value regardless of the received electric field strength.
(ト) 考案の効果
本考案の電子チユーナに依れば、AGC増幅回
路によるIF出力信号のP/S比変化を補正でき
るので、上記増幅回路に起因して弱電界受信時に
P/S比が増大することによつて生じるカラービ
ートや音声ビート等のビート妨害を防止できると
共に、強電界受信時にP/S比が小さくなること
によつて生じるバズの発生を阻止できる。また、
それによつて入力同調回路の可変範囲が何等変更
されることもない。(G) Effects of the invention According to the electronic tuner of the invention, it is possible to correct the P/S ratio change of the IF output signal due to the AGC amplifier circuit, so that the P/S ratio changes when receiving a weak electric field due to the above amplifier circuit. It is possible to prevent beat disturbances such as color beats and audio beats caused by the increase in electric field intensity, and it is also possible to prevent buzz caused by a decrease in the P/S ratio when receiving a strong electric field. Also,
This does not change the variable range of the input tuning circuit in any way.
第1図は本考案の電子チユーナの一実施例を示
す回路図、第2図は従来の電子チユーナを示す回
路図、第3図a,b,cは入力同調回路の周波数
特性を示す特性図、第4図は出力同調回路の周波
数特性を示す特性図である。
3:入力同調回路、4:AGC増幅回路、8:
出力同調回路、D4:可変容量ダイオード。
Fig. 1 is a circuit diagram showing an embodiment of the electronic tuner of the present invention, Fig. 2 is a circuit diagram showing a conventional electronic tuner, and Fig. 3 a, b, and c are characteristic diagrams showing the frequency characteristics of the input tuning circuit. , FIG. 4 is a characteristic diagram showing the frequency characteristics of the output tuning circuit. 3: Input tuning circuit, 4: AGC amplifier circuit, 8:
Output tuning circuit, D4: variable capacitance diode.
Claims (1)
トに印加され、AGC制御電圧(VG)が第2ゲー
トに印加されるデユアルゲートFET(T)を使用
したAGC増幅回路4と、 中間周波数信号に変換された前記AGC増幅回
路4からの信号を出力する出力同調回路8とを備
える電子チユーナに於いて、 前記AGC制御電圧(VG)の変化による前記デ
ユアルゲートFET(T)の入力容量(Co)の変化
により惹起される前記入力同調回路3の周波数特
性の変動を相殺する方向に、前記出力同調回路8
の周波数特性を変化させて、受信電界強度の変化
に起因するこの電子チユーナの映像キヤリア周波
数対音声キヤリア周波数の相対利得比の変動を小
さくするために、前記出力同調回路8の同調素子
として使用され、容量が前記AGC制御電圧
(VG)に応じて可変制御される可変容量素子
(D4)を、備えることを特徴とする電子チユー
ナ。[Claims for Utility Model Registration] 1. An input tuning circuit 3, and a dual gate FET (within which the received signal from the input tuning circuit 3 is applied to the first gate and the AGC control voltage (VG) is applied to the second gate). In an electronic tuner comprising an AGC amplification circuit 4 using the AGC amplifier circuit 4 using the AGC amplifier T) and an output tuning circuit 8 that outputs the signal from the AGC amplifier circuit 4 converted into an intermediate frequency signal, the AGC control voltage (VG) is The output tuning circuit 8 is arranged in a direction that cancels out fluctuations in the frequency characteristics of the input tuning circuit 3 caused by changes in the input capacitance (Co) of the dual gate FET (T).
is used as a tuning element of the output tuning circuit 8 in order to change the frequency characteristics of the electronic tuner and reduce fluctuations in the relative gain ratio of the video carrier frequency to the audio carrier frequency of this electronic tuner caused by changes in the received electric field strength. An electronic tuner comprising: a variable capacitance element (D 4 ) whose capacitance is variably controlled according to the AGC control voltage (VG).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2317085U JPH0349482Y2 (en) | 1985-02-20 | 1985-02-20 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2317085U JPH0349482Y2 (en) | 1985-02-20 | 1985-02-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61140645U JPS61140645U (en) | 1986-08-30 |
JPH0349482Y2 true JPH0349482Y2 (en) | 1991-10-22 |
Family
ID=30516162
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2317085U Expired JPH0349482Y2 (en) | 1985-02-20 | 1985-02-20 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0349482Y2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0783281B2 (en) * | 1989-07-15 | 1995-09-06 | 日本マランツ株式会社 | AGC circuit |
-
1985
- 1985-02-20 JP JP2317085U patent/JPH0349482Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS61140645U (en) | 1986-08-30 |
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