JPH0348519A - Power-on reset circuit - Google Patents

Abstract

PURPOSE:To output a reset signal until a power supply voltage reaches a voltage by which an arithmetic logic circuit stops its operation by providing a capacity between a comparator and a power source and controlling an output stage. CONSTITUTION:Two nodal points A, B of a voltage dividing circuit 10 become the same potential when a power supply voltage Vcc becomes a prescribed value, and from an output terminal 2 of a comparator 20 for comparing the potentials of the nodal points A, B, a reset signal is outputted. This power source Vcc and a gate of a P channel transistor(TR) Q6 of an output stage of the comparator 20 are connected by a capacity C, and connected to a gate of an N channel TR Q8 inserted through between its connecting point and the terminal 2. Accordingly, even when a voltage VDD drops to an operation unstable area of the comparator 20, the TR Q8 is turned on by a charge accumulated in the capacity C and the reset signal is latched, and until the power supply voltage becomes a value by which an arithmetic processing logic circuit cannot be operated, the reset signal is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power-on reset circuit configured with complementary MOS transistors.

[Conventional Technology] FIG. 2 is a circuit diagram showing a conventional power-on reset circuit.

A conventional power-on reset circuit includes a voltage dividing circuit 10 having two types of voltage dividing characteristics, and a comparator circuit 20 that compares two outputs of the voltage dividing circuit 10.

The voltage dividing circuit 10 includes a first voltage dividing circuit and a second voltage dividing circuit. The first voltage divider circuit is power supply 3 and ground 4
Resistor RIIR2 and diode D=-02 between
, D3 are connected in series, and the second voltage dividing circuit is constructed by connecting a resistor R3 and diodes D4, Dr5, and D6 in series between the power supply 3 and the ground 4. Then, the resistor R. of this first voltage dividing circuit. and resistance R2
A connection point A between the resistor R3 and the diode D4 of the second voltage dividing circuit is connected to the converter 20.

Comparator 20 is configured as follows.

That is, P channel transistor Q. , Q2's sources are connected to the power supply 3, and these two transistors Q=,
The gate of Q2 is a transistor Q. connected to the drain of This forms a current mirror circuit. The drain of the transistor Qs is connected to the drain of an N-channel transistor Q3, and the gate of the transistor Q3 is connected to the connection A of the voltage dividing circuit 10. Also, the drain of transistor Q2 has N
The drain of channel transistor Q4 is connected, and the gate of this transistor Q4 is connected to connection B of voltage dividing circuit 10. These transistors Q3 and Q
The sources of transistors 4 and 4 are connected to each other, and an N-channel transistor Q5 is inserted between this connection and ground 4. The gate of this transistor QI5 is connected to the bias terminal 1.

A connecting portion between transistors Q2 and Q4 is connected to the gate of a P-channel transistor Q8 in the output stage. The source of this transistor Q8 is connected to the power supply 3. Further, the drain of this transistor Q8 is connected to the drain of the N-channel transistor Q7, and is also connected to the output terminal 2. Transistor Q7 has its source connected to ground 4 and its gate connected to bias terminal 1.

In the power-on reset circuit configured as described above, when the voltage vDD of the power supply 3 changes, the potentials of the connection parts A and B of the voltage dividing circuit change at a predetermined rate of change. This rate of change is determined by the resistances R1, R2, R3 and the diode Di lD.
It is determined by 2s Da + D4t D5+D6. The potentials of the connections A and B match when the power supply voltage vDD reaches a specific voltage. In addition, the power supply voltage VDD
However, when the potentials of connections A and B are smaller than a certain matching voltage, the potential of connection A becomes higher than the potential of connection B, and the output terminal 2 of this power-on reset circuit becomes "0". level”.

[Problems to be Solved by the Invention] However, in the conventional power-on reset circuit described above, three transistors (QI, Q3, Q5 or Q21Q4, Q5) are connected in series between the power supply 3 and the ground 4.
Since the voltage vDD of power supply 3 is connected to this stage, the voltage vDD of power supply 3 is
If the voltage is lower than the sum of the threshold voltages of two transistors, the comparator 20 will not operate normally and the output of the power-on reset circuit will become unstable.

On the other hand, in a logic circuit connected to this power-on reset circuit, for example, an inverter is configured in two stages in series, including one P-channel transistor and one N-channel transistor.

The voltage at which the logic circuit in which two transistors are connected in series stops operating is lower by the threshold voltage of one transistor (approximately IV) than the comparator 20 of the power-on reset circuit. Therefore, when the voltage vDD of the power supply 3 decreases, even if the reset signal is output once, the converter 20 does not operate normally and the reset is canceled while the internal logic circuit is decreasing to a voltage that completely stops operating. Sometimes I put it away.

The present invention has been made in view of such problems, and includes:
Even if the power supply voltage is lower than the minimum operating power supply voltage of the comparator that constitutes the power-on reset circuit, the comparator will not operate until the power supply voltage reaches the power supply voltage at which the internal arithmetic logic circuits etc. connected to the power-on reset circuit completely stop operating. It is an object of the present invention to provide a power-on reset circuit that can fix the output of the circuit and hold a logic circuit or the like in a reset state.

[Means for Solving the Problems] The power-on reset circuit according to the present invention divides a power supply voltage and includes two voltage divider circuits having different voltage division characteristics whose voltage division ratios match when a specific power supply voltage is reached. a comparator that has an output stage configured by a P-channel transistor and an N-channel transistor and compares the voltages divided by the two voltage dividing circuits; and a converter connected between the gate of the P-channel transistor and a power supply. an N capacitor connected between the output of the comparator and ground and having its gate connected to the gate of the P-channel transistor.
A channel transistor.

[Operations] In the present invention, a capacitor is connected between the gate of the P-channel transistor in the output stage of the comparator and the power supply. Further, an N-channel transistor is interposed between the output terminal of the power-on reset circuit and ground, and the gate of this transistor is connected to the gate of the P-channel transistor. Therefore, the gates of the N-channel transistors are also connected to the negative electrode of the capacitor.

When the power supply voltage drops to a certain voltage, a reset signal is output to the output terminal of the power-on reset circuit.
At this time, charge is accumulated in the capacitor. If the power supply voltage drops further and comparator operation becomes unstable,
Since the N-channel transistor is held in the on state by the charge accumulated in this capacitor, the potential of the output terminal does not change and the reset signal can be maintained.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

The circuit of this embodiment differs from the conventional circuit in that a capacitor C and a transistor Q8 are newly provided.
The rest of the configuration is basically the same as that of the conventional power-on reset circuit, so the same components in FIG. 1 as in FIG. 2 are given the same reference numerals, and detailed explanation thereof will be omitted.

In this embodiment, a capacitor C is connected between the power supply 3 and the gate of the transistor Q8 in the output stage of the comparator 20. Further, an N-channel transistor Q8 is interposed between the output terminal 2 and the ground 4, and the gate of this transistor Q8 is connected to the connection between the capacitor C and the gate of the transistor Qe.

The power-on reset circuit of this embodiment has a power supply voltage vDD
When V is equal to or higher than the minimum operating voltage of the comparator 20, an "O level" is output to the output terminal 2 as the power supply voltage VDD decreases, similar to the conventional power-on reset circuit. At this time, charge is accumulated in the capacitor C. When the power supply voltage vDD becomes lower than the minimum operating voltage of the comparator 20, the operation of the comparator 20 becomes unstable.
Since charge is accumulated in the capacitor C connected between the transistor Q6 and the transistor Q6, the gate potential of the transistor Q6 is held at vDD. At this time, since the same signal is also input to the gate of N-channel transistor Q8, transistor Q8 is turned on. Therefore, the output terminal 2 maintains the "O level".

Note that the capacitance value of the capacitor C is preferably a value such that the load on the comparator 20 does not become too large, for example, 1 pF or less. In addition, since the N-channel transistor Q8 operates only near the threshold voltage of the P-channel transistor Q8, the on-resistance value is several tens of kilohms.
A transistor with a relatively weak driving force may be used.

[Effects of the Invention] As described above, according to the present invention, a capacitor is connected between the gate of the P-channel transistor in the output stage of the comparator and the power supply, and the connection point between the gate of the P-channel transistor and the capacitor is An N-channel transistor with its gate connected to The charge keeps the N-channel transistor on.

Therefore, reliable reset of the logic circuit can be guaranteed when the power supply voltage drops.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional power-on reset circuit.

Claims (1)

[Claims] (1) An output stage consisting of two voltage divider circuits that divide the power supply voltage and have different voltage division characteristics whose voltage division ratios match when a specific power supply voltage is reached, and a P-channel transistor and an N-channel transistor. a comparator for comparing the voltages divided by the two voltage dividing circuits; a capacitor connected between the gate of the P-channel transistor and the power supply; and a capacitor connected between the output of the comparator and ground. and an N-channel transistor whose gate is connected to the gate of the P-channel transistor.