JPH0346361A - Semiconductor device, semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce an undesired radiation, a mutual modulation and to enhance a conversion gain by providing a wiring layer grounded in an external circuit between a transistor which inputs a local oscillation output and a transistor which inputs a signal. CONSTITUTION:Emitters of a first transistor Tr1 and a second transistor Tr2 are connected in a differential type in package, a local oscillation output is input to either the first or second transistor, connectors are connected to the connecting parts of emitters, and a differential circuit element having a third transistor Tr3 which inputs a signal is provided. In this case, wiring layers 1042, 1043 grounded in an external circuit are provided between the transistor which inputs a signal and the transistor which inputs a signal. Thus, an output from a local oscillator can be raised to enhance a conversion gain.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to semiconductor devices and semiconductor integrated circuit devices, and is particularly applicable to ultra-small surface mounting of differential amplifier circuits, and to high-frequency signals. It is used in circuits suitable for processing.

(Prior Art) FIG. 18 shows a pattern layout of a conventional high frequency differential amplifier corresponding to the first invention. FIG. 19 shows an example of a circuit including its peripheral portion.

The above pattern and circuit are included in the first part inside the envelope (not shown).
Transistor (Tri) and second transistor (Tr2)
Each emitter of is connected in a differential manner.

That is, the local oscillation output is inputted to one of the above-mentioned transistors (Tri, Tr2), for example, the first transistor (Tr2) from the terminal 1001 which is a bonding pad, and the emitter 1111 of the local oscillation output is inputted to the second transistor (Tr2). The emitter 1121 and the collector 1133 of the third transistor (Tr3) are commonly connected by a wiring 1141. Further, the base 1122 of the second transistor is connected to the terminal 1002 of the peripheral circuit shown in FIG.
is grounded at high frequency by a capacitor.

A high frequency signal is applied to the base 1132 of the third transistor through the peripheral circuit, and the first transistor (Tr
The output from the local oscillator is applied to the base 1112 of I). Then, a signal having a frequency difference between the high frequency signal and the local oscillator is output from the collector 1123 of the second transistor. In addition, the collectors 1113 and 1123 of both the first and second transistors are connected to the power supply (Vcc) through resistors.
) and the emitter 11 of the third transistor
31 is a contact portion 1151 provided on the terminal 1005
Therefore, it is at a predetermined potential (usually grounded), which is the same potential as the silicon substrate 1100.

Next, a conventional example semiconductor device corresponding to the second invention will be explained with reference to FIGS. 20 to 24.

Ultra-small surface-mounted semiconductor devices (hereinafter referred to as semiconductor devices) are used, which are attached to wiring patterns provided on wiring boards to configure electronic circuits, along with circuit components such as resistors and capacitors. . An example of the internal structure of such a semiconductor device is shown in FIG. The semiconductor device shown in FIG. 20 has four leads 2112, 21 centered around a chip bed 2101 formed in a part of a metal lead frame.
22, 2132, and 2142 are provided facing each other and protruding from both sides, and each inner end is a connection area 2112a for a bonding wire, which will be described later.

2122a, 2132a, and 2142a, each of which corresponds to the electrode 2113.21 on the upper surface of the semiconductor chip 2103 mounted on the chip bed 2101.
23.2133°2143 and bonding wire 2 respectively
114.2124.2134°2144 to achieve electrical connection. Note that one of the connection areas 2112a is formed by extending one side of the chip bed 2101 along the long side of the resin sealing body. And the above leads 2112, 2122.2132.21
42 are the respective connection areas 2112a, 212
Inward from 2a, 2132a, 2142a is the chip bed 2101. The semiconductor chip 2103 and the bonding wires 2114, 2124, 2134, and 2144 are sealed in a resin sealing body 2105 as an example of an envelope. In addition, since the connection areas of the leads are located on the opposing inner sides, except for those formed by extending the central chip bed, the lead numbers in each drawing will be indicated by a and the explanation will be omitted. .

In the configuration of the semiconductor device described above, the lead width is 0.3 or more, and the chip bed 2101 is a square with a side of 0.811I11.

Lead parallel spacing and lead 2122.2] 32.21
42 and chip bed 2101 or resin sealing body 2105
The dimensions of the resin sealing body 2105 (envelope) are the short side length (A construction: Fig. 20).
is 1, 6 mm, and the long side length (B: Fig. 20) is 2.9 mm.
It has become.

Next, the semiconductor device shown in FIG. 21 is a 5-pin type semiconductor device that is configured to require more functions than the 4-pin type semiconductor device described above.

This structure has five leads 2212, 2222, 2232
．． Regarding 2242°2252, leads 2212 and 22
52. 2222 and 2232 are arranged facing each other at the long side ends of the resin sealing body 2205, and the leads 2242 and the chip bed 2201 are arranged facing each other between them. In this way, the dimensions of the resin sealing body 2205 are adjusted to the short side length (A2: 21st
Figure) is 1, 6nu++, long side length (B: Figure 21) is 2
．． It consists of 9 questions. Each of the above side lengths is equal to a 4-pin semiconductor device.

Furthermore, as multi-functions are required, semiconductor pellets with circuit functions consisting of transistors, diodes, resistors, etc. are equipped with six electrodes, as partially shown in Fig. 22, for example. , the lead leading to these needs to have 6 pins.

The above 6-pin semiconductor device was constructed as shown in FIG. 23(a). The feature of this structure is that the chip bed 2301 is arranged at the center, and the long side end of the sealing resin body 2305 has a board 236.
2 and 2352.2322 and 2332 are placed opposite each other,
Leads 2312 and 2342 are arranged facing each other between them. The lead 2312 is connected to the center chip bed 2301.
is formed by extending to the long side of the resin sealing body, and the lead 23
It protrudes from the resin sealing body through twelve connection areas 2312a.

In addition, 2303 in the figure is a semiconductor chip, 2313.2
323°2333, 2343.2353.2363 are all semiconductor chip electrodes, 2314.2324.2
334.2344.2354.2364 is a bonding wire. In this way, the dimensions of the resin sealing body 2305 are determined such that the short side length (A, Fig. 23 (a)) is 1.9 mm, and the long side length (B: Fig. 23 (a)) is 2.9 mm. It is composed of The short side length (A1) is about 0.3 mm larger than that of the 4-pin and 5-pin cases. The details of this dimension are shown in Figure 26 (
Shown in b).

Next, another configuration example of a 6-pin semiconductor device is shown in FIG.
). The feature of this structure is that the chip bed 2401 is arranged at the center, and the leads 2412 extending from it are
The structure is similar to that illustrated in the pin semiconductor device (FIG. 21). That is, the connection area 241 of the lead 2412
2a is formed by extending one side of the chip bed 2401 along the long side of the resin sealing body. Even if you do this,
This is because the leads 2422 and 2452 need to be placed directly opposite the chip bed 2401.

Contains these leads 2412.2422.2432.2
442° 2452, 2462, and connection area 2412a
, 2422a, 2432a.

The arrangement of 2442a, 2452a, and 2462a is
When installed as shown in FIG. 4(a), the resin sealing body 2405 has a short side length (A4) of 2.2 mm and a long side length (B) of 2.2 mm.
It will be 9H. Therefore, the short side length of this structure is approximately 0.6 mm larger than that of the conventional 4-pin and 5-pin cases.

Details of this dimension are shown in FIG. 24(b).

In addition, 2403 in FIG. 24(a) is a semiconductor chip, 2413, 2423.2433.2443.2453
．． 2463 is an electrode formed on the semiconductor chip 2403, 2414.2424°2434, 2444.245
4.2464 is a bonding wire that makes an electrical connection between the electrode and the connection area of the lead.

An example of a conventional circuit device corresponding to the third invention will be explained with reference to FIG. 25 and FIG. 27.

In the dual gate metal oxide semiconductor field effect transistor (hereinafter abbreviated as dual gate MOS FET) shown in the top view in FIG. 25, the pin terminal 3301 is the first gate, the pin terminal 3302 is the second gate, The pin terminal 3303 is the drain, the pin terminal 330
4 leads out each electrode of the source. This moss F
For example, ET is used in a mixing circuit section of a superheterodyne receiver as shown in FIG. 26. That is, in the circuit shown in FIG. 26, a local oscillation signal applied from a terminal 3311 is passed through a coupling capacitor 3321, and the second pin terminal 3302 is biased to an appropriate voltage.
injected from. In addition, the high frequency signal applied from the terminal 3312 passes through a coupling capacitor 3324, and is preliminarily connected to a resistor 3324.
322 and a resistor 3323 to an appropriate voltage and is injected from the first pin terminal 3301. Third
The pin terminal 3303 has a terminal 3313 connected to it.
From there, an intermediate frequency signal generated from the local oscillation signal and the high frequency signal is extracted and injected into the next stage circuit (not shown).

Further, the fourth pin terminal 3304 serves as a ground terminal for alternating current. The first pin terminal 3301 that inputs the high frequency signal and the second pin terminal 3302 that inputs the local oscillation signal are adjacent to each other, and the dimensions of the semiconductor device itself are small, for example, 2.9 mm x 1.5 mm. The distance between the pin terminals is also very narrow at 1.9 mm.

FIG. 27 shows an equivalent circuit of the dual gate MOS FET shown in FIGS. 25 and 26.

A conventional differential amplifier circuit of a semiconductor device corresponding to the fourth invention will be explained.

The differential amplifier circuit shown in Figure 28 is used for high frequency mixers, etc., but in order to improve high frequency performance,
Since integration is difficult, conventional devices have been constructed by combining discrete elements. For example, bipolar transistors with a transition frequency fy of about 2 GHz are often used in VHF band tuners of television receivers, and bipolar transistors with a transition frequency fy of about 4 GHz are often used in UHF tuners.

On the other hand, as TVs, VTRs, and other devices become more sophisticated and more compact, tuners are also required to be more efficient and more compact. things are needed.

No. 28 regarding the conventional example of the integrated circuit device according to the fifth invention
This will be explained with reference to FIGS. 31 to 31.

A circuit as shown in FIG. 29 is frequently used in general electric circuits. - As an example, there is a circuit as shown in FIG.
) and the signal fL (260 MHz) from the local oscillator to extract an output signal (60 MHz). In the above circuit, the following points are important.

(1) Since it is undesirable for fs and fl to have mutual interference, the respective input terminals Bl, B3. In the case of FIG. 30, the base terminal B1 of the first transistor (Tri) and the base terminal B3 of the third transistor (Tr3) need to be placed as far apart as possible.

(2) Mutual interference between input and output is undesirable, so in the case of input and output terminals, the base terminal and collector terminal of each transistor should be placed as far apart as possible.

(3) Currently, electronic devices are trending toward miniaturization, so
Even when a circuit as shown in FIG. 9 is sealed in one package, the size of the package needs to be extremely small.

An example of an integrated circuit device in which the circuit shown in FIG. 29 is sealed in one package is shown in FIG. 31. In the integrated circuit device shown in the figure, two circuits shown in FIG. 29 are formed in one package. Third
In the circuit shown in Figure 1, for example, fS is input to the terminal 5111, fl is input to the terminal 5112, and the output is input to the terminal 5111.
If it is taken out from No. 13, the above-mentioned conditions (1)<2) are satisfied, and good characteristics can be obtained. Also, as you can see from the same figure, there are no intersecting parts of the wiring,
Therefore, the manufacturing process is also relatively easy. Furthermore, since two circuits shown in FIG. 29 are formed, the pin arrangement is also reasonable.

(Problem to be Solved by the Invention) In the conventional pattern layout shown in FIG. 18, which corresponds to the first invention, the first
Wiring 1 leading to the base 1112 of the transistor (Tri)
142 and a wiring 1143 from the terminal 1003 of the bonding pad to which a high-frequency signal is applied to the base 1132 of the third transistor (Tr3). The wiring 1144 leading to the base 1122 of the transistor (Tr2) occupies only a part of the silicon substrate;
Transistor (Tri) and third transistor (Tr3)
The high frequency separation between the two is incomplete. For this reason, it has been difficult to suppress unnecessary radiation and intermodulation caused by the output of the local oscillator entering the high frequency signal line. In addition, due to the above problem, it is not possible to increase the output of the local oscillator, so there is a serious problem that the conversion gain becomes low. In addition to reducing unwanted radiation and intermodulation,
The purpose is to increase conversion gain.

According to the structure of the semiconductor device shown in the prior art corresponding to the second invention, especially the structure and arrangement of the leads for leading out the electrodes, an example of 6 pins for multifunctionalization is 4 pins.
~5 pins and the size of the envelope (resin sealing body) are larger. Due to this.

When mounting or assembling many semiconductor devices on one wiring board, it is necessary to use different carriers, holders, etc., which reduces the efficiency of the assembly process, complicates the disposal system of the assembly equipment, and increases the size. Additionally, there were other problems, such as the amount of effort required for maintenance.

The present invention has been made in view of the problems in the conventional semiconductor devices mentioned above.
The purpose is to provide an improved structure of a semiconductor device.

The semiconductor device shown in the conventional technique corresponding to the third invention has the following problems.

(1) Since there are multiple input signals, leakage and interference of individual signals is possible. This effect is particularly noticeable in semiconductor devices that use small envelopes with small pin-terminal intervals.

(2) In semiconductor devices used in mixed circuits, the local oscillation signal has a high level and may leak to the outside as unwanted radiation.Furthermore, the local oscillation signal may suppress the intermediate frequency signal at the output terminal. be. Possible problems include:

In the circuit configured with discrete elements in the conventional technology corresponding to the fourth invention, the occupied area is large;
This was a limiting factor in the miniaturization of equipment. In addition, in the case of a discrete configuration, the wiring between elements cannot be made smaller than a certain level, resulting in problems such as the locally oscillated high frequency to the mixer leaking to the antenna and being radiated to the outside, causing interference to other equipment. was.

The conventional technology corresponding to the fifth invention does not sufficiently achieve the recent trend of packaging integrated circuit devices on circuit boards at high density in order to downsize electronic devices. That is, the integrated circuit device shown in FIG. 31 is advantageous when two circuits shown in FIG. 29 are used in close proximity in an electric circuit, but only one circuit is used as shown in FIG. 30. If the two circuits are used separately or if the two circuits are used separately, there will be disadvantages in terms of mounting area or wiring. Therefore, an integrated circuit device in which one circuit shown in FIG. 29 is sealed is also required. If such an integrated circuit device is considered as an extension of the conventional technology shown in Fig. 31, it will be as shown in Figs. 32 and 33, but when used in the electric circuit shown in Fig. 30, the following will occur. There are problems such as.

First, in the case of the integrated circuit device shown in FIG.
If fs is input to 12, fl terminal is input to the fourth terminal 5214, and output is taken out from the fifth terminal 5215, items (1) and (2) described in the prior art section are satisfied, but only one side of the package Since four leads (5211 to 5214) are formed on one side and two leads (5215, 5216) are formed on the other side, the package becomes quite large.

Next, in the case of the integrated circuit device shown in FIG. 33, three leads are attached to opposite sides of the package, and the package can be made considerably smaller.

However, i'1. f3 respectively to the first terminals 5311.
When the signals are input to the second terminal 5312, since the respective leads are adjacent to each other, mutual interference between the respective signals becomes a problem. Also, fL and fs are the fourth terminal 5314 and the second terminal 5
312 (not shown), the input terminal (fourth terminal 5314) and the output terminal (fifth terminal 531)
5) are placed adjacent to each other, there are problems such as mutual interference between input and output.

The present invention has been made to solve the above-mentioned problems in the conventional technology, and is aimed at miniaturizing semiconductor devices.

The purpose is to improve high frequency electrical characteristics.

[Structure of the invention]

(Means for Solving the Problems) A semiconductor integrated circuit device according to a first invention has emitters of a first transistor and a second transistor connected in a differential manner in an envelope, and one of the transistors A semiconductor integrated circuit device is provided with a differential circuit element including a third transistor to which a local oscillation output is input, a collector is connected to the connection portion of each of the emitters, and a signal is input. A wiring layer grounded in an external circuit is provided between the transistor to which the signal is input and the transistor to which the signal is input.

A semiconductor device according to a second aspect of the invention includes a chip bed on which a semiconductor chip is attached, a plurality of pairs of leads protruding from both sides of an envelope around the chip bed, and electrodes on the top surface of the semiconductor chip. It is provided with electrical connection means, and some of the leads are formed extending from a part of the periphery of the chip bed, and the means for connecting with the electrode is formed by connecting leads from a different part of the periphery of the chip bed. It is characterized by comprising connection areas extending in different directions.

A semiconductor device according to a third aspect of the present invention is a semiconductor device including a differential amplifier circuit in an envelope and a signal input terminal and a signal output terminal on opposite sides of the envelope. It is characterized in that it consists of a plurality of signal input terminals and is provided with a shield terminal between these signal input terminals to prevent mutual interference between input signals.

A semiconductor device according to a fourth aspect of the present invention includes first to third elements formed adjacent to each other on a semiconductor substrate, first electrodes of the first element and second element, and first electrodes of the first element and the second element, and the third element. a metal layer electrically connecting the third electrode of the element;
a first terminal connected to a second electrode of the element and formed in the shape of a metal pad for external connection; and a first terminal disposed adjacent to the first terminal and connected to a second electrode of the second element. a second terminal for external connection; a third terminal for external connection arranged next to the second terminal and connected to the second electrode of the third element; and a third terminal arranged next to the third terminal. a fourth terminal for external connection connected to the first electrode of the third element;
a fifth terminal for external connection arranged adjacent to the fourth terminal and connected to the third electrode of the second element; and a fifth terminal arranged between the fifth terminal and the first terminal of the first element The device includes a chip having a sixth terminal for external connection connected to the third electrode of the device.

A semiconductor integrated circuit device according to a fifth aspect of the present invention includes first to third elements formed adjacent to each other on a semiconductor substrate, first electrodes of the first element and second element, and a first electrode of the first element and the second element. a metal layer that electrically connects the third electrode of the third element; a first terminal that is connected to the second electrode of the first element and is formed in the shape of a metal pad for external connection; a second terminal for external connection arranged next to the first terminal and connected to the second electrode of the second element; and a second terminal arranged next to the second terminal and connected to the second electrode of the third element. a third terminal for external connection connected, a fourth terminal for external connection arranged adjacent to the third terminal and connected to the first electrode of the third element, and adjacent to the fourth terminal The third element of the second element is arranged in
a fifth terminal for external connection connected to the electrode of the fifth terminal;
and a sixth terminal for external connection disposed between the first terminal and connected to the third electrode of the first element; A conductive layer connecting the second electrode to the second terminal is formed on a portion of the diffusion region constituting the third electrode of the third element via an electrically pure edge layer. It is something to do.

(Function) In the first aspect of the invention, a wiring layer grounded by an external circuit is passed between the high frequency signal line and the local oscillation line, thereby preventing mutual modulation of both signals and undesired interference with the high frequency signal line. Radiation is reduced. This makes it possible to increase the output from the local oscillator and increase the conversion gain.

The semiconductor device according to the second invention described below has an envelope (4
i1 fat sealing body) can be formed to have the same size as that of 4 to 5 pins. This eliminates the need to use different carriers, holders, etc. in equipment for mounting and assembling semiconductor devices on substrates, thereby improving the efficiency of the assembly process and simplifying the active system of the assembly equipment.

Further, in the semiconductor device according to the third aspect of the invention, mutual interference between the two input terminals is reduced by providing a terminal grounded at high frequency via a capacitor between the two input terminals. Further, the input terminal and the output terminal are arranged on opposite sides of the envelope to isolate the input circuit and the output circuit, thereby suppressing mutual interference.

The fourth invention is a bipolar transistor or a MOS F transistor.
By monolithically forming a circuit combining three ETs on a semiconductor substrate and optimizing the arrangement of the electrodes, it is possible to improve the packaging density and achieve a super-heavy design (-1, 5n+iX3.On+m), it is possible to provide a high-performance differential amplification type mixer element.

In a fifth invention, when a high frequency differential amplifier circuit is mounted in one package, the pin terminals protruding from opposite sides of the package are arranged such that fs is input to the third terminal and fl is input to the first terminal. , the output (fi) is arranged so as to be output from the fourth terminal protruding from the opposite side of one side on which the first to third terminals are arranged, thereby reducing fs, fl and mutual interference between input and output, and reducing high frequency An electrical circuit with excellent characteristics can be formed.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

An example of a circuit constituting a semiconductor device according to the first invention and its pattern layout is shown in FIGS. 1 and 2. This semiconductor device has three npn type transistors, a first
or third transistor (Tri, Tr2, Tr3
), the emitter 1 of the first transistor (Tri)
011 and the emitter 10 of the second transistor (Tr2)
21 and the collector 103 of the third transistor (Tr3)
3 is connected to the arrangement %1041, the collector 1013 of the first transistor (Tri) is connected to the sixth bonding pad terminal 1006, and the collector 1023 of the second transistor (Tr2) is connected to the fourth bonding pad terminal 1006. It is connected to the pad terminal 1004 and to the power supply (Vcc) from the peripheral circuitry through a resistor. The base 1012 of the first transistor (Tri) is connected to the first bonding pad terminal 1001 by a wiring 1042,
Local oscillator output from outside is injected and also.

The base 1032 of the third transistor (Tr3) is connected to the third bonding pad terminal 100 by a wiring 1043.
3, and a high frequency signal from the outside is injected.

The base 1022 of the second transistor (Tr2) is connected to the collector 103 of the third transistor by a wiring 1044.
The upper part of the 3rd part overlaps with this, and the 3rd part
and the first transistors (Tr3, Tri), and is connected to a second bonding pad terminal 1002, which is grounded at high frequency by an external circuit.

The emitter 1031 of the third transistor (Tr3) is connected to the fifth bonding pad terminal 1005, and a contact hole 1051 provided in the fifth bonding pad terminal 1005 connects the silicon substrate 1t.
It is connected to the same potential as oo, and is set to ground potential by an external circuit.

Note that in this invention, the first to third transistors are MOS (M
etal Oxide Sen+1 conductor
) It goes without saying that even FETs (field effect transistors) are suitable.

Next, a semiconductor device according to an embodiment of the second invention will be described with reference to FIGS. 2(a) and 2(b). In FIG. 2(a), which shows a cross-sectional view of the structure of the semiconductor device, the semiconductor pellet 2003 has internal transistors, diodes, resistors, etc., which are the same as those described in the conventional example. electrode 2013.2023.2
033.2043.2053.2063 placement only lead 2012.2022.2032.2042.2052
．． 2062 and its inner end connection area 2012a,
2022a, 2032a.

They are provided corresponding to the arrangement of 2042a, 2052a, and 2062a. Further, the electrodes on the main surface of the semiconductor pellet are connected to bonding wires 2014.2024.2034.204 in the connection area of each corresponding lead.
4. They are connected at 2054° and 2064° to establish electrical connection.

Here, the lead 2012 extends from one side of the chip bed 2001 (lower side in the figure), and the adjacent lead 2022
, 2062 and protrudes from the resin sealing body 2005 of the envelope. Also, unlike other leads whose inner ends are used as connection areas for bonding wires for connecting electrodes, this lead 2012 has a connection area 2012a.
is the lead 2012 in the chip bed 2001
(vertical side in Fig. 2(a))
The leads extend in a direction different from the direction in which the leads protrude.

This connection area 2012a has the same width and length as the other lead connection areas 2022a and 2032a.

It may be approximately equivalent to 2042a, 2052a, 2062'a. Further, although the figure shows two connection areas extending in opposite directions from the chip bed 1, one of the connection areas that is advantageous for wire bonding may be used, or even one connection area may be used.

Although the semiconductor device configured as described above has 6 pins, the dimensions of the resin sealing body 5 of the envelope are as shown in FIG. 2(b). Figure 2 (a)) is 1,
At 6 mm, the short side length A1 and the long side length B were the same as those of conventional 4-pin and 5-pin pins.

FIG. 3 shows a top view of a semiconductor device using an FET according to an embodiment of the third invention, and FIG. Shown in Figure 4.

In FIGS. 3 and 4, the pin terminal 3301 is
Gate and pin terminals 3302 each lead out the second gate, and are arranged on one side of the envelope with the pin terminal 3301, and between these two pins, a capacitor 3011 is connected and a pin terminal is connected to the AC ground. 3001 is arranged. In addition, a pin terminal 330 leading out the drain electrode
3 and the pin terminal 3304 from which the source electrode is derived are connected to the pin terminals 3302, 3001. Pin terminals 3303, 3304, and 3002 are arranged on a side opposite to one side of the envelope on which pin terminals 3303, 3301, and 3301 are provided, facing the pin terminal group, respectively. This pin terminal 3002 is a pin terminal for deriving an intermediate frequency signal generated from a local oscillation signal and a high frequency signal, and is connected to a terminal 3314 via a coupling capacitor 3012 to be connected to the next stage circuit (not shown). . Note that the terminal 3313 is a power source (Vcc). The terminals arranged in this manner achieve isolation between the input terminals and between the input and output terminals.

Note that the structure of the chip of the semiconductor device in this invention is as follows:
As shown in Figure 5, three transistors (Tri, T
Even if differential amplification is performed using
As shown in Figure 6, three field effect transistors (FE
It is also possible to apply differential amplification using T-1-FET-2, FET-3).

In addition, in the internal arrangement shown by the broken line in FIG.
3 indicates a semiconductor chip, and 3004 indicates a chip bed on which the semiconductor chip 3003 is attached.

An embodiment of the fourth invention will be described below with reference to FIGS. 7 to 11.

FIG. 8 shows the arrangement of the bonding pads according to the first embodiment of the present invention, which corresponds to the circuit example shown in FIG. 7, and FIG. 9 shows the pattern of the surface metal layer. In the figure, the first transistor (Tr
i) The second transistor (Tr2) and the third transistor (Tr3) can be constructed using a known bipolar integrated circuit manufacturing process, with a fine pattern, low capacitance structure, and shallow junction formation suitable for high frequencies. etc., realizing a high f7, but since it is not directly related to the essence of the present invention, a detailed explanation will be omitted. The essence of the present invention lies in the layout of the device, particularly the arrangement of electrodes and bonding pads for external connections.

In the semiconductor substrate 4000 shown in FIG. 9, 4001 is a first transistor (Tri) region, 4002 is a second transistor (Tr2) region, 4003 is a third transistor (Tr3) region, and 4003 is a third transistor (Tr3) region.
The base of i) is led out by a metal wiring layer and connected to the bonding pad around the main surface of the semiconductor substrate 4000 as shown in FIG. 8, and local oscillation high frequency (fL) is injected from the peripheral circuit (not shown). be done. In addition, a second bonding pad B2 adjacent to the old bonding pad
The base of the transistor (Tr2) is connected, and a high frequency signal (fs) is injected from a peripheral circuit (not shown).

Furthermore, the third transistor (Tr3) is connected to the bonding pad B3 adjacent to the bonding pad B2.
The base of the bonding pad B1.
Along with B2, it is arranged along one side of the main surface of the semiconductor substrate. Next, the emitter of a third transistor (Tr3) is connected to a bonding pad E3 disposed along the side adjacent to the negative side of the semiconductor substrate, which serves as a power ground for the peripheral circuit. Further, bonding pads C2 and C1 are arranged along the side adjacent to the adjacent side, and the collector of a second transistor (Tr2) is led out and connected to the bonding pad C2 to output (fi) to the peripheral circuit. The first transistor (
The collector of Tri) is lead-out connected and grounded in the peripheral circuit.

In FIG. 1O, each of the first to third transistors (Trl"Tr3) in the first embodiment is replaced with a MOS FET (MO
5TI, MOSi2, MOSi3) is shown. By changing the names of the electrodes such as emitter to source (S), base to gate (G), and collector to drain (D), they can be formed in the same manner as in the previous embodiment.

An embodiment of the fifth invention will be described below with reference to FIGS. 11 and 12.

As shown in FIG. 11, the chip has a first element (Tr), a second element (Tr2), and a third element (Tr3) formed adjacent to each other on a semiconductor substrate. The emitter electrodes of the first element (Tri) and the second element (Tr2) are connected to each other, and the third element (T
The collector electrode of r3) is connected with a metal layer 5010. Next, a first terminal 5001 connected to the base electrode of the first element (Tri) and formed in a metal pad shape for external connection, and a first terminal 5001 arranged next to the first terminal 5001 and connected to the second element A second terminal 5002 for external connection connected to the base electrode of (Tr2), and the second terminal 5002
A third terminal 5003 for external connection is arranged next to and connected to the base electrode of the third element (Tr3);
a fourth terminal 5004 for external connection connected to the emitter electrode of the second element (Tr2), and a fifth terminal 5004 for external connection arranged adjacent to the fourth terminal 5004 and connected to the collector electrode of the second element (Tr2). a terminal 5005 and the fifth terminal 500
5 and the first terminal 5001.
6th for external connection connected to the collector electrode of Tri)
In particular, a conductive M5012 connecting the base electrode of the second element (Tr2) to the second terminal 5002 is connected to the third terminal 5006 as shown in FIG.
Diffusion region 5 forming the collector electrode of the element (Tr3)
043 with an electrical insulating layer 5050 interposed therebetween.

Hereinafter, in the case of using an NPN bipolar transistor, a method for manufacturing the main parts will be explained with reference to FIG. 14.

After forming n++ buried layers 5021 and 5041 on the upper surface of a lightly doped P-type silicon substrate 5040, a p-type epitaxial layer 5020 is formed. Next, the n-type impurity is selectively diffused to form the n-type collector region 5022.5032.504.
2.

Also n++ collector area 5023.5033.5043
form. Next, base regions 5024, 5034, and 5044 are formed by selectively diffusing n-type impurities, and polycrystalline silicon layers 5025a and 5025a containing n-type impurities are respectively formed in base regions 5024, 5034, and 5044.
5035a.

5045a (5035a is not shown in FIG. 12) is selectively diffused to form an n+ type upper emitter region 5025.
5035.5045 (5035 is not shown in FIG. 12). Next, a glabella insulating film 5050 is formed, and as shown in FIG. Contact holes 5025a, 5024a, 50 for exposing parts
22a, 5035a, 5034a.

5032a, 5045a, 5044a, 5042
After forming the wiring electrode 5011.50 with a conductive material
12.5013.5014.5015°5016 are provided, and each of the terminals 5001.5002.5003°50
04, 5005, and 5006 to achieve electrode derivation, and a chip of a semiconductor integrated circuit device is formed.

Next, details of the manufacturing method will be explained with reference to FIG. 12.

First, a semiconductor substrate 5040 containing about 8 x 10110l4' of boron is prepared. The semiconductor substrate 504
N+ type buried layer 5021.5031.5 selectively containing antimony of the order of 5 x 10"c++-" on the top surface of the
041 (5031 is not shown in FIG. 12), an epitaxial layer 5020 containing about 2×101101 s' of boron is grown. next,
Accelerating voltage 70 KeV, dose amount 3.0 x 1012 cm-
3, and acceleration voltage 40KaV, dose amount 2×10”C
After implanting phosphorus by m-3 ion implantation, 1150
℃ for about 12 hours in a N2 atmosphere to form n-type collector regions 5022, 5032, 5042 (5032 is not shown in FIG. 12) and n+-type collector regions 5.
023° 5033 and 5043 (5033 is not shown in FIG. 12) are formed, respectively. Next, an oxide film of about 10
Formed around 00A.

Accelerating voltage 40KeV, dose amount 3. OX 10”am-
After boron ion implantation in step 2, step 11 was performed in a nitrogen atmosphere.
The base region 5024 is annealed at 00°C for about 50 minutes.
．． 5034° 5044 (5034 is not shown in FIG. 12).

Next, emitter regions 5025, 5035, 5045 are formed by a polysilicon layer doped with arsenic.

In FIGS. 13 and 14, the n+ type collector region 5
This polycrystalline silicon layer is also present on a portion of 023, 5033, and 5043, and this is to reduce the contact resistance with the conductive member. Next, the film is deposited to a thickness of 8,000 wafers by CVI (chemical vapor deposition) or the like, and then annealed at 1,100° C. for an appropriate time in a nitrogen atmosphere to control the direct current amplification factor hFE.

Next, a contact hole is provided in each region to lead out the region of each element in the wiring layer, and the wiring electrode layer 5010°501
1, 5012.5013.5014.5015.501
6 is made of aluminum, and each terminal 50 is connected by these.
01.5002゜5003, 5004.5005.50
Connect to 06.

In the embodiment, each of the first to third elements is a bipolar transistor, but the emitter, base, and collector electrodes can also be used in the case of a MOS (metal oxide semiconductor device), FET (field effect transistor), etc. Needless to say, it can be applied as source, gate, and drain electrodes. Furthermore, it can also be applied to cases where a resistive element or a capacitive element is included.

[Effects of the Invention] According to the first invention, intermodulation of two signals and undesired radiation to the high frequency signal line are reduced by passing a wiring layer grounded by an external circuit between the high frequency signal line and the local oscillation line. can do. This has the significant advantage of increasing the output from the local oscillator and increasing the conversion gain.

According to the second aspect of the invention, it is possible to meet the demand for increasing the number of bins accompanying the multifunctionalization of semiconductor devices without increasing the size. Therefore, it has a remarkable effect on miniaturizing electronic circuits.

In addition, since it can be formed into an envelope of the same size as a conventional semiconductor device, placement on a wiring board can be accomplished using the same jig used for transporting and assembling other semiconductor devices. The configuration is simplified, and its design and maintenance are also facilitated.

Furthermore, since the input and output sides of the semiconductor device can be separated by a connection area extending from the chip bed, interference and oscillation between the two can be prevented, improving the electrical performance of the semiconductor device and circuit. There are significant advantages such as improved performance and ease of design.

According to the third invention, it is possible to suppress mutual interference between input signals and input/output signals of a semiconductor device, and it is possible to easily design an isolation method for input signals and input/output signals of the example superheterodyne method. In the semiconductor device according to the fourth invention, the chip size can be reduced to about 0.6 mm square, and as shown in FIG.
By mounting and bonding to a frame as shown in Figure 16, the size of the molded body can be reduced to approximately 1.5 m.
It can be enclosed in an ultra-small surface-mounted envelope measuring 3 m x 3 m.
compared to a discrete configuration.

At least three times higher density packaging is possible. Next, we will discuss the advantages of using the elements of this semiconductor device in actual applications. FIG. 30 shows an example of a circuit in which the integrated device of the present invention is applied to a television tuner. A high frequency signal of frequency fs is input to the base of the third transistor (Tr3). A locally oscillated high frequency wave having a frequency fl is input to the base of the first transistor (Tri). The emitter of the third transistor (Tr3) is connected to the power supply ground, and the collector of the first transistor (Tri) and the base of the second transistor (Tr2) are grounded at high frequency.

The first transistor (Tri), the second transistor (
Tr2) and the third transistor (Tr3), a resistor for applying an optimum DC bias, a capacitor, an inductance, etc. for controlling high frequency signal are added as appropriate, but detailed explanation is not related to the essence of the present invention. Since there is none, I will omit it. f from the collector of the second transistor (Tr2)
The difference and sum frequencies of l and fs are output, and the necessary intermediate frequency fi component is extracted. In this case f of fl
It is necessary to minimize the wraparound to the S side and the wraparound of fi to the fS side.

In the present invention, a ground terminal bonding pad (B2) is output between the bonding pad (B3) where f3 is inserted and the bonding pad (B1) where fl is inserted, and the bonding pad (B3) and fi are output. Ponding pad (
A grounding pad (C3) as a ground terminal is inserted between C2), and all signals are grounded and shielded in the middle. Furthermore, the frame during assembly has a similar shielding structure, and the placement of the chip's bonding pads can be easily matched to this frame, making it possible to have an optimal assembly structure.

The first transistor (Tri), the second transistor (
The effect is the same when both Tr2) and the third transistor (Tr3) are configured with MOS FETs, but
Since the input-output characteristics of the MOS FET are close to ideal square-law characteristics, it is possible to obtain characteristics with lower distortion.

In addition, the third transistor is a MOS FET (MO5T3
), when the first transistor (Tr l ) and the second transistor (Tr2) are configured with bipolar transistors, the low distortion of MOSFET and the high gm characteristic of bipolar transistor are utilized at the same time, resulting in a mixer with higher performance. realizable.

As described above, by using the integrated element of the semiconductor device according to the present invention, it is possible to have a packaging density more than three times that of conventional circuits, and it is also possible to reduce the interference radio waves caused by unnecessary radiation. This greatly contributes to the miniaturization and higher performance of equipment such as televisions and videos.

The present invention is not limited to mixer circuits, but can be used as a general differential amplifier, and can be applied to oscillators and many other applications.

The semiconductor integrated circuit device according to the fifth invention has the following effects.

First, when the circuit shown in Fig. 14 is mounted in one package, the lead arrangement as shown in Fig. 15 becomes possible.
In the applied circuit example shown in FIG. 16, fS is the third terminal,
By inputting fl from the first terminal and taking the output from the fourth terminal, it is possible to reduce mutual interference between fs and fl and between input and output, and it is possible to form an electrical circuit with good high frequency characteristics. .

Second, there is no need for complex processes such as multilayer wiring, and there is no need to run long wiring lines, so the chip size can be reduced. For example, if a circuit is configured with three bipolar transistors as shown in Figure 13, the chip size can be 0.54m+oXO, 54+mm, and it can be mounted on a lead frame as shown in Figure 17. If an integrated circuit device is formed, the envelope 5060
It is possible to set the size to approximately 2.9 mm x 1.6 mm. This is the same size as a conventional ultra-small surface mount device and is suitable for high-density surface mounting.

In the above explanation, we explained the case of an integrated circuit device formed only with bipolar transistors, but MOSFE
It may be configured with a T, or it may be applicable even if a resistive element and a capacitive element are included.

[Brief explanation of drawings]

1(a) and 1(b) relate to an embodiment according to the first invention, FIG. 1(a) is a configuration circuit diagram of a semiconductor device of the first invention, and FIG. FIGS. 2(a) and 2(b) are a diagram showing a pattern layout of a), and FIGS. b) is a top view showing the main part of FIG. 2(a), FIGS. 3 to 6 relate to the embodiment according to the third invention, FIG. The figure is a circuit diagram in which the FET of FIG. 3 is used, FIGS. 5 and 6 are diagrams showing the structure of a chip of a semiconductor device, and FIG.
The figure shows the configuration circuit diagram of the semiconductor device of the first embodiment, FIG. 8 shows the arrangement of the bonding pads, FIG. 9 shows a top view showing the pattern of the surface metal layer, and FIG. 10 shows the semiconductor device of the second embodiment. The configuration circuit diagrams, FIGS. 11 and 12, relate to an embodiment according to the fifth invention, FIG. 11 is a top view showing a pattern of a surface metal layer of a semiconductor integrated circuit device, and FIG. 12 is a top view showing a pattern of a surface metal layer of a semiconductor integrated circuit device. Cross-sectional view for explaining the manufacturing method, 13th
The figure is a top view for explaining the correlation between the structure and effects of the embodiment of the fourth invention, and FIGS. 14 to 17 are diagrams for explaining the correlation between the structure and effects of the fifth invention. , Fig. 14 is a circuit diagram, Fig. 15 is a top view showing lead arrangement, Fig. 16 is a top view showing the lead arrangement.
The figure is an applied circuit diagram, Figure 17 is a top view of the envelope, Figures 18 to 33 are diagrams for explaining conventional examples, and Figure 18 is a diagram for explaining the conventional example.
22 and 22 relate to a conventional example of the first invention, and FIG. 18 is a top view showing a pattern layout of a high frequency differential amplifier;
Figure 19 is a circuit diagram including peripheral parts, Figures 20 to 2
FIG. 4 relates to the conventional example of the second invention, and FIG.
1 is a top view showing the structure of the semiconductor device, FIG. 22 is a circuit diagram, FIG. 23(a) is a top view showing the configuration, and FIG. 23(b) is a top view showing the structure of the semiconductor device.
) is a top view showing the main parts, FIG. 24(a) is a top view showing the configuration, FIG. 24(b) is a top view showing the main parts, and FIGS. 25 to 27 are conventional views of the third invention. Regarding examples, Fig. 25 is a top view of the dual gate MOS FIET, Fig. 26 is a peripheral circuit diagram, Fig. 27 is a circuit diagram, and Figs. 28 to 33 are
The figures relate to the conventional example of the fifth invention, and are shown in figures 28 to 30.
Each figure is a circuit diagram, and each of FIGS. 31 to 33 is a diagram showing the internal structure of the envelope. Tri, Tr2. Tr3: first to third transistors. MO5TI, MO3T2. MO5T3...first to third moss FIET. fl...Local oscillation output, fs...High frequency signal, fi
...output signal.

Claims (5)

[Claims] (1) The emitters or sources of the first transistor and the second transistor are connected in a differential manner within the envelope, and the local oscillation output is input to one of these transistors, and the connection portion of each emitter is In a semiconductor integrated circuit device equipped with a differential circuit element including a third transistor to which a collector or drain is connected to and to which a signal is input, there is a gap between the transistor to which the local excavation output is input and the transistor to which the signal is input. 1. A semiconductor integrated circuit device comprising a wiring layer which is grounded in an external circuit. (2) A chip bed with a semiconductor chip attached thereto, a plurality of pairs of leads protruding from both sides of the envelope around the chip bed, and means for electrically connecting these leads to electrodes on the top surface of the semiconductor chip. Some of the leads are formed to extend from a part of the periphery of the chip bed, and the means for connecting to the electrodes are formed to extend from a different part of the periphery of the chip bed in a direction different from that of the leads. What is claimed is: 1. A semiconductor device comprising: a connection area having a connection area; (3) In a semiconductor device that includes a differential amplifier circuit inside an envelope and has a signal input terminal and a signal output terminal on opposite sides of the envelope, there is a plurality of signal input terminals, and these A semiconductor device comprising a shield terminal between signal input terminals for preventing mutual interference between input signals. (4) first to third elements formed adjacent to each other on a semiconductor substrate; first electrodes of the first element and second element; and third electrode of the third element; a first terminal connected to the second electrode of the first element and formed in the shape of a metal pad for external connection; a second terminal for external connection connected to the second electrode of the second element; and a second terminal for external connection arranged adjacent to the second terminal and connected to the second electrode of the third element. a fourth terminal for external connection arranged next to the third terminal and connected to the first electrode of the third element; and a fourth terminal arranged next to the fourth terminal and connected to the first electrode of the third element; a fifth terminal for external connection connected to the third electrode of the first element; and a fifth terminal for external connection arranged between the fifth terminal and the first terminal and connected to the third electrode of the first element. A semiconductor device including a chip having six terminals. (5) first to third elements formed adjacent to each other on a semiconductor substrate; first electrodes of the first element and second element; and third electrode of the third element; a first terminal connected to the second electrode of the first element and formed in the shape of a metal pad for external connection; a second terminal for external connection connected to the second electrode of the second element; and a second terminal for external connection arranged adjacent to the second terminal and connected to the second electrode of the third element. a fourth terminal for external connection arranged next to the third terminal and connected to the first electrode of the third element; and a fourth terminal arranged next to the fourth terminal and connected to the first electrode of the third element; a fifth terminal for external connection connected to the third electrode of the first element; and a fifth terminal for external connection arranged between the fifth terminal and the first terminal and connected to the third electrode of the first element. 6 terminals, and the conductive layer connecting the second electrode of the second element to the second terminal constitutes the third electrode of the third element. A semiconductor integrated circuit device, characterized in that it is formed on a part of the region with an electrically insulating layer interposed therebetween.