JPH0345550B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and particularly to a dynamic memory structure suitable for increasing capacity.

Dynamic memory, which consists of a single capacitor and a single transistor, has fewer components.
Because the number of wires is small, it is especially used as a method for large-capacity semiconductor memory. However, in the conventional configuration, as shown in FIG. 1, a capacitor 1 and a transistor 2 are arranged in a plane on the surface of a substrate 3. The charge accumulated in the capacitor is
Since it is distributed to the stray capacitance of the bit line during reading, a somewhat large capacitance is required to detect it as a signal. In addition, a somewhat large capacitance is required to prevent malfunctions due to unexpected charge generation due to α rays, etc., and a capacitor of about 60 fF is usually used in a 256K-bit memory.
Typically, this capacitor consists of a switch transistor followed by a MOS inversion layer or diffusion layer, and occupies an area of about 60 μm ² . Therefore, in such a planar configuration, it is difficult to reduce the size of the unit cell, which has been an obstacle to increasing the capacity of the memory.

The purpose of the present invention is to provide a structure for a device that overcomes the limitations of dynamic memory and can increase the capacity. Another object of the present invention is to provide a memory cell structure.

The features of the device in the present invention are vertical FET,
In other words, a transistor in which the direction of the controlled current is perpendicular to the substrate is used for switching, the control electrode for switching is narrowed, and a capacitor for charge storage is placed at one end of the semiconductor constituting the transistor, and a capacitor for writing/reading is placed at the other end. It has a structure in which two signal lines are connected. A further feature of this structure is that it is composed of crossing points of bit lines and word lines for memory access.

The present invention will be explained below using examples.

FIG. 2 is a sectional view showing an embodiment of the present invention. The semiconductor substrate 21 is p-type Si, and the memory cell is formed at the intersection of a bit line conductor 23 running parallel to the plane of the paper and a word line conductor 24 running perpendicular to the plane of the paper. The word line conductor 24 has an opening at the intersection with the bit line, and a columnar semiconductor 25 passes through this opening. This semiconductor rod 25 is, for example, p-type with a resistance of 0.1 to 10 Ω·cm, and both ends (top and bottom) are n-type regions 26 and 27 with low resistivity, one end of which is connected to a bit line, and the other end is connected to a capacitor. Each is connected by a resistive contact to the semiconductor 28 to be formed. The length of the p-type region of the semiconductor rod 25 is approximately equal to the thickness of the word line conductor 24;
Further, the p-type region is connected to the word line 24 and the thin insulating film 29.
The outer periphery of the p-type region constitutes an insulated gate field effect transistor forming a channel. The semiconductor 28 forming the capacitor has an n-type resistivity, and is connected to the substrate 21 and the thin insulating film 2.
2, and the capacitance between it and the substrate is used to store memory charge.

Memory operation is based on conventional MOS dynamics
Similar to RAM, driving the word line opens and closes the FET formed on the side wall of the semiconductor body, electrically connecting/disconnecting the bit line and the capacitor.

The embodiment shown in FIG. 2 is manufactured by the steps shown in FIG. First, a flat p-type (100) of around 1Ω・cm
A silicon substrate is used as the starting material. After lightly oxidizing the surface, boron for a channel stopper is introduced into the entire surface by ion implantation, and a layer 301 with a slightly lower resistivity is provided on the surface. Next, the portion where the capacitor is to be formed is steeply etched using a known silicon dry etch to form a recess 302. Next, after once removing the oxide film, it is thinly re-oxidized to form a dielectric insulating film 303 for a capacitor, producing the shape shown in FIG. 3A.

Next, as shown in Figure 3 B, a known CVD is applied to the entire surface.
A polycrystalline Si layer 311 doped with n-type impurities at a high concentration is formed by a method. In this state, the surface is melted and recrystallized by a known beam annealing method. At this time, if one side of the depression 302 is about 4 μm or less, the known graphoepitaxial phenomenon occurs.
According to the shape of the depression, a single crystal with a preferred orientation of <100> is grown perpendicular to the main surface. More preferably, prior to forming the polycrystalline Si layer, an opening is formed in the main surface at a location other than the depression 302 to expose the underlying Si, and then the polycrystalline Si layer is formed.

After the beam annealing, the surface is approximately flattened, and more preferably, the thickness is flattened using a known bias sputtering method or the like. Next, as shown in FIG. 3C, a p-type layer 321 of 0.1 Ω·cm is epitaxially grown on this layer, and an n ⁺ layer 322 is formed by introducing n-type impurities into the entire surface by ion implantation and diffusion. Form.

Next, as shown in FIG. 3D, the upper part of the capacitor area is covered with photoresist 331, and the upper Si layer is
The trench is dug down to the insulating film 332 formed on the substrate. The dry etch selectivity ratio between Si and SiO ₂ is approximately 50:
1, this end point detection is easy.

Next, as shown in FIG. 3E, SiO ₂ films 341 and 342 are deposited by plasma CVD or sputtering while leaving the resist 331. Its deposited thickness is the n ⁺ region 34 forming the capacitor
3 and p region 34 formed by epitaxial growth.
4 so that the top surface of the membrane coincides with the boundary with 4.

Next, the resist 331 is removed, and at the same time the deposited SiO ₂ film 342 on it is also removed. In this state, a thermal oxide film 351 of 500 Å or less is formed, and at the same time the deposited SiO ₂ film is sintered and integrated with the insulating film formed on the substrate to obtain the structure shown in FIG. 3F.

Next, Al is deposited on the entire surface, and its thickness is made to be the same as or slightly thicker than the p-type epitaxial layer 361. Furthermore, the Al deposited layer is patterned to form word lines 363 as shown in FIG. A portion 364 of the Al deposited film remains on the memory cell in a separated state.

Next, an insulating film 3 for separating word lines and bit lines.
71 is deposited, and the protrusion at the top of the memory cell is preferentially removed by sputtering using a well-known leveling sputtering method to expose the n ⁺ diffusion layer 372 at the top of the memory cell, and Al is deposited on the entire surface to form the bit line 373. form,
The structure shown in FIG. 3C is obtained. This figure has the same structure as shown in FIG.

FIG. 4 is a schematic plan view of four memory cells, and the cell of the present invention has bit wiring B1, B2, etc.
They are formed in the respective crossing regions with the word wirings W1, W2, etc., and the minimum processing area in this case is the interval between the semiconductor rod penetrating portion 41, the capacitor region 42 of the cell, and the capacitor region 43 of the adjacent cell.
However, since the channel part of the FET and the capacitor have a three-dimensional structure, for example, even if the minimum processing line width is 1.2 μm, a FET with a channel width of 4 μm can be obtained, and the channel width and length, which are the performance index of the FET, can be obtained. The ratio is improved by 2 to 3 times. Furthermore, there is no particular limit in the depth direction when forming a capacitor, but if it is formed in a cubic shape, per unit area of approximately 13 μm ² ,
A capacitor area of 29 μm ² is obtained. If an even larger capacitor area is required, the surface area can be expanded by forming the capacitor deeper or by adding an uneven shape. Capacity can be obtained.

In the above-mentioned embodiment, the switching transistor used was an insulated gate field effect transistor in which the outer peripheral side wall of the semiconductor rod was used as a channel, but in FIG.
It may be used as an electrostatic induction transistor of a type in which the conductivity of the semiconductor rod is controlled by electrostatic induction depending on the word line potential. Furthermore, as shown in FIG. 5, the memory cell of the present invention can also be constructed using a Schottky gate type FET in which the word line 51 and the semiconductor body main portion 52 are in direct contact.

As described above, the memory cell according to the present invention occupies a small area and can be formed at the intersection of word wiring and bit wiring for accessing the memory. As explained in the embodiment, according to the present invention, the area required to configure the equivalent of 1 megabit is 14 ^mm2 , and this is an improvement over the switching transistor used in the conventional 256K bit dynamic memory. This value is based on achieving the same capacitance using a transistor with mutual conglucance.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional structural diagram of a MOS dynamic memory having a conventional structure, FIGS. 2 and 5 are cross-sectional diagrams of a memory showing an embodiment of the present invention, and FIG. 4 is a plan view showing the structure of the present invention. The figure is a process diagram showing an example of the method for manufacturing the memory of the present invention. 21...Substrate, 23...Bit line conductor, 24...
...Word line conductor, 25...Semiconductor rod, 22,2
9...Insulating film.

Claims (1)

[Claims] 1. At least a memory cell consisting of a capacitor for storing information and a field effect transistor for driving the capacitor, and bit lines and word lines that intersect with each other for accessing the memory. In the semiconductor memory device, the field effect transistor is disposed within a region defined by the line width of the bit line and the word line in a region where the bit line and the word line intersect when the semiconductor memory device is viewed from vertically above. a source region, a channel region, and a drain region;
A semiconductor memory device characterized in that a connection portion between the bit line and the field effect transistor and a connection portion between the electrode of the capacitor and the field effect transistor are provided. 2. Claim 1, wherein the capacitance formation region substantially overlaps with the region defined by the line width of the bit line and word line in the region where the bit line and word line intersect. semiconductor storage device. 3. The capacitor includes an insulating film formed on the surface of a groove formed in a semiconductor substrate having a first conductivity type and a low resistance semiconductor formed on the insulating film,
The field effect transistor includes a first semiconductor region formed in the upper part of the trench, and a low-temperature semiconductor region having a second conductivity type opposite to the first conductivity type formed in contact with the upper and lower sides of the first semiconductor region, respectively. Claim 1 or 2, characterized by comprising second and third semiconductor regions of the resistor, and a word line formed on the side surface of the first semiconductor region with an insulating layer interposed therebetween. The semiconductor storage device described in .