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JPH0342688Y2 - - Google Patents

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Publication number
JPH0342688Y2
JPH0342688Y2 JP1982013002U JP1300282U JPH0342688Y2 JP H0342688 Y2 JPH0342688 Y2 JP H0342688Y2 JP 1982013002 U JP1982013002 U JP 1982013002U JP 1300282 U JP1300282 U JP 1300282U JP H0342688 Y2 JPH0342688 Y2 JP H0342688Y2
Authority
JP
Japan
Prior art keywords
fet
electrode
gate electrode
gate
spiral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1982013002U
Other languages
Japanese (ja)
Other versions
JPS58116244U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1300282U priority Critical patent/JPS58116244U/en
Publication of JPS58116244U publication Critical patent/JPS58116244U/en
Application granted granted Critical
Publication of JPH0342688Y2 publication Critical patent/JPH0342688Y2/ja
Granted legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【考案の詳細な説明】 本考案は、電界効果型トランジスタ(以下
FETと称する)に係り、特にアナログ回路の集
積化に好適なFETの構造に関するものである。
[Detailed explanation of the invention] This invention is a field-effect transistor (hereinafter referred to as
The present invention relates to a FET structure suitable for integrating analog circuits.

従来、FETの高性能化、つまり、高利得化及
び、低雑音化、高速化は、主としてゲート電極長
さの短縮による、チャンネル長の短縮により、或
いは、ゲート電極の幅の拡大によるチャンネル幅
の拡大により、実現されて来た。チャンネル幅の
拡大によりFETの利得を高め、雑音を低減する
ことが可能となるが、チャンネル幅の拡大は同時
に、FETのゲートに平行な方向の寸法の拡大を
ともなう。このため、高利得、低雑音のFETを
作るためには、ゲートと平行な方向に長いFET
を、作る必要が生じる。しかし、このように、長
いFETは、集積回路内にFETを取り入れる場合、
回路内各素子を集積回路中に配置する場合、配置
の自由度を減少させる結果を引き起こす、集積回
路全体の寸法の増大を引き起こす、等の不都合を
生じる。以上の様な不都合を避けるために、「ア
イ.ビー.エム.ジヤーナル.リサーチ.デベロ
ツプメント(IBM Journal Research
Development)」(1970年3月)・P.125に示すよ
うに、ゲート電極を円環状に配置し、FETを有
効に使用できる形にする方法も考案されている
が、この方法では、電極取り出し部の自由度が少
なく、又素子平面の利用効率が高いとは言えな
い。
Conventionally, improvements in FET performance, that is, higher gain, lower noise, and higher speed, have been achieved mainly by shortening the gate electrode length, channel length, or increasing the channel width by increasing the width of the gate electrode. This has been achieved through expansion. Increasing the channel width makes it possible to increase the gain of the FET and reduce noise, but at the same time, increasing the channel width also increases the dimension of the FET in the direction parallel to the gate. Therefore, in order to create a FET with high gain and low noise, a long FET in the direction parallel to the gate is required.
It becomes necessary to make . However, when incorporating a FET into an integrated circuit, a long FET like this
When each element in a circuit is arranged in an integrated circuit, disadvantages arise, such as a reduction in the degree of freedom of arrangement and an increase in the overall dimensions of the integrated circuit. In order to avoid the above-mentioned inconveniences, the IBM Journal Research Development (IBM Journal Research Development)
As shown in "Development" (March 1970), p. 125, a method has been devised in which the gate electrode is arranged in an annular shape so that the FET can be used effectively. The degree of freedom of the parts is small, and the utilization efficiency of the device plane cannot be said to be high.

本考案の目的は、上記諸欠点を解決し、FET
の実寸法を一方向に長い形態から、二方向に同程
度に広がる形態とし、FETを使い易い形態にす
るにある。
The purpose of this invention is to solve the above-mentioned drawbacks and to
The actual size of the FET is changed from a long one in one direction to one that spreads to the same extent in two directions, making it easier to use the FET.

本考案はFETのゲート電極の幅を出来るだけ
大きくし、しかもFETの形態を正方形に近づけ
るために、FET全体をゲート電極、ソース電極、
ドレイン電極が存在する平面上で、渦巻状に形成
する方法を取る。FETを渦巻状に形成すること
により、本考案においては半導体表面の全面を
FETとして利用出来る。さらに、渦巻状に形成
したために、FETのとなりにFETが存在する形
となる。つまり、渦巻を一周したFETが、元の
FETととなり合せとなつて存在する。このため、
このとなり合せとなつた同一のFETの間に、も
う一つのゲートを入れることが出来る。この新し
いゲートの挿入により、従来の電極配置に比べ同
一の面積でFETのゲート幅を、実効的に2倍と
することができる。
In this invention, in order to make the width of the gate electrode of the FET as large as possible and to make the shape of the FET close to a square, the entire FET is connected to the gate electrode, source electrode,
A method is adopted in which the electrode is formed in a spiral shape on the plane where the drain electrode exists. By forming the FET in a spiral shape, in this invention the entire semiconductor surface can be covered.
Can be used as a FET. Furthermore, since it is formed in a spiral shape, an FET exists next to an FET. In other words, the FET that has gone around the spiral is
It exists alongside the FET. For this reason,
Another gate can be inserted between these adjacent identical FETs. By inserting this new gate, the FET gate width can be effectively doubled with the same area compared to the conventional electrode arrangement.

このような本考案の具体的な実施例を第1図で
説明する。横型FETに対してならば常に適用で
きるが、例として、GaAsシヨツトキバリア型
FETについて説明する。
A concrete embodiment of the present invention will be described with reference to FIG. It can always be applied to horizontal FETs, but as an example, G as shot barrier type
Explain FET.

まず半絶縁性GaAs基板上に、エピタキシヤル
成長法、あるいは、イオン打込法等により、N型
GaAs半導体を形成する。次に第1図中2で示す
ソース電極部、4で示すドレイン電極部6で示す
ソース電極パツド部、及び、8で示すドレイン電
極パツド部にさらにN型不純物を、拡散法あるい
は、イオン打込法等により分布させる。これは、
電極金属とのオーミツク性接合を形成するためで
ある。次に、第1図中2で示すソース電極部、4
で示すドレイン電極部、6で示すソース電極パツ
ド部、及び8で示すドレイン電極パツド部、つま
り上記方法でN型不純物を二重に導入した部分
に、金属を蒸着し電極とする。次に1で示すゲー
ト電極部A、3で示すゲート電極部B、5及び7
で示すゲート電極パツド部にN型半導体層とシヨ
ツトキバリアを形成するような金属を蒸着する。
1で示すゲート電極部A及び3で示すゲート電極
部Bは、渦巻状FETの最も内側で図のように接
続され、この部分も、2で示すソース電極と4で
示すドレイン電極にはさまれ、FETとして動作
する。このようなFETは、各パツド部を除く全
ての部分がFETとして動作する。更に、渦巻の
一周ちがいの部分もFETとして動作し、ソース
電極部及びドレイン電極部の長さが一般的な
FETと同じであつたとしても、その2倍の長さ
を持つFETとして動作する。
First, N-type is grown on a semi-insulating GaAs substrate by epitaxial growth or ion implantation.
Forms a GaAs semiconductor. Next, N-type impurities are further added to the source electrode portion shown by 2 in FIG. distribution according to the law, etc. this is,
This is to form an ohmic contact with the electrode metal. Next, the source electrode section indicated by 2 in FIG.
Metal is deposited on the drain electrode portion shown by , the source electrode pad portion 6, and the drain electrode pad portion 8, that is, the portion into which N-type impurities are doubly introduced by the above method, to form electrodes. Next, gate electrode part A indicated by 1, gate electrode part B indicated by 3, 5 and 7
A metal that forms an N-type semiconductor layer and a shot barrier is deposited on the gate electrode pad portion shown by .
The gate electrode part A indicated by 1 and the gate electrode part B indicated by 3 are connected at the innermost part of the spiral FET as shown in the figure, and this part is also sandwiched between the source electrode indicated by 2 and the drain electrode indicated by 4. , operates as a FET. In such a FET, all parts except each pad part operate as an FET. In addition, the parts of the spiral that are located at different circumferences also operate as FETs, and the lengths of the source and drain electrodes are longer than normal.
Even if it is the same as a FET, it operates as a FET with twice the length.

上記のような構成により、本考案における
FETは、従来に比べ実効的に2倍長いゲーム幅
を持ちながら、占有面積は増大せず、その形態
は、正方形に近くなる。このためFETとして使
い易い形態となり、又FET製造の場合にも長い
ゲート幅を持つFETが、細長いチツプとならず
に作成出来るために、歩留向上やチツプスクライ
ブ後の取扱いが容易になる等利点が多い。又この
ようなFETを集積回路中で使用する場合、FET
が細長い形状とならないため、配線が容易であ
る。他の素子と同様の形状であるため集積回路内
でのFETの配置が他の素子と同じように出来る
等、集積回路内の素子の配置について自由度が増
大する。
With the above configuration, in this invention,
Although the FET has an effective game width twice as long as the conventional one, the area it occupies does not increase, and its shape is closer to a square. This makes it easy to use as a FET, and in the case of FET manufacturing, FETs with long gate widths can be manufactured without creating elongated chips, which has advantages such as improved yield and easier handling after chip scribing. There are many. Also, when using such a FET in an integrated circuit, the FET
Since it does not have an elongated shape, wiring is easy. Since the FET has the same shape as other elements, the degree of freedom in arranging elements within the integrated circuit increases, such as allowing the FET to be placed in the same way as other elements.

第1図では、正方形の場合を示したが、FET
の形状は、渦巻状であれば、円形であつても良い
し、又任意の多角形とすることも可能である。
Figure 1 shows the square case, but the FET
The shape may be circular as long as it is spiral, or it may be any polygon.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案になる実施例を示し、FETを、
そのFETが形成されているチツプの平面に垂直
な方向から見た電極部分を示している。 1……ゲート電極部A、2……ソース電極部、
3……ゲート電極部B、4……ドレイン電極部5
……ゲート電極部Aパツド、6……ソース電極部
パツド、7……ゲート電極部Bパツド、8……ド
レイン電極パツド。
Figure 1 shows an embodiment of the present invention, in which the FET is
It shows the electrode part viewed from a direction perpendicular to the plane of the chip where the FET is formed. 1... Gate electrode part A, 2... Source electrode part,
3... Gate electrode part B, 4... Drain electrode part 5
...Gate electrode part A pad, 6... Source electrode part pad, 7... Gate electrode part B pad, 8... Drain electrode pad.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ソース電極とドレイン電極を、共に並列に渦巻
状に配置し、前記両電極間に生ずるすべての間隙
にゲート電極を設けるとともに、前記各電極に対
する接続パツドを、前記渦巻の最外周における前
記各電極の端部において形成した電界効果型トラ
ンジスタ。
A source electrode and a drain electrode are arranged in parallel in a spiral shape, a gate electrode is provided in every gap between the two electrodes, and a connection pad for each electrode is connected to each electrode at the outermost periphery of the spiral. Field effect transistor formed at the end.
JP1300282U 1982-02-03 1982-02-03 field effect transistor Granted JPS58116244U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1300282U JPS58116244U (en) 1982-02-03 1982-02-03 field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1300282U JPS58116244U (en) 1982-02-03 1982-02-03 field effect transistor

Publications (2)

Publication Number Publication Date
JPS58116244U JPS58116244U (en) 1983-08-08
JPH0342688Y2 true JPH0342688Y2 (en) 1991-09-06

Family

ID=30025538

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1300282U Granted JPS58116244U (en) 1982-02-03 1982-02-03 field effect transistor

Country Status (1)

Country Link
JP (1) JPS58116244U (en)

Also Published As

Publication number Publication date
JPS58116244U (en) 1983-08-08

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