[go: up one dir, main page]

JPH0342510B2 - - Google Patents

Info

Publication number
JPH0342510B2
JPH0342510B2 JP14103183A JP14103183A JPH0342510B2 JP H0342510 B2 JPH0342510 B2 JP H0342510B2 JP 14103183 A JP14103183 A JP 14103183A JP 14103183 A JP14103183 A JP 14103183A JP H0342510 B2 JPH0342510 B2 JP H0342510B2
Authority
JP
Japan
Prior art keywords
cooling structure
fluid
semiconductor device
substrate
partition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14103183A
Other languages
Japanese (ja)
Other versions
JPS6032348A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14103183A priority Critical patent/JPS6032348A/en
Publication of JPS6032348A publication Critical patent/JPS6032348A/en
Publication of JPH0342510B2 publication Critical patent/JPH0342510B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、冷却構造を備えた半導体装置に係
り、特に超大形コンピユータ等に高密度に実装さ
れる大規模集積回路チツプ等から発生する熱を除
去するのに好適の冷却構造を備えた半導体装置に
関するものである。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device equipped with a cooling structure, and in particular to a semiconductor device equipped with a cooling structure. The present invention relates to a semiconductor device equipped with a cooling structure suitable for removal.

〔発明の背景〕[Background of the invention]

従来の半導体素子あるいは集積回路チツプを備
えた半導体装置の冷却構造の各例を、各図を参照
して説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of conventional cooling structures for semiconductor devices including semiconductor elements or integrated circuit chips will be described with reference to the drawings.

第1図は、従来例の冷却構造を備えた半導体装
置の断面図、第2図、第3図は、いずれも他の従
来例の冷却構造を備えた半導体装置の断面図で、
第1図と同一符号のものは同等部分を示してい
る。
FIG. 1 is a cross-sectional view of a semiconductor device equipped with a conventional cooling structure, and FIGS. 2 and 3 are cross-sectional views of semiconductor devices equipped with other conventional cooling structures.
Components with the same reference numerals as in FIG. 1 indicate equivalent parts.

第1図において、多層配線された基板1の上に
多数の大規模集積回路(以下LSIという)チツプ
2がフエースダン接合によつて実装されている。
多数のLSIチツプ2を覆うようにハウジング3A
が基板1に装着されている。各LSIチツプ2の裏
面に接触するようハウジング3A面に多数の可撓
性の袋4が取付けられ、袋4の内には、流動性に
富み高熱伝導性の液体5が封入されている。袋4
はハウジング3Aを基板1に装着する際、各LSI
チツプ2に、ある圧力をもつて密着するように押
し付けられる。LSIチツプ2は、基板1と半田ボ
ール7とでフエースダン接合され、基板1の裏面
のピン8と電気的に接続されている。半田ボール
7は非常に小さいため、LSIチツプ2の発熱は、
半田ボール7を通して基板にほとんど伝えること
ができない。したがつて大部分の熱はLSIチツプ
2の裏面から高熱伝導性の液体5が封入された袋
4を経て、ハウジング3Aに伝えられ、ハウジン
グ3Aに設けられた冷却水流路9を流れる冷却水
により除去される。
In FIG. 1, a large number of large-scale integrated circuit (hereinafter referred to as LSI) chips 2 are mounted on a substrate 1 having multilayer wiring by face-to-face bonding.
Housing 3A covers a large number of LSI chips 2.
is attached to the board 1. A large number of flexible bags 4 are attached to the surface of the housing 3A so as to be in contact with the back surface of each LSI chip 2, and a highly fluid and highly thermally conductive liquid 5 is sealed inside the bags 4. bag 4
When installing housing 3A on board 1, each LSI
It is pressed tightly against the chip 2 with a certain pressure. The LSI chip 2 is face-down bonded to the substrate 1 and solder balls 7, and is electrically connected to pins 8 on the back surface of the substrate 1. Since the solder ball 7 is very small, the heat generated by the LSI chip 2 is
Almost no signal can be transmitted to the board through the solder balls 7. Therefore, most of the heat is transferred from the back side of the LSI chip 2 to the housing 3A via the bag 4 filled with a highly thermally conductive liquid 5, and is transferred to the housing 3A by the cooling water flowing through the cooling water channel 9 provided in the housing 3A. removed.

基板1は、多層配線構造のため一般に変形しや
すく製造的に反りが発生する。また、半田ボール
7による接合方法は一度にLSIチツプ2の多数の
電気配線を行う特徴があり、各LSIチツプ2の実
装高さをそろえることが困難である。したがつ
て、ハウジング3AとLSIチツプ2との熱的結合
を図る可撓性の熱伝導経路が必要となる。この
点、第1図の冷却構造は袋4内に封入された高熱
伝導性液体5が非圧縮性流体であるため、袋4は
非常に可撓性に富んだ材料で形成されなければな
らない。しかも、封止液体5に対し耐蝕性があ
り、熱伝導率ができるだけ大きな、耐熱性に富ん
だ膜でなければならず、袋材料の選定が非常に難
かしい。また、第1図の袋構造では、LSIチツプ
2の変形量が大きくなると、袋4内の液体5の内
圧力が大きくなる。そのため、LSIチツプ2に加
わる荷重も大きくなるので、形状寸法が非常に小
さい半田ボールは塑性変形する。このような状態
で、LSIチツプ2に長期間、通電、停止のサイク
ルを続ければ、クリープ現象により半田ボール7
は破断してしまい、電気接続が断線する。一方、
袋4の薄膜にも大きな張力が加わり、膜の寿命を
低下させる。
Since the substrate 1 has a multilayer wiring structure, it is generally easily deformed and warped during manufacturing. Furthermore, the bonding method using the solder balls 7 is characterized in that a large number of electrical wirings of the LSI chips 2 are connected at the same time, and it is difficult to make the mounting heights of each LSI chip 2 the same. Therefore, a flexible heat conduction path for thermally coupling the housing 3A and the LSI chip 2 is required. In this regard, in the cooling structure shown in FIG. 1, since the highly thermally conductive liquid 5 sealed in the bag 4 is an incompressible fluid, the bag 4 must be made of a highly flexible material. In addition, the membrane must be highly heat resistant, having corrosion resistance against the sealing liquid 5, and having as high a thermal conductivity as possible, making selection of the bag material extremely difficult. Furthermore, in the bag structure shown in FIG. 1, as the amount of deformation of the LSI chip 2 increases, the internal pressure of the liquid 5 in the bag 4 increases. Therefore, the load applied to the LSI chip 2 also increases, and the solder balls, which have very small dimensions, are plastically deformed. If the cycle of energizing and stopping the LSI chip 2 continues for a long time under this condition, the solder ball 7 will be damaged due to the creep phenomenon.
will break, breaking the electrical connection. on the other hand,
A large tension is also applied to the thin film of the bag 4, reducing the life of the film.

そこで上記の欠点を改善するため、第2図の冷
却構造が提案されている。
In order to improve the above-mentioned drawbacks, the cooling structure shown in FIG. 2 has been proposed.

第2図の冷却構造は、第1図と同様に基板1上
に半田ボール7によつてフエースダン接合された
LSIチツプ2と基板1の上面から全体に薄膜10
がコーテイングされ、コーテイング薄膜10の上
のハウジング3B内面間の空間領域11に、流動
性に富み高熱伝導率の液体12を充填されたもの
である。LSIチツプ2の発熱は上部の液体12か
らハウジング3Bを経て、ハウジング3B内に設
けられた冷却水流路9を流れる冷却水により排除
される。
The cooling structure shown in FIG. 2 is connected face-down to the substrate 1 by solder balls 7 in the same way as in FIG. 1.
Thin film 10 is applied to the entire top surface of LSI chip 2 and substrate 1.
is coated, and a space region 11 between the inner surface of the housing 3B above the coating thin film 10 is filled with a fluid 12 having high fluidity and high thermal conductivity. The heat generated by the LSI chip 2 is removed by the cooling water flowing from the upper liquid 12 through the housing 3B and through the cooling water passage 9 provided in the housing 3B.

しかし、このような第2図の冷却構造では新た
な問題が生じる。基板1上に多数実装されたLSI
チツプのうち1部分のチツプが不良になつた場
合、不良チツプの交換が要求される。マルチ・チ
ツプ・モジユールは1チツプ・モジユールに比べ
高価であるため、モジユール全体を廃棄すること
はできない。しかし、LSIチツプ背面に薄膜が施
されているので、薄膜の補修が非常に困難であ
る。たとえ一部分補修が行われても、薄膜10は
継ぎ目が生じる。また、薄膜全体を剥離させれ
ば、良品のチツプの半田ボールに影響を及ぼし、
モジユールの信頼性を低下させる。
However, a new problem arises in the cooling structure shown in FIG. 2. Many LSIs mounted on board 1
If one of the chips becomes defective, replacement of the defective chip is required. Since multi-chip modules are more expensive than single-chip modules, the entire module cannot be disposed of. However, since a thin film is applied to the back of the LSI chip, it is extremely difficult to repair the thin film. Even if a partial repair is performed, the membrane 10 will have seams. Also, if the entire thin film is peeled off, it will affect the solder balls on good chips.
Decreases module reliability.

そこで、更に上記の欠点を解決するため、第3
図の冷却構造が提案されている。第1図および第
2図と同等部分は、同一番号を付け説明を省略す
る。
Therefore, in order to further solve the above drawbacks, a third
The cooling structure shown in the figure is proposed. Portions equivalent to those in FIG. 1 and FIG. 2 are given the same numbers and their explanations will be omitted.

多数のLSIチツプ2とハウジング3Cの内面間
に流動性に富んだ高熱伝導性の流体13を充填さ
せた袋14が挿入されている。各LSIチツプ2は
この袋14に接触することにより冷却される。し
かし第3図の冷却構造においては下記の問題が生
ずる。すなわち、LSIチツプ2の冷却性能を高め
ようとすると、袋14との密着性を良くしなけれ
ばならない。そのため袋14の膜は第1図の場合
と同様に薄くて柔軟性のある膜が要求される。ま
た、第1図と異なり、袋14はLSIチツプ2の端
が接触するため、袋14が破断する恐れがあり、
長期使用に対する信頼性に問題がある。
A bag 14 filled with a highly fluid and highly thermally conductive fluid 13 is inserted between a large number of LSI chips 2 and the inner surface of the housing 3C. Each LSI chip 2 is cooled by contacting this bag 14. However, the following problem occurs in the cooling structure shown in FIG. That is, in order to improve the cooling performance of the LSI chip 2, the adhesion with the bag 14 must be improved. Therefore, the membrane of the bag 14 is required to be thin and flexible as in the case of FIG. Also, unlike in FIG. 1, the bag 14 comes in contact with the edge of the LSI chip 2, so there is a risk that the bag 14 will break.
There are problems with reliability for long-term use.

〔発明の目的〕[Purpose of the invention]

本発明は、以上述べた従来技術の問題点を解決
するためになされたもので、基板の反り、半導体
チツプの接続変位、冷却構造部の組立時の変形や
熱変形などさまざまの変位を吸収する機能を備
え、かつ、冷却性能のすぐれた冷却構造を備えた
半導体装置を提供することを、その目的としてい
る。
The present invention has been made in order to solve the problems of the prior art described above, and is capable of absorbing various displacements such as board warpage, connection displacement of semiconductor chips, deformation during assembly of the cooling structure, and thermal deformation. It is an object of the present invention to provide a semiconductor device equipped with a cooling structure that is functional and has excellent cooling performance.

〔発明の概要〕[Summary of the invention]

本発明に係る半導体装置の構成は、基板と、こ
の基板に実装される複数の半導体チツプと、この
半導体チツプを覆うように基板に装着されている
ハウジングとからなる半導体装置において、前記
基板と前記ハウジングとで形成される空間領域を
仕切るように、かつ、前記半導体チツプの上部を
覆うように可撓性のある仕切り膜を設け、当該仕
切り膜と前記ハウジングとで形成される空間領域
に、流動性のある高熱伝導性流体を充填し、さら
に、前記仕切り膜と前記半導体チツプの背面との
間に、流動性のある高熱伝導性流体を充填した複
数の枕を、前記複数の半導体チツプとおのおの独
立に接触するように配設したものである。
A semiconductor device according to the present invention includes a substrate, a plurality of semiconductor chips mounted on the substrate, and a housing attached to the substrate so as to cover the semiconductor chips. A flexible partition film is provided to partition a spatial region formed by the housing and to cover the upper part of the semiconductor chip, and a flexible partition film is provided to partition a spatial region formed by the housing and to cover the upper part of the semiconductor chip. Further, a plurality of pillows filled with a fluid and highly thermally conductive fluid are provided between the partition film and the back surface of the semiconductor chip, respectively. They are arranged so that they come into contact with each other independently.

なお付記すれば、本発明は、半導体装置のさま
ざまの変位を吸収するため、多数の半導体チツプ
の上面とハウジング内面との間に2重の可撓性冷
却構造を設けたことが特徴点である。すなわち、
基板の反り、冷却構造全体の変形など、各々の半
導体チツプに共通する大きな変位を吸収する機構
と、各々の半導体チツプの接続バラツキを吸収す
る機構とを別々に分離させたものである。
Additionally, the present invention is characterized in that a double flexible cooling structure is provided between the top surface of a large number of semiconductor chips and the inner surface of the housing in order to absorb various displacements of the semiconductor device. . That is,
A mechanism for absorbing large displacements common to each semiconductor chip, such as warpage of the substrate and deformation of the entire cooling structure, and a mechanism for absorbing connection variations of each semiconductor chip are separated.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の各実施例を各図を参照して説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

第4図は、本発明の一実施例に係る冷却構造を
備えた半導体装置の断面図、第5図、第6図、第
7図はいずれも本発明の他の実施例に係る冷却構
造を備えた半導体装置の断面図であり、これら各
図において、先の第1図と同一符号のものは、従
来技術と同等部分を示している。
FIG. 4 is a cross-sectional view of a semiconductor device equipped with a cooling structure according to one embodiment of the present invention, and FIGS. 5, 6, and 7 all show cooling structures according to other embodiments of the present invention. 1 is a sectional view of a semiconductor device equipped with the same technology. In each of these figures, the same reference numerals as in FIG. 1 indicate parts equivalent to those in the prior art.

まず、本発明の一実施例を第4図を参照して説
明する。
First, one embodiment of the present invention will be described with reference to FIG.

多数のLSIチツプ2は多層配線基板1と微小な
半田ボール7を介してフエースダン接合によつて
電気的な接続とチツプの固定とが行われている。
多数のLSIチツプ2を覆うようにハウジング3が
基板1に装着されている。多数のLSIチツプ2の
上面とハウジング3の内面との間に可撓性のよい
変形可能な仕切り膜15が設けられ、この仕切り
膜15とハウジング3内面とで形成される空間領
域に流動性に富んだ高熱伝導性の流体16が充填
されている。一方、仕切り膜15の反対側の表面
には、各複数のLSIチツプ2と相対応するおのお
の独立した複数の枕17が設けられている。これ
ら枕17は、各LSIチツプ2の背面とおのおの独
立に良好に接触しうるように、流動性で高熱伝導
性の流体16′が薄い被覆膜18によつて覆われ
ている。
A large number of LSI chips 2 are electrically connected and the chips are fixed by face-to-face bonding via a multilayer wiring board 1 and minute solder balls 7.
A housing 3 is attached to the board 1 so as to cover a large number of LSI chips 2. A highly flexible and deformable partition film 15 is provided between the upper surface of the large number of LSI chips 2 and the inner surface of the housing 3, and a fluidic region is provided in the space formed by the partition film 15 and the inner surface of the housing 3. It is filled with a rich and highly thermally conductive fluid 16. On the other hand, on the opposite surface of the partition film 15, a plurality of independent pillows 17 are provided, each corresponding to a plurality of LSI chips 2. These pillows 17 are covered with a fluid and highly thermally conductive fluid 16' by a thin coating film 18 so as to be able to come into good contact with the back surface of each LSI chip 2 independently.

なお、仕切り膜15は薄い金属箔あるいは合成
樹脂などで良い。
Note that the partition film 15 may be made of thin metal foil, synthetic resin, or the like.

また、流動性で高熱伝導性の流体16,16′
は液体金属あるいは熱伝導性グリースなどがよ
い。
In addition, the fluid 16, 16' is a fluid with high thermal conductivity.
is preferably a liquid metal or thermally conductive grease.

さらに、薄い被覆膜18は、内部の流体16′
に対し耐食性があり、熱伝導率ができるだけ大き
い耐熱性のものが良く、たとえば、パリレン膜
(商品名)などが好適である。その他の構造は従
来例と同一であるので、説明を省略する。
Additionally, the thin coating 18 may cause the internal fluid 16' to
It is preferable to use a heat-resistant material that has corrosion resistance and a thermal conductivity as high as possible, such as Parylene film (trade name). The rest of the structure is the same as the conventional example, so the explanation will be omitted.

次に上記のように構成された本実施例の作用に
ついて説明する。
Next, the operation of this embodiment configured as described above will be explained.

仕切り膜15には予じめ複数の枕17が設けら
れているが、上記構造を備えたハウジング3を基
板1の上にかぶせたのち、ハウジング3内の流体
封入孔19から流体16を仕切り膜15とハウジ
ング3内面との間にし封入すると、基板1の反
り、冷却構造全体の変形及び組立時の寸法誤差
は、仕切り膜15と流体16との変形によつて、
各LSIチツプ2の共通変位を吸収することができ
る。また、流体16の封入圧力をわずかに高める
ことにより、各LSIチツプ2と接する枕17も少
しづつ変形し、各LSIチツプ2の接続時のバラツ
キを吸収することができる。このような状態に冷
却構造が組み立てられると、LSIチツプ2から発
生する熱は複数の枕17を経て、仕切り膜15、
流体16、ハウジング3、冷却水流路9と次々に
伝わり冷却される。各複数のLSIチツプ2に複数
の枕17がおのおの独立に接触することができる
ため、冷却性能を著しく高めることができる。
A plurality of pillows 17 are provided in advance on the partition membrane 15. After the housing 3 having the above structure is placed over the substrate 1, the fluid 16 is supplied to the partition membrane from the fluid sealing hole 19 in the housing 3. 15 and the inner surface of the housing 3, warping of the substrate 1, deformation of the entire cooling structure, and dimensional errors during assembly are caused by the deformation of the partition film 15 and the fluid 16.
The common displacement of each LSI chip 2 can be absorbed. Furthermore, by slightly increasing the sealing pressure of the fluid 16, the pillow 17 in contact with each LSI chip 2 is also deformed little by little, and variations in connection of each LSI chip 2 can be absorbed. When the cooling structure is assembled in such a state, the heat generated from the LSI chip 2 passes through the plurality of pillows 17, and then passes through the partition membrane 15,
The fluid is transmitted to the fluid 16, the housing 3, and the cooling water channel 9 one after another and is cooled. Since the plurality of pillows 17 can contact each of the plurality of LSI chips 2 independently, the cooling performance can be significantly improved.

さらに、仕切り膜15と基板1とで形成される
空間領域に、高熱伝導性の気体、たとえばヘリウ
ムなどを充満させると、枕17とLSIチツプ2と
の接触熱抵抗を小さく抑えることができる。
Furthermore, if the spatial region formed by the partition film 15 and the substrate 1 is filled with a highly thermally conductive gas such as helium, the contact thermal resistance between the pillow 17 and the LSI chip 2 can be kept low.

次に、本発明の他の実施例を第5図を参照して
説明する。第5図の例は、第4図の例の一変形で
あり、第4図と同一符号は同等部分を示してい
る。
Next, another embodiment of the present invention will be described with reference to FIG. The example in FIG. 5 is a modification of the example in FIG. 4, and the same reference numerals as in FIG. 4 indicate equivalent parts.

本例では、仕切り膜20は、枕17をかこむよ
うに外周部に蛇腹構造部20aを備えている。先
の第4図の例で、仕切り腹が金属箔としても、箔
の可撓性は必ずしも大きくないので、第5図の例
では蛇腹構造部20aを設けることによつて仕切
り膜20の変形能力を高めたものである。
In this example, the partition membrane 20 includes a bellows structure portion 20a on the outer periphery so as to surround the pillow 17. In the example shown in FIG. 4, even if the partition belly is made of metal foil, the flexibility of the foil is not necessarily large, so in the example shown in FIG. It is an enhanced version of

次に、本発明のさらに他の実施例を第6図を参
照して説明する。第6図の例は、第4図または第
5図の例の枕7に対し工夫を加えたものであり、
第4図と同一符号のものは同一部分を示してい
る。
Next, still another embodiment of the present invention will be described with reference to FIG. The example in FIG. 6 is a modification of the pillow 7 in the example in FIG. 4 or 5,
The same reference numerals as in FIG. 4 indicate the same parts.

本例では、複数の枕17内に流体16′を充填
しやすくするため、仕切り膜15を枕内封止流体
16′との接触部に、介在部材に係る受け台21
を設けている。
In this example, in order to make it easier to fill the plurality of pillows 17 with the fluid 16', the partition membrane 15 is placed in contact with the in-pillow sealing fluid 16', and a cradle 21 associated with the intervening member is
has been established.

次に、本発明のさらに他の実施例を第7図を参
照して説明する。第7図の例は、第6図の例と同
一効果を期待する応用例であり、第4図と同一符
号のものは同一部分を示している。
Next, still another embodiment of the present invention will be described with reference to FIG. The example in FIG. 7 is an application example in which the same effect as the example in FIG. 6 is expected, and the same reference numerals as in FIG. 4 indicate the same parts.

本例では、複数の枕17内に流体16′を充填
しやすくするため、仕切り膜15′と枕内封止流
体16′との接触部に、介在部材に係る凸部1
5′aを設けたもので、凸部15′aは、仕切り膜
15′にわずかな凹凸を形成したものである。
In this example, in order to make it easier to fill the plurality of pillows 17 with the fluid 16', a convex portion related to the intervening member is placed at the contact area between the partition membrane 15' and the intra-pillow sealing fluid 16'.
5'a is provided, and the convex portion 15'a is formed by forming slight irregularities on the partition film 15'.

このような本発明の各実施例によれば、各LSI
チツプの変位を、基板全体の大きな変位と、各
LSIチツプ相互の小さなバラツキとに分離して吸
収することができる。このため、各LSIチツプと
ハウジング間の熱抵抗を小さく抑えることができ
る。したがつて、LSIチツプの熱的信頼性が高め
られ、結局、半導体装置を用いる電子機器全体の
信頼性を上げることができる。
According to each embodiment of the present invention, each LSI
We consider the displacement of the chip to be a large displacement of the entire board, and
Small variations between LSI chips can be separated and absorbed. Therefore, the thermal resistance between each LSI chip and the housing can be kept low. Therefore, the thermal reliability of the LSI chip is improved, and as a result, the reliability of the entire electronic device using the semiconductor device can be improved.

なお、前記の各実施例では、超大形コンピユー
タ等に用いられるLSIチツプを備えた半導体装置
の例を説明したが、本発明はLSIチツプのみに限
らず、同等の効果が期待できる半導体チツプを備
えた半導体装置の冷却構造の範囲で汎用的なもの
である。
In each of the above embodiments, an example of a semiconductor device equipped with an LSI chip used in an ultra-large computer, etc. was explained, but the present invention is not limited to only an LSI chip, but can also be applied to a semiconductor device equipped with a semiconductor chip that can be expected to have the same effect. This is a general-purpose cooling structure for semiconductor devices.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、半導体
装置の基板の反り、半導体チツプの接続変位、冷
却構造部の組立時の変形や熱変形などさまざまの
変位を吸収する機能を備え、かつ、冷却性能のす
ぐれた冷却構造を備えた半導体装置を提供するこ
とができる。
As explained above, according to the present invention, the present invention has a function of absorbing various displacements such as warpage of the substrate of a semiconductor device, connection displacement of semiconductor chips, deformation during assembly of the cooling structure, and thermal deformation, and A semiconductor device having a cooling structure with excellent performance can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来例の冷却構造を備えた半導体装
置の断面図、第2図は、他の従来例の冷却構造を
備えた半導体装置の断面図、第3図は、さらに他
の従来例の冷却構造を備えた半導体装置の断面
図、第4図は、本発明の一実施例の冷却構造を備
えた半導体装置の断面図、第5図は、本発明の他
の実施例の冷却構造を備えた半導体装置の断面
図、第6図、第7図は、いずれも本発明のさらに
他の実施例の冷却構造を備えた半導体装置の部分
断面図である。 1……基板、2……LSIチツプ、3……ハウジ
ング、15,15′……仕切り膜、15′a……凸
部、16,16′……高熱伝導性流体、17……
枕、20……仕切り膜、20a……蛇腹構造部。
FIG. 1 is a cross-sectional view of a semiconductor device equipped with a conventional cooling structure, FIG. 2 is a cross-sectional view of a semiconductor device equipped with another conventional cooling structure, and FIG. 3 is still another conventional example. FIG. 4 is a cross-sectional view of a semiconductor device equipped with a cooling structure according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view of a semiconductor device equipped with a cooling structure according to another embodiment of the present invention. 6 and 7 are all partial sectional views of a semiconductor device equipped with a cooling structure according to still another embodiment of the present invention. 1...Substrate, 2...LSI chip, 3...Housing, 15, 15'...Partition membrane, 15'a...Protrusion, 16, 16'...High thermal conductivity fluid, 17...
Pillow, 20... Partition membrane, 20a... Bellows structure part.

Claims (1)

【特許請求の範囲】 1 基板と、この基板に実装される複数の半導体
チツプと、この半導体チツプを覆うように基板に
装着されているハウジングとからなる半導体装置
において、前記基板と前記ハウジングとで形成さ
れる空間領域を仕切るように、かつ、前記半導体
チツプの上部を覆うように可撓性のある仕切り膜
を設け、当該仕切り膜と前記ハウジングとで形成
される空間領域に、流動性のある高熱伝導性流体
を充填し、さらに、前記仕切り膜と前記半導体チ
ツプの背面との間に、流動性のある高熱伝導性流
体を充填した複数の枕を、前記複数の半導体チツ
プとおのおの独立に接触するように配設したこと
を特徴とする冷却構造を備えた半導体装置。 2 特許請求の範囲第1項記載のものにおいて、
仕切り膜に蛇腹構造部を設けたものである冷却構
造を備えた半導体装置。 3 特許請求の範囲第1項または第2項記載のも
ののいずれかにおいて、流動性のある高熱伝導性
流体として、低融点の液体金属を用いたものであ
る冷却構造を備えた半導体装置。 4 特許請求の範囲第1項ないし第3項記載のも
ののいずれかにおいて、仕切り膜と基板とで形成
される空間領域に、高熱伝導性の気体を充満させ
たものである冷却構造を備えた半導体装置。 5 特許請求の範囲第1項ないし第4項記載のも
ののいずれかにおいて、仕切り膜と枕内封止流体
との接触部に、流体の充填を扶ける介在部材を設
けたものである冷却構造を備えた半導体装置。
[Claims] 1. A semiconductor device comprising a substrate, a plurality of semiconductor chips mounted on the substrate, and a housing attached to the substrate so as to cover the semiconductor chips, wherein the substrate and the housing A flexible partition film is provided to partition the formed spatial region and to cover the upper part of the semiconductor chip, and a flexible partition film is provided in the spatial region formed by the partition film and the housing. A plurality of pillows filled with a fluid highly thermally conductive fluid are filled between the partition membrane and the back surface of the semiconductor chip, and each pillow is independently contacted with the plurality of semiconductor chips. What is claimed is: 1. A semiconductor device equipped with a cooling structure, characterized in that the cooling structure is arranged so as to 2. In what is stated in claim 1,
A semiconductor device equipped with a cooling structure in which a bellows structure is provided on a partition membrane. 3. A semiconductor device according to claim 1 or 2, which includes a cooling structure that uses a low melting point liquid metal as a fluid and highly thermally conductive fluid. 4. A semiconductor provided with a cooling structure in which a spatial region formed by a partition film and a substrate is filled with a highly thermally conductive gas in any one of claims 1 to 3. Device. 5. In any one of claims 1 to 4, a cooling structure is provided in which an intervening member for assisting the filling of fluid is provided at the contact portion between the partition membrane and the sealing fluid in the pillow. Semiconductor device equipped with
JP14103183A 1983-08-03 1983-08-03 Semiconductor device with cooling structure Granted JPS6032348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14103183A JPS6032348A (en) 1983-08-03 1983-08-03 Semiconductor device with cooling structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14103183A JPS6032348A (en) 1983-08-03 1983-08-03 Semiconductor device with cooling structure

Publications (2)

Publication Number Publication Date
JPS6032348A JPS6032348A (en) 1985-02-19
JPH0342510B2 true JPH0342510B2 (en) 1991-06-27

Family

ID=15282604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14103183A Granted JPS6032348A (en) 1983-08-03 1983-08-03 Semiconductor device with cooling structure

Country Status (1)

Country Link
JP (1) JPS6032348A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012256792A (en) * 2011-06-10 2012-12-27 Toshiba Corp Heat dissipation structure
JP5861692B2 (en) * 2013-02-05 2016-02-16 株式会社デンソー Manufacturing method of heat dissipation structure

Also Published As

Publication number Publication date
JPS6032348A (en) 1985-02-19

Similar Documents

Publication Publication Date Title
US5184211A (en) Apparatus for packaging and cooling integrated circuit chips
US7629684B2 (en) Adjustable thickness thermal interposer and electronic package utilizing same
US12080614B2 (en) Lidded semiconductor package
JP2570498B2 (en) Integrated circuit chip carrier
US5952611A (en) Flexible pin location integrated circuit package
KR100575590B1 (en) Heat-Resistant Stacking Packages and Modules with They
US5953592A (en) Method of fabricating semiconductor having through hole
US6087203A (en) Method for adhering and sealing a silicon chip in an integrated circuit package
JP2000353767A (en) Board for mounting electronic component, package, mounting method, and method for housing integrated circuit chip in package
JPH08222671A (en) Cooler for circuit module
JPH0774282A (en) Semiconductor device
US7605020B2 (en) Semiconductor chip package
JPH07202463A (en) Electronic circuit module
TW200427016A (en) Flip chip package
JPH1117064A (en) Semiconductor package
CN100431143C (en) Semiconductor Package Structure
JPS59213151A (en) Cooling device for semiconductor element
JPH0342510B2 (en)
JPH0878572A (en) SEMICONDUCTOR PACKAGE, MANUFACTURING METHOD THEREOF, AND CIRCUIT BOARD AND ELECTRONIC DEVICE MOUNTING THE SAME PACKAGE
WO1989008327A1 (en) Method and apparatus for packaging and cooling integrated circuit chips
JP2710986B2 (en) Electronic equipment
JP2002289735A (en) Semiconductor device
JPH0582688A (en) Semiconductor integrated circuit device
JP7469410B2 (en) Electronic device and method for manufacturing electronic device
JP2715974B2 (en) Semiconductor device and manufacturing method thereof