JPH0340290A - Data transfer system and address converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer system and an address conversion device that include a bus master and a memory that perform burst transfer.

[Conventional technology]

Conventionally, this type of address translation device has been used to enable continuous burst transfer access from the bus master (usually cptt) to memory (usually SRAM) in block units in a data transfer system equipped with a bus master and memory that performs burst transfer. In order to achieve this, a system has been disclosed that generates an SRAM input lower address from a burst transfer request generated by a CPU and a burst compatible lower address.

This address translation device generates consecutive addresses based on the burst compatible lower address, which is the start address of the burst transfer generated by the CPU, while the burst transfer request generated by the CPU is asserted, and generates the lower address of the memory. give as.

[Problem to be solved by the invention]

By the way, as the operating frequency of microprocessor systems has increased in recent years, SRA with short access time has become available.
M has been developed, but in addition to the conventional chip enable access time from after the address input is confirmed until the chip enable signal is asserted and data is output, the chip enable signal is in the asserted state, that is, the memory chip is in the enabled state. The address access time from when a change in address input is detected to when data is output is defined. Most high speed S
For the RAM, the above two access times are the same, 7. That is, when performing address access,
Faster access can be achieved.

Here, address access is ATD (addraz
ztransition detect) method has been realized. However, when multiple address input lines change simultaneously, noise tends to occur inside the SRAM chip, and as a result of step 7, the internal write circuit malfunctions, causing the SR
Certain bits in the AM may be inverted, resulting in garbled information.

Problems with the conventional address translation device that implements burst transfer will be explained with reference to the timing diagram of FIG.

While the burst transfer request 13 generated by the CPU is asserted, the upper address 11 is also determined, and the burst-compatible lower address 12 indicating the start address of the burst transfer is also determined. Here, the burst compatible lower address 12 is °0°
Consider the case of

The conventional address translation device generates the SRAM input lower address 14 as 0°, °1", "2°, "3", that is, the burst compatible lower address 12 is 2b.
If it is expressed as a binary number, it is “00”, “0”.
1", "10", and 111". At this time, the address line A1 is connected to the SRAM input lower address 1401 bi
When the t-th is 0, it is L and tl, and when it is 1, it is H and tx.

Further, the address line AO becomes L when the 0th bit of the SRAM input lower address 14 is 00, and becomes H when it is 1. Therefore, at the point where the SRAM input lower address 14 changes from "1" to "2", the address line A1 changes from L to H, and the address line AO changes from H to L.

In this way, address lines A1. Since AO changes at the same time, these two address lines A1. The AO address change skinny (2) causes data corruption in the SRAM, and the burst read data 15 has a problem in that the data corresponding to the part where the SRAM input lower address 14 is @2° is corrupted.

An object of the present invention is to provide a data transfer system and an address conversion device that do not cause such data corruption.

[Means to solve the problem]

To achieve the above object, the data transfer system of the present invention uses SRAM input as a lower address.

Gray code (alternating binary code), an address that creates a binary code in which when consecutive numbers are expressed in binary, the representations of adjacent numbers differ by only one digit. Equipped with a conversion device.

Such an address translation device includes, for example, means for holding Gray code data, a means for receiving the burst transfer request and a burst compatible address generated by the bus master, and a means for holding the Gray code data including the memory. and a means for outputting a Gray code as a burst compatible lower address given to the address.

[Effect]

The address translation device generates a gray-coded address while a burst transfer request generated by the CPU is asserted based on a burst-compatible lower address that is a start address of a burst transfer generated by the CPU, and converts the lower address of the memory into Give it as an address.

In Gray-coded addresses, since the representations of adjacent consecutive binary numbers differ by one digit, the address lines change one by one, making it difficult for the information in the SRAM to become corrupted.

The present invention can be preferably used for accessing a cache memory using SRAM.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of the data transfer system of the present invention.

This system includes a CPU 1 that controls the entire system;
Burst compatible lower address 1 output by CPU 1 with
2 and the burst transfer request 13, an address translation device 2 generates a Gray coded address 14 which is an SRAM input lower address, and burst read data 15 corresponding to the upper address 11 and the Gray coded address 14 output by the CPU 1. and the memory 3 which outputs to the CPU 1 while the chip enable signal 16 is asserted.

FIG. 4 shows an embodiment of the address translation device 2. The address translation device 2 shown in FIG. 4 includes an incrementer 21 that increments a given initial value address using a clock signal, and a selector 22 that selects the address output from the incrementer 21;
and a control circuit 23 that generates a select signal based on the strobe signal and clock signal from the CPU 1 and controls switching of the selector 22.

The code conversion table 24 outputs a memory input address using the address output from the cough selector 22 as an index address.

The code conversion table 24 is composed of, for example, memory, registers, and the like. In this code conversion table 24,
For example, as shown in FIG.
A gray code is stored as table value 244 corresponding to 4g. In other words, this code conversion table 2
4 serves as a means for holding Gray code data.

Although an example of 3-hat code data has been shown here, it goes without saying that the code data is limited to this.Next, the data transfer system in FIG. will be explained with reference to the timing diagram of FIG.

The burst compatible lower address 12 indicates the start address of burst transfer while the burst transfer request 13 generated by the CPU 1 is asserted. here.

Consider the case where the burst compatible lower address 12 is 0°.

The address translation device 2 generates Gray coded addresses 14 such as "0", °1", °3°, and '2°.

Although FIG. 5 shows an example of a 5-bit gray code, for the sake of simplicity, the explanation will be given here assuming that the burst compatible lower address 12 is 2 bits.

During burst transfer, the first word is the burst transfer compatible initial value address bits output from CPU 1.

At this time, the control circuit 23 (see FIG. 3) receives the strobe signal from the CPU 1 and outputs a select signal that causes the selector 22 to select the initial value address.
The initial value address is sent to the code conversion table 24 through the kernel selector 22, and a gray code using this value as an index is output as an input address to the memory 30.

In addition to being sent to the selector 22, the initial value address is also input to the incrementer 21.

The subsequent word is incrementer 2 with the initial value set.
1 is incremented every clock, the output is sent to the code conversion table 24 via the selector 22, and the input address of the memory 3 is output in gray code. At this time, the selector 22 at the end of the control circuit 231 is controlled to select the output of the incrementer 21.

The output from the code conversion chifur 24 is a gray code as described above. In the case of 2b□t, when expressed in two escape numbers, they are 00", 01", 11, and 10.

By generating the gray coded address 14 in this way, address lines A1. Since AO does not change when open, the memory 3 transfers the burst read data 15 to the address lines A1. A
For the change point of n, output to CPU 1 after the delay time specified by address access time ■.

According to this embodiment, since the address lines change one by one when the burst compatible lower address of the SRAM input address is generated, burst transfer can be realized without garbled the data in the -5RAM.

Furthermore, even when writing data into the memory 3, the gray code described above is used, thereby making it possible to match the address at the time of reading.

〔Effect of the invention〕

As explained above, according to the present invention, when the CPU performs continuous burst transfer access to memory in block units, the representations of successive binary numbers that differ by only one digit differ from each other by one digit. Since addresses are generated, the address lines change one by one, making it possible to achieve address access that does not cause data corruption.
This has the effect of speeding up data transfer to the CPU.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the data transfer system of the present invention, FIG. 2 is a timing diagram of the operation of a conventional data transfer system, and FIG. 3 is a block diagram showing the configuration of an embodiment of the data transfer system of the present invention. FIG. 4 is a block diagram showing the configuration of an embodiment of the address translation device of the present invention, and FIG. 5 is an explanatory diagram showing an example of a code conversion table in the address translation device. 1・・・・・・・・・・・・・・・CPU (bus master) 2
・・・・・・・・・Address Henjima Device 3・・・・
...Memory (SRAM) 21...
...Incrementer 22...Selector 23...Control circuit

Claims (1)

[Scope of Claims] 1. In a data transfer system including a bus master that generates a burst transfer request and a memory, the burst transfer request and the burst corresponding address generated by the bus master are received, and the burst counterpart address is provided to the memory. A data transfer system comprising an address translation device that generates a lower address using a Gray code. 2. In an address translation device used in a data transfer system comprising a bus master that generates a burst transfer request and a memory, means for holding Gray code data; and means for causing the means for holding the Gray code data to output the Gray code as a burst compatible lower address given to the memory.