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JPH0338847A - Manufacture of hybrid integrated circuit device - Google Patents

Manufacture of hybrid integrated circuit device

Info

Publication number
JPH0338847A
JPH0338847A JP17462789A JP17462789A JPH0338847A JP H0338847 A JPH0338847 A JP H0338847A JP 17462789 A JP17462789 A JP 17462789A JP 17462789 A JP17462789 A JP 17462789A JP H0338847 A JPH0338847 A JP H0338847A
Authority
JP
Japan
Prior art keywords
chip
flip
integrated circuit
circuit device
loaded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17462789A
Other languages
Japanese (ja)
Inventor
Hiromi Sakata
坂田　博美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17462789A priority Critical patent/JPH0338847A/en
Publication of JPH0338847A publication Critical patent/JPH0338847A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To realize a high-density mounting operation by a method wherein a flip-chip IC is loaded on an insulating substrate on which a conductor pattern has been formed, it is connected by a reflow method, a TABIC is loaded on the upper part of the flip-chip IC and outer leads of the TABIC are connected by a thermocompression bonding method. CONSTITUTION:A conductor pattern 2 is formed on an insulating substrate 1; a flip-chip IC 7 on which solder bumps 8 have been formed is loaded and connected by a relow method. Then, a TABIC 9 is loaded on the upper part of the flip-chip IC 7; outer leads are connected by a thermocompression bonding method. In addition, a chip coating resin 6 is coated and cured. When the TABIC is loaded on the flip-chip IC so as to be piled up in this manner, a mounting area is reduced as compared with conventional methods and a high- density mounting operation can be realized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路装置の製造方法に関し、特に半導
体チップの実装工程を含む混成集積回路装置の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a hybrid integrated circuit device, and more particularly to a method for manufacturing a hybrid integrated circuit device including a semiconductor chip mounting process.

〔従来の技術〕[Conventional technology]

従来、複数の半導体チップを搭載した混成集積回路装置
は第３図に示すように、ＩＣチップ４を絶縁性基板１上
に接着樹脂３を用いて平面的に搭載し、Ａｕ線５を用い
てワイボンディングを行ない、ＩＣチップ４をチップコ
ート樹脂６にて被覆するのが一般的であった。Conventionally, in a hybrid integrated circuit device equipped with a plurality of semiconductor chips, as shown in FIG. Generally, the IC chip 4 is coated with a chip coat resin 6 by performing wire bonding.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の混成集積回路装置は、半導体チップを平
面的に配列しているので、実装面積が半導体チップの面
積により制約されるという欠点があった。The conventional hybrid integrated circuit device described above has the drawback that the mounting area is limited by the area of the semiconductor chips because the semiconductor chips are arranged in a plane.

本発明の目的は、実装面積が半導体チップの面積により
制約されない高密度実装が可能な混成集積回路装置の製
造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a hybrid integrated circuit device that allows high-density packaging in which the mounting area is not limited by the area of a semiconductor chip.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、複数の半導体チップを搭載した混成集積回路
装置の製造方法に於いて、導体パターンを形成した絶縁
性基板上にフリップチップＩＣを搭載しリフロー法によ
り接続する工程と、前記フリップチップＩＣの上部にＴ
ＡＢ　　ＩＣを搭載しＴＡＢ　　ＩＣのアウターリード
〜を熱圧着法により接続する工程とを含んで構成されて
いる。The present invention provides a method for manufacturing a hybrid integrated circuit device equipped with a plurality of semiconductor chips, including a step of mounting a flip-chip IC on an insulating substrate on which a conductor pattern is formed and connecting the flip-chip IC by a reflow method; T at the top of
The process includes the steps of mounting the AB IC and connecting the outer leads of the TAB IC by thermocompression bonding.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の第１の実施例の要部断面図である。FIG. 1 is a sectional view of a main part of a first embodiment of the present invention.

第１の実施例は第１図に示すように、まず、絶縁性基板
１上に導体パターン２を形成し、はんたバンプ８を形成
したフリップデツプＩＣ７を搭載し、リフロー法により
接続する。In the first embodiment, as shown in FIG. 1, a conductor pattern 2 is first formed on an insulating substrate 1, a flip-deep IC 7 with solder bumps 8 formed thereon is mounted, and connections are made by a reflow method.

次に、ＴＡＢ　　ＩＣ９を前記フリップチップＩＣ７の
上部に搭載し、熱圧着により、アウターリードを接続す
る。Next, the TAB IC9 is mounted on the flip chip IC7, and the outer leads are connected by thermocompression bonding.

次に、チップコート樹脂６を塗布し１５０°Ｃて１〜２
間キュアを行なう。Next, apply chip coat resin 6 and heat it at 150°C for 1 to 2 hours.
Perform a temporary cure.

第２図は本発明の第２の実施例の要部断面図である。FIG. 2 is a sectional view of a main part of a second embodiment of the present invention.

第２の実施例は、第２図に示すように、導体パターン２
を有する絶縁性基板１は、フリップチップＩＣ７の搭載
部に凹みを有している。凹みの深さＴは、フリップチッ
プＩＣ７のはんだハンプ８を含み厚さと同等にする。In the second embodiment, as shown in FIG.
The insulating substrate 1 has a recess in the mounting portion of the flip chip IC 7. The depth T of the recess is equal to the thickness including the solder hump 8 of the flip chip IC 7.

フィリップチップＩＣ７，ＴＡＢ　　ＩＣ９の接続方法
は、第１の実施例と同じである。The method of connecting the Philips chip IC7 and TAB IC9 is the same as in the first embodiment.

この実施例では、フリップチップＩＣ搭載部に凹みを有
する事により、全体の厚みを薄く出来る利点がある。This embodiment has the advantage that the overall thickness can be reduced by having a recess in the flip-chip IC mounting portion.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、フリップチップＩＣ上に
ＴＡＢ　　ＩＣを重ねて搭載することにより、実装面積
を従来より小さく出来、より高密度実装が可能となると
いう効果がある。As explained above, the present invention has the advantage that by mounting the TAB IC on top of the flip chip IC, the mounting area can be made smaller than conventionally, and higher density packaging becomes possible.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の第１の実施例の要部断面図、第２図は
本発明の第２の実施例の要部断面図、第３図は従来の混
成集積回路装置の一例の要部断面図である。FIG. 1 is a sectional view of a main part of a first embodiment of the present invention, FIG. 2 is a sectional view of a main part of a second embodiment of the invention, and FIG. 3 is a main part of an example of a conventional hybrid integrated circuit device. FIG.

Claims (1)

【特許請求の範囲】[Claims] 　複数の半導体チップを搭載した混成集積回路装置の製
造方法に於いて、導体パターンを形成した絶縁性基板上
にフリップチップＩＣを搭載しリフロー法により接続す
る工程と、前記フリップチップＩＣの上部にＴＡＢ　Ｉ
Ｃを搭載しＴＡＢ　ＩＣのアウターリードを熱圧着法に
より接続する工程とを含むことを特徴とする混成集積回
路装置の製造方法。A method for manufacturing a hybrid integrated circuit device equipped with a plurality of semiconductor chips includes a step of mounting a flip chip IC on an insulating substrate on which a conductive pattern is formed and connecting it by a reflow method, and a step of mounting a TAB on the top of the flip chip IC. I
1. A method for manufacturing a hybrid integrated circuit device, comprising a step of mounting a TAB IC and connecting outer leads of a TAB IC by thermocompression bonding.
JP17462789A 1989-07-05 1989-07-05 Manufacture of hybrid integrated circuit device Pending JPH0338847A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17462789A JPH0338847A (en) 1989-07-05 1989-07-05 Manufacture of hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17462789A JPH0338847A (en) 1989-07-05 1989-07-05 Manufacture of hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0338847A true JPH0338847A (en) 1991-02-19

Family

ID=15981902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17462789A Pending JPH0338847A (en) 1989-07-05 1989-07-05 Manufacture of hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0338847A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001037332A1 (en) * 1999-11-16 2001-05-25 Indian Space Research Organisation A high density hybrid integrated circuit package having a flip-con structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001037332A1 (en) * 1999-11-16 2001-05-25 Indian Space Research Organisation A high density hybrid integrated circuit package having a flip-con structure

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