JPH0335586U - - Google Patents
Info
- Publication number
- JPH0335586U JPH0335586U JP9687389U JP9687389U JPH0335586U JP H0335586 U JPH0335586 U JP H0335586U JP 9687389 U JP9687389 U JP 9687389U JP 9687389 U JP9687389 U JP 9687389U JP H0335586 U JPH0335586 U JP H0335586U
- Authority
- JP
- Japan
- Prior art keywords
- vram
- cpu
- display
- cpu access
- chip select
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003213 activating effect Effects 0.000 claims 1
- 230000004913 activation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Landscapes
- Digital Computer Display Output (AREA)
Description
第１図は、この考案の表示装置について、その
要部構成の詳細な一実施例を示す機能ブロツク図
、第２図は、この考案の表示装置について、その
ノーマルモードの動作を説明するためのタイミン
グチヤート、第３図は、この考案の表示装置につ
いて、そのノーウエイトモードの動作を説明する
ためのタイミングチヤート。
図面において、１……表示コントローラで、１
１……そのＶＲＡＭチツプセレクト検出部、１２
……ＶＲＡＭ制御信号生成部、１３……モード切
換え制御部、１４……ＶＲＡＭアドレスカウンタ
、１５……ＣＰＵ／表示アドレス切換え部、１６
……ＣＰＵ／表示データ切換え部、１７……表示
データバツフア、１８……バツフア入出力制御部
、１９……表示情報合成部、２……ＣＰＵ、３…
…ＶＲＡＭ、４……ＣＲＴデイスプレイ等の表示
装置。
FIG. 1 is a functional block diagram showing a detailed example of the main configuration of the display device of this invention, and FIG. 2 is a functional block diagram for explaining the normal mode operation of the display device of this invention. Timing Chart FIG. 3 is a timing chart for explaining the operation of the display device of this invention in the no-wait mode. In the drawing, 1...Display controller, 1
1... VRAM chip select detection section, 12
... VRAM control signal generation section, 13 ... Mode switching control section, 14 ... VRAM address counter, 15 ... CPU/display address switching section, 16
...CPU/display data switching unit, 17...Display data buffer, 18...Buffer input/output control unit, 19...Display information synthesis unit, 2...CPU, 3...
...VRAM, 4...Display device such as CRT display.
Claims (1)
表示手段とを備えた表示装置において、 ＣＰＵからのＶＲＡＭのチツプセレクト信号が
入力されたとき、表示用ＶＲＡＭアドレスカウン
ターを一時停止させ、ＣＰＵのアクセス終了後カ
ウントを再開し、かつ、ＣＰＵアクセス用期間に
ＣＰＵのアクセスがないときにカウントするアド
レスカウンタと、 ＣＰＵアクセス用期間でＣＰＵのアクセスがな
いとき、前記ＶＲＡＭのチツプセレクト信号をア
クテイブにするチツプセレクト信号アクテイブ手
段と、 ＶＲＡＭデータをＣＰＵ側と表示側と切換える
ＶＲＡＭデータ切換え手段と、 該ＶＲＡＭデータ切換え手段から出力される表
示用のデータを格納するバツフアメモリと、 通常の時分割方式をノーウエイトモードに切換
えるモード切換え手段、 とを前記表示コントローラへ設けたことを特徴
とする表示装置。[Scope of utility model registration claims] CPU, VRAM, display controller,
In a display device equipped with a display means, when a VRAM chip select signal from the CPU is input, the display VRAM address counter is temporarily stopped, the count is restarted after the CPU access is completed, and the CPU access period is an address counter for counting when there is no CPU access during the CPU access period; chip select signal activation means for activating the chip select signal of the VRAM when there is no CPU access during the CPU access period; and displaying the VRAM data on the CPU side. The display controller is provided with: a VRAM data switching means for switching between the two sides, a buffer memory for storing display data output from the VRAM data switching means, and a mode switching means for switching from a normal time division method to a no-wait mode. A display device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9687389U JPH0335586U (en) | 1989-08-19 | 1989-08-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9687389U JPH0335586U (en) | 1989-08-19 | 1989-08-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0335586U true JPH0335586U (en) | 1991-04-08 |
Family
ID=31646049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9687389U Pending JPH0335586U (en) | 1989-08-19 | 1989-08-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0335586U (en) |
-
1989
- 1989-08-19 JP JP9687389U patent/JPH0335586U/ja active Pending
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