JPH033251B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD The present invention relates to a logic integrated circuit used in an arithmetic control circuit or the like in a computer capable of generating, applying, and observing test data. Prior Art Conventionally, there are the following testing methods for logic circuits. That is, in the first method, test data is generated, applied, and observed in synchronization with a clock pulse given to a logic circuit (hereinafter referred to as a sequential circuit) that includes a plurality of flip-flops (hereinafter referred to as F/Fs). is going on. However, this method requires a lot of effort for testing because it does not use an efficient algorithm for generating test data. In order to improve this drawback, a scan pass method has been proposed in which a shift register is formed by cascaded F/Fs and a test is performed by sequentially scanning in and scanning out the data of these F/Fs during testing. Details of this method can be found in the 12th publication published by IEEE in 1975.
Page 114 of “Design Automation Conference”
The paper “TEST GENERATION SYSTEMS IN” by S.Funatsu et al on page 122
However, this method has the disadvantage that it takes time to scan in and scan out the test data. A loop is provided to generate a test bit pattern using pseudo-random numbers, and a test is performed by giving each of the test bit patterns. There has also been proposed a test method that includes a data compression function to reduce test result data by performing a logical operation and outputting the result of the operation (the test result cannot be reproduced from the result of the operation). Details of this method can be found in the publication “1979 IEEE Test Conference” published by IEEE in 1979.
Bernd Ko¨nemann et al on pages 37 to 41
Paper “BUILT−IN LOGIC BLOCK” by
OBSERVATION TECHNIQUES". This method automatically generates a test bit pattern internally and compresses the test results, reducing the amount of data output from the circuit under test, thereby reducing test time. However, it is not possible to divide the circuit under test into multiple parts and test each divided circuit individually.Therefore, when testing, the test must be performed on the entire target circuit. As a result, there is a drawback that a large amount of test data and time are required.Object of the Invention An object of the present invention is to provide a logic integrated circuit that solves the above-mentioned drawbacks.Configuration of the InventionA bit pattern consisting of a plurality of signals. a combinational circuit which receives bit patterns in parallel and outputs bit patterns in parallel; a master side flip-flop group which receives part of the bit patterns from this combinational circuit in parallel; a slave-side flip-flop group for receiving a bit pattern from the flip-flop group and feeding it back to the combinational circuit; an additional front-stage additional flip-flop for making each of the master-side flip-flops into a master-slave flip-flop configuration; Constructing a shift register having a feedback loop by vertically sustaining an additional flip-flop in the previous stage,
a master-side connection circuit that operates as a data compressor for the output of the test circuit in a test mode; an additional flip-flop at a subsequent stage for configuring each of the slave-side flip-flop groups into a master-slave flip-flop configuration; and the slave-side flip-flop and the subsequent stage. A shift register with a feedback loop is constructed by cascade-connecting additional flip-flops.
It is equipped with a slave-side connection circuit that operates as a random number generator in test mode. Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, the logic circuit of the present invention includes a combinational circuit 101, a part of the output of this combinational circuit 101 is inputted through lines 130-1 to 130-n, and the output line is connected to a line 140-1. A master-slave flip-flop (hereinafter referred to as F/F) group 1 which partially inputs to the combinational circuit 101 through 140-n.
02, a terminal 103 for scanning in the bit pattern to the F/F group 102, a terminal 104 for scanning out the bit pattern, the F/F group 106,
Input terminal group 110 for the combinational circuit 101
-1 to 110-n, and output terminal group 120-1
~120-n. The combinational circuit 101 includes US Patent
Described in Fig. 5 of No. 3761695
COMBINATIONAL NETWORK 40, 41 and 42 can be used. In normal mode operation, this circuit uses the F/F group 102 as a normal master-slave F/F group. The circuit under test, which is the entire configuration of FIG. 1, is operated as a synchronous sequential circuit.
When testing this circuit, the F/F group 102 is replaced with a shift register by control signals from control signal terminals 105 and 106.
By serially applying a test bit pattern from 03 onwards, the input of the combinational circuit 101 can be set to an arbitrary bit. Furthermore, since the bit pattern value set in the F/F group 102 can be observed serially via the terminal 104, the output bit pattern of the combinational circuit 101 is output from the output terminal 120-
1 to 120-n can be fully observed in conjunction with the test result bit pattern. Referring to FIG. 2, the first example of the F/F group 102 includes master side F/Fs 201, 202, 20
3, 204, ... 207, and 208, slave side F/F 211, 212, 213, 214, ...
...217 and 218, mode switching circuit 22
0, 222, 230, and 240 and exclusive OR circuits (EORs) 25
It consists of 0 and 260. In normal mode operation, the bit pattern flows from the master side F/F 201 to the slave side F/F 211, and when setting the initial bit pattern during testing, the F/Fs 211, 212, 212, which take a shift register configuration from the scan-in terminal 103, ...2
The bit pattern is set at 17 and 218. Similarly, when observing the F/F bit pattern, use the scan out terminal 10 from the shift register.
The bit pattern is output via 4. Furthermore, during testing, the feedback loop can be used to perform EOR between the bit pattern in the previous stage of the shift register and the bit pattern from the loop. Referring to FIG. 3A, the mode switching circuit 220 in FIG. 2 is composed of an OR gate 301, an AND gate 302, an EOR gate 303, and a true complement gate 304 that outputs both a true signal and a complementary signal. Next, the operation of this mode switching circuit 220 will be explained in detail. In this circuit, an input bit pattern is applied to the output line 311 from the master side F/F 201 via the line 321 according to the values from the terminals 105 and 106, and an input bit pattern is applied to the scan-in terminal 10.
3 through the line 322 and the feedback loop and the subsequent F/F2.
12 and each output is EORed to line 32
Any of the bit patterns given through 3 is output. The detailed operation of this circuit can be shown in Table 1 as follows. Referring to FIG. 3B, the mode switching circuit 222 of FIG. 2 is comprised of an OR gate 301, an AND gate 302, and a true complement gate 304 that outputs both a true signal and a complementary signal. In this circuit, the output line 311 is connected to the master side F/Fs 203, 205 and 207 in FIG.
Either the bit pattern given through the line 321 from the F/Fs 212, 214, and 216 in FIG. 2 is outputted. Details of this circuit

【table】

[Table] The detailed operations can be shown in Table 2 above. Referring to FIG. 3C, the mode switching circuit 230 in FIG.

[Table] In this circuit, as shown in FIG. 2, the output line 331 receives the bit pattern and feed input from the circuit 101 in FIG. Back loop and rear F/
The respective outputs of F202 are subjected to EOR and one of the logical values indicated by the bit pattern and ground potential provided via line 333 is output. Details of this operation can be shown in Table 3 as described above. Referring to FIG. 3D, the mode switching circuit 240 of FIG. 2 is composed of an OR gate 301, an AND gate 302, an exclusive OR circuit 303, and a true complement gate 304 that outputs both a true signal and a complementary signal. . In this circuit, the output line 331 receives the bit pattern shown in FIG. Line 1 from combinational circuit 101
30-2, 130-3, 130-4 and 342
Either the bit pattern given through the line 341 or the bit pattern obtained by EORing the bit pattern given through the line 341 and the bit pattern given through the line 342 are output.

[Table] Details of this operation can be shown in Table 4 as described above. Next, the operation of this embodiment will be explained in detail with reference to FIGS. 1 to 8 and Tables 1 to 4. The operation of this embodiment is divided into a normal operation and a test operation consisting of initial setting, testing, and test result observation. A Normal operation When the values of the control signals from the terminals 105 and 106 in FIG. 1 become "1, 1", the lines 130-1 to 130-
Bit patterns are provided in parallel via m. This bit pattern is applied to the switching circuits 230 and 240 in FIG. 2 in the F/F group 102 in FIG. 1, the master side F/F group 201, 203,
205 and 207, switching circuits 220 and 221, slave side F/F groups 211, 21
3,215 and 217 and line 140-1,
Feedback is provided to the combinational circuit 101 via 140-2, 140-3 and 140-4. Note that the switching circuits 220, 22
2, 230 and 240 perform operations in normal mode as shown in Tables 1 to 4. B Test Operations (a) Initial Settings Initial setting operations are first performed in reset mode and shift mode. First, in reset mode, all F/F 201 shown in Fig.
-208 and 211-218 are set to "0". The switching circuits 220, 22
2, 230 and 240 operate in the normal mode as shown in Tables 1 to 4. Then, in shift mode, the master side F/
F groups 201-208 operate in shift mode. The input bit pattern to this shift register is determined by the output bit pattern of switching circuit 230. terminals 105 and 1
Since the value of the control signal forming the above-mentioned shift mode given from 06 is "1, 0", as is clear from Table 3, the operation is the same as the reset mode, and the output bit of the switching circuit 230 becomes "0". , the switching circuit 24
As is clear from Table 4, 0 is the master side F/F group 201- for operating in shift mode.
208 operates as a shift register and the F/
The output bits of F group 201-208 are all "0". Since the switching circuits 220 and 222 also operate in the shift mode from Tables 1 and 2, the slave side F/F group 21
1-218 also operates as a shift register. This input bit pattern is “0,
0, 0 and 1” are scan-in terminals 103
When set to , the slave side F/F group 2
The bit pattern of 11-218 is “1, 1,
0, 0, 0, 0 and 0''. These are the initial values to be set in the circuit 101 as the test bit pattern. (b) Test The test is conducted under feedback mode. That is, the terminal 105 When control signals "0, 1" are applied from 106 and 106, the switching circuits 220, 230 and 240 operate in the feedback mode shown in Tables 1, 3 and 4, and the switching circuit 222 operates in the feedback mode shown in Tables 1, 3 and 4.
It operates in the shift mode shown in . As a result, the entire configuration shown in FIG. 2 becomes equivalent to the configurations shown in FIGS. 4 and 6. Of the configuration shown in FIG. 2, the master side F/F group 201-208 and their peripheral circuits are shown in FIG.
8 and its peripheral circuits are shown in FIG. Referring to Figure 4, slave side F/F2
F/F circuits 211 and 21 in response to the supply of clock pulses to each of F/F circuits 11-218.
The output bit patterns Q ₁ , Q ₂ , Q ₃ and Q ₄ of 3, 215 and 217 vary as shown in FIG. Referring to Figure 5, clock cycle 0
In the output bit patterns Q ₁ , Q ₂ ,
Q ₃ and Q ₄ are set to “1, 0, 0 and 0”. Then clock cycle 1-
At 14, all different bit patterns are generated sequentially. clock cycle 15-29
Similar patterns are also generated from the F/F circuits 211, 213, 215 and 217. These bit patterns are
It is determined from the combination of the contents of Q ₁ , Q ₂ , Q ₃ and Q ₄ and can be used as a random number. That is, the configuration shown in FIG. 4 functions as a linear, feedback register random number generator. Referring to FIG. 6, in response to the supply of clock pulses to each of the master side F/F groups 201-208, the F/F circuits 201 and 20
The output bit patterns Q ₁ , Q ₂ , Q ₃ and Q ₄ of No. 3, 205 and 207 vary as shown in FIG. Referring to FIG. 7, first, at clock cycle 0, the F/F circuits 201, 203, 2
Output bit pattern Q ₁ of 05 and 207,
Q ₂ , Q ₃ and Q ₄ are (0, 0, 0 and 0)
It is. Signal line 1 in the next clock cycle 1
30-1, 130-2, 130-3 and 1
The bit pattern “0, 0,
0 and 1'' are given, the F/F
The output bit patterns Q ₁ , Q ₂ , Q ₃ and Q ₄ of circuits 201, 203, 205 and 207 are "0, 0, 0 and 1". Similarly below
When 15 clocks and a bit pattern as shown in FIG. 7 are supplied, the F/F circuits 201, 203, 205
and 207 output bit patterns Q ₁ , Q ₂ ,
Q ₃ and Q ₄ are “1, 0, 0, and 1”. (c) Observation of test results Referring to FIG. 8, the combinational circuit 10
Failure detection of No. 1 is performed as follows.
That is, the signal lines 130-1, 130-2,
Combinational circuit 10 supplied with bit patterns via 130-3 and 130-4
A failure occurs within 1. If the effect of the failure appears on the signal line 130-3 in clock cycle 9, the effect will be on the master side F/
It is sequentially transmitted to F groups 201-208. As a result, the output bit patterns Q ₁ , Q ₂ ,
Q ₃ and Q ₄ become (1, 1, 1 and 0). This is the F/F circuit 20 in a normal case.
1, 203, 205 and 207, i.e., Q ₁ , Q ₂ ,
Q ₃ and Q ₄ are (1, 0, 0, and 1), and the pattern (1, 1, 1, and 0) is different from the pattern "1, 0, 0, 1", so a failure is detected. It can be performed. As described above, the master side F/F group 201-208 observes the output bit patterns of the F/F circuits 201, 203, 205, and 207 in a specific observation cycle (clock cycle 15 in this example). Therefore, the output bit pattern Q ₁ − in every cycle is
Since it is possible to detect failures without observing the state of _Q4 , it works as a data compression device for test circuit output. In other words, in Fig. 2, the master side F/F
Circuits 201, 202, 203, 204,...
By configuring . . Figures 9 and 10
Each figure shows the second F/F group 102 in FIG.
An example and a third example are shown below. Comparing the first example shown in FIG. 2 and the second example shown in FIG. 9 of the F/F group 102,
In the first example of FIG. 2, one input terminal of EOR circuits 250 and 260 is connected to the output terminals of F/Fs 202 and 212. However, in the second example of FIG.
It is connected to 14 output terminals. When comparing and referring to FIG. 10 showing the third example of the F/F group 102 in FIG. 1 and FIG. 2 showing the first example, the example in FIG.
The other input terminals of EORs 250 and 260 are connected to the output terminals of F/Fs 208 and 218. However, in the example shown in Figure 10,
The other input terminals of EORs 250 and 260 are connected to the output terminals of F/Fs 208 and 218. 11 to 13 are diagrams for explaining the operation of the second example of FIG. 9. Next, the operation of the second embodiment of the present invention will be described with reference to FIGS. 1, 9, and 11 to 13. The initial settings in the normal operation and test operation in this embodiment are the same as those in the first embodiment. However, in the initial setting, when "0, 1, 0 and 1" is given as the input bit pattern from the scan-in terminal shown in FIG.
The bit pattern of groups 211-218 is “1,
1, 0, 0, 1, 1, 0 and 0''. Referring to FIG. 11, at clock cycle 0, the output bit patterns Q ₁ ,
Q ₂ , Q ₃ and Q ₄ are “1, 0, 1 and 0”
is set to Subsequently, all different bit patterns are generated sequentially in clock cycles 1-8. These bit patterns are determined from the combination of the contents of Q ₁ , Q ₂ , Q ₃ and Q ₄ and can be used as random numbers. Referring to FIG. 12, first, at clock cycle 0, the F/F circuits 201, 203,
Output bit pattern of 205 and 207
Q ₁ , Q ₂ , Q ₃ and Q ₄ are “0, 0, 0, and 0”. When the bit patterns "0, 0, 0 and 1" are applied via signal lines 130-1, 130-2, 130-3 and 130-4 in the next clock cycle 1, the output bit patterns Q ₁ , Q ₂ , Q ₃ and Q ₄
becomes "0, 0, 0 and 0". Referring to FIG. 13, the combinational circuit 1
01 failure detection is performed as follows. That is, the signal lines 130-1, 130-
2, 130-3 and 130-4, the effect of the failure is transmitted to the master side F/2 via signal line 130-2 in clock cycle 1. It is sequentially transmitted to F groups 201-208. As a result, clock cycle 8
Output bit pattern Q ₁ , Q ₂ , Q ₃ and
Q ₄ becomes "1, 1, 1 and 0". This is different from the output bit pattern "0, 1, 0, and 1" shown in FIG. 12 in the normal case, and failure detection can be performed based on this difference. As mentioned above, the master side F/F
Groups 201-208 are F/F circuits 201, 203, 205 and 2 at clock cycle 8.
By observing the output bit patterns Q ₁ - _{Q 4} of 07, it is possible to detect failures without observing the states of the output bit patterns Q ₁ - _{Q 4} in every clock cycle, and it can be used as a data compression device for test circuit output. Operate. 14 to 16 are diagrams for explaining the operation of the third example shown in FIG. 10. Next, Figure 1,
The operation of the third embodiment of the present invention will be described with reference to FIG. 10 and FIGS. 14 to 16. The initial settings in the normal operation and test operation in this embodiment are the same as those in the first embodiment. Referring to FIG. 14, in clock cycle 0, slave side F/F circuits 211, 2
The output bit patterns Q ₁ -Q ₄ of 13, 215 and 217 are set to "1, 0, 0 and 0". Then clock cycle 1-
5, all different bit patterns are generated sequentially. These bit patterns are Q ₁
−Q It is determined from the combination of the contents of ₄ and can be used as a random number. Referring to FIG. 15, at clock cycle 0, similar to the operation in FIG.
F/F circuits 201, 203, 205 and 2
The output bit pattern _Q1 - _Q4 of 07 is “0,
0, 0 and 0''. In the next clock cycle 1, signal lines 130-1, 130-2, 1
When the bit patterns "0, 0, 0 and 1" are applied through the output terminals 30-3 and 130-4, the output bit patterns _Q1 - _Q4 are "0, 0, 0 and 1".
0, 0 and 0''. Referring to FIG. 16, the combinational circuit 1
01 failure detection is performed as follows. That is, the signal lines 130-1, 130-
2, 130-3 and 130-4.
When a failure occurs in clock cycle 1, the effect of this failure occurs on signal line 130-2 of clock cycle 1 and is sequentially transmitted to master side F/F groups 201 and 208. As a result, clock cycle 5
The output bit pattern Q ₁ −Q ₄ is “1, 1,
0 and 1". This corresponds to the output bit pattern "1, 1,
1" and 1", and failure detection can be performed based on this difference.As described above, the master side F/F group 201-2
08 is F/F circuit 2 at clock cycle 5
By observing the output bit patterns Q ₁ -Q ₄ of 01, 203, 205 and 207,
Failure detection is possible without observing the states of the output bit patterns _Q1 - _Q4 in every clock cycle, and the circuit operates as a data compression device for the test circuit output. Effects of the Invention In other words, the present invention has the advantage that by configuring the flip-flop group as a shift register with a feedback loop for both master side and slave side systems, each operation of generating/applying test data and observing can be easily realized. effective.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of the present invention, and FIG. 2 is a diagram showing the configuration of the present invention.
A diagram showing the detailed configuration of the F/F group shown in the figure, 3rd A
3D is a diagram showing the detailed configuration of the switching circuit in FIG. 2, FIGS. 4 to 8 are diagrams for explaining the operation of the first embodiment of the present invention, and FIG. 10
The figure shows a modification of Fig. 2, Figs. 11-13.
The figure is a diagram for explaining the operation of FIG. 9, and FIGS. 14 to 16 are diagrams for explaining the operation of FIG. 10. In FIGS. 1 to 16, 101...combination circuit, 102...master/slave F/F
Group, 103...Scan-in terminal, 104...
Scan out terminals, 105, 106...Operating mode control terminals, 110-1 to 110-l...Input terminal group, 120-1 to 120-n...Output terminal group, 130-1 to 130-m... Combinational circuit output, 140-1 to 140-m... Combinational circuit input, 201, 202, 203, 204, 20
5,206,207,208...Master side F/
F, 211, 212, 213, 214, 215,
216, 217, 218...Slave side F/F,
220, 222, 230, 240...Switching circuit, 221...Clock signal, 241, 242,
243, 244, 245, 246, 247, 24
8...Clock supply signal to each F/F, 250,
260...Exclusive OR gate, 301...OR
Gate, 302...AND gate, 303...Exclusive OR gate, 304...True complementary gate, 31
1... Output signal of switching circuits 220, 222,
321...Data input signal, 322...Shift/
data signal, 323...feedback signal,
331... Output signal of switching circuits 230, 240, 332... Data input signal of switching circuit 230, 333... Feedback signal of switching circuit 230, 341... Shift data signal of switching circuit 240, 342... Switching circuit 24
0 data input signal.

Claims (1)

[Scope of Claims] 1. A combinational circuit that receives bit patterns consisting of a plurality of signals in parallel and outputs the bit patterns in parallel, a master side flip-flop group that receives part of the bit patterns from this combinational circuit in parallel, and A slave-side flip-flop group is provided corresponding to each flip-flop in the master-side flip-flop group and receives a bit pattern from the flip-flop group and returns it to the combinational circuit, and each of the master-side flip-flop groups is configured as a master-slave flip-flop. A shift register having a feedback loop is constructed by cascade-connecting the master side flip-flop and the preceding additional flip-flop,
a master-side connection circuit that operates as a data compressor for the output of the test circuit in a test mode; an additional flip-flop at a subsequent stage for configuring each of the slave-side flip-flop groups into a master-slave flip-flop configuration; and the slave-side flip-flop and the subsequent stage. A shift register with a feedback loop is constructed by cascade-connecting additional flip-flops.
A logic integrated circuit comprising: a slave-side connection circuit that operates as a random number generator in a test mode.