JPH0330988B2 - - Google Patents
Info
- Publication number
- JPH0330988B2 JPH0330988B2 JP59118460A JP11846084A JPH0330988B2 JP H0330988 B2 JPH0330988 B2 JP H0330988B2 JP 59118460 A JP59118460 A JP 59118460A JP 11846084 A JP11846084 A JP 11846084A JP H0330988 B2 JPH0330988 B2 JP H0330988B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor element
- film
- display panel
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 13
- 229920005989 resin Polymers 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000003825 pressing Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000016 photochemical curing Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000009125 cardiac resynchronization therapy Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ELデイスプレイパネルや液晶デイ
スプレイパネルと、これを駆動する半導体素子と
の接続の構造ならびにその製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a connection structure between an EL display panel or a liquid crystal display panel and a semiconductor element for driving the same, and a manufacturing method thereof.
従来例の構成とその問題点
近年、液晶デイスプレイパネルやELデイスプ
レイパネルを用いて、画像表示や文字表示する機
器が増加している。これらデイスプレイパネルは
肉厚を薄くできる特徴はあるものの、鮮明な画像
や高精細度のキヤラクターを表示する場合、前記
デイスプレイパネルに形成されている走査線の数
を増やさなければならない。この事は、液晶デイ
スプレイやELデイスプレイがよりCRTの表示性
能に接近し、附加価値を高めるうえでも不可欠の
事である。ところが、前記走査線の数を増やして
しまうと、デイスプレイパネルの電極数も比例し
て増大する。電極数の増大は、これを駆動するた
めの駆動用のLSIの数も増大する結果となるもの
である。Conventional configurations and their problems In recent years, the number of devices that display images and characters using liquid crystal display panels and EL display panels has increased. Although these display panels have the feature that they can be made thinner, in order to display clear images or high-definition characters, it is necessary to increase the number of scanning lines formed on the display panel. This is essential for liquid crystal displays and EL displays to approach the display performance of CRTs and increase added value. However, if the number of scanning lines is increased, the number of electrodes of the display panel will also increase proportionally. An increase in the number of electrodes results in an increase in the number of driving LSIs for driving the electrodes.
したがつて、液晶デイスプレイパネルやELデ
イスプレイパネルの性能向上を計ろうとすれば、
必然的に、前記駆動用LSIとデイスプレイパネル
の電極との接続点数が増え、信頼性を低下さす原
因となるばかりか、実装コストが著じるしく増大
し、実用化をはばむ原因となつている。 Therefore, if you are trying to improve the performance of LCD display panels or EL display panels,
Inevitably, the number of connection points between the driving LSI and the electrodes of the display panel increases, which not only causes a decrease in reliability, but also significantly increases the implementation cost, hindering practical application. .
第１図で従来の構成を説明する。半導体素子１
は、セラミツク基板または樹脂基板で構成される
回路基板２にダイボンデイングされ、半導体素子
１の電極と回路基板２の配線パターン３，３′と
は極細のワイヤー４で接続されている。またワイ
ヤー４で接続された半導体素子上は、エポキシ，
シリコーン樹脂等の保護樹脂５で覆われている。
回路基板２には複数個の半導体素子が投載される
ものである。 A conventional configuration will be explained with reference to FIG. Semiconductor element 1
is die-bonded to a circuit board 2 made of a ceramic or resin substrate, and the electrodes of the semiconductor element 1 and the wiring patterns 3, 3' of the circuit board 2 are connected by extremely thin wires 4. Also, on the semiconductor element connected by wire 4, epoxy,
It is covered with a protective resin 5 such as silicone resin.
A plurality of semiconductor elements are mounted on the circuit board 2.
一方、デイスプレイパネル１０は、例えばガラ
ス基板１１上に電極１２がITO等の材料で構成さ
れているものである。導体素子１の電極と接続さ
れている回路基板２の配線パターン３と前記デイ
スプレイパネル１０の電極とは、ポリイミドフイ
ルムをベースにしたCu箔のパターン１４を有す
るフレキシブル基板１５で接続される。フレキシ
ブル基板１５の回路基板側の接続は通常半田づけ
で実装され、反対側のデイスプレイパネルの電極
１２とは、これもまたITO膜上に半田づけ可能な
材料と被着せしめ、半田づけするものである。フ
レキシブル基板１５のかわりに、カーボン粉末を
接着剤で固めた基板も用いられるが、ELデイス
プレイの如き、高電圧、大電流を印加するものに
は著じるしく不向きである。 On the other hand, the display panel 10 has an electrode 12 made of a material such as ITO on a glass substrate 11, for example. The wiring pattern 3 of the circuit board 2 connected to the electrode of the conductor element 1 and the electrode of the display panel 10 are connected by a flexible substrate 15 having a pattern 14 of Cu foil based on polyimide film. The connection on the circuit board side of the flexible substrate 15 is usually mounted by soldering, and the electrode 12 of the display panel on the opposite side is also made by applying a solderable material on the ITO film and soldering it. be. Instead of the flexible substrate 15, a substrate made of carbon powder hardened with an adhesive can also be used, but this is extremely unsuitable for devices that apply high voltage and large current, such as EL displays.
第１図の構成では、半導体素子１の電極からデ
イスプレイパネルの電極に到達するのに、４箇所
の接続点を有するものである。すなわち、半導体
素子１の電極とワイヤー４、ワイヤー４と回路基
板２の配線パターン３、配線パターン３とフレキ
シブル基板、それにフレキシブル基板とデイスプ
レイパネルの電極の合計４箇所の接続点になる。
この事は、駆動用の半導体素子が増加するに従が
い、半導体素子の数の４倍の接続点となり、これ
ら接続点は著じるしく接続の信頼性を低下さすも
のであつた。また、半導体素子を搭載するための
回路基板やフレキシブル基板等を必要とし、実装
コストを引き上げる結果となつていた。 The configuration shown in FIG. 1 has four connection points from the electrode of the semiconductor element 1 to the electrode of the display panel. That is, there are a total of four connection points: the electrode of the semiconductor element 1 and the wire 4, the wire 4 and the wiring pattern 3 of the circuit board 2, the wiring pattern 3 and the flexible substrate, and the flexible substrate and the electrode of the display panel.
As the number of driving semiconductor elements increases, the number of connection points becomes four times the number of semiconductor elements, and these connection points significantly reduce the reliability of the connection. Moreover, a circuit board, a flexible board, etc. are required for mounting the semiconductor element, resulting in an increase in mounting costs.
発明の目的
本発明はこのような従来の問題に鑑み、デイス
プレイパネルと半導体素子の接続をより信頼性高
い方法で形成することを目的とする。OBJECTS OF THE INVENTION In view of these conventional problems, an object of the present invention is to form a connection between a display panel and a semiconductor element using a more reliable method.
発明の構成
本発明は、リードを有する樹脂フイルム上に半
導体素子を値接搭載し、リードの他端をデイスプ
レイパネルの電極に接合する構成によつて、接続
点が著じるしく少なく、実装コストの安価な実装
体を実現可能とするものである。Structure of the Invention The present invention has a structure in which semiconductor elements are mounted on a resin film having leads, and the other ends of the leads are bonded to electrodes of a display panel, thereby significantly reducing the number of connection points and reducing mounting costs. This makes it possible to realize an inexpensive mounting body.
実施例の説明
第２図で本発明の実装体の実施例を説明する。
基板１９はポリイミドまたはガラス入りエポキシ
樹脂フイルム２０にSnメツキ処理したCu箔パタ
ーン２１，２１′が貼付され、半導体素子１を接
続する領域において開孔部２２が形成されてい
る。開孔部２２はCu箔による配線パターンのリ
ード２１，２１′が突出された延在され、リード
２１の一端は、後述する半導体素子１と電極と接
合され、他端はデイスプレイパネル１０の電極１
２の領域まで連続して延在するものである。（第
２図ａ）。DESCRIPTION OF EMBODIMENTS An embodiment of the mounting body of the present invention will be described with reference to FIG.
The substrate 19 has Sn-plated Cu foil patterns 21 and 21' attached to a polyimide or glass-filled epoxy resin film 20, and an opening 22 is formed in the region where the semiconductor element 1 is connected. Leads 21 and 21' of a wiring pattern made of Cu foil are extended from the opening 22, and one end of the lead 21 is connected to a semiconductor element 1 and an electrode, which will be described later, and the other end is connected to an electrode 1 of a display panel 10.
It extends continuously to the second area. (Figure 2a).
半導体素子１の電極には、例えば高さ10〜
30μmのAuによる突起１５が形成されており、こ
の突起とフイルム２０の開孔部２２に突出したリ
ード２１，２１′とAu，Snの合金で接合されて
いる。また半導体素子１の表面には開孔部２２を
通して保護樹脂２３が滴下され、半導体素子の信
頼性をより一層高めるものである。デイスプレイ
パネル１０の電極１２と半導体素子１に接合され
延在したリード２１との接続は、第２図ｂに示す
様に、電極１２とリード２１との間に有機接着材
料２４を介在させ、圧接せしめ、硬化し、固定す
るものである。有機接着材料２４は、電極１２側
もしくはフイルム２０を含めたリード側２１、も
しくは両方の側にあらかじめ塗布、貼付してお
き、電極１２とリード２１とを圧接して硬化せし
めても良い。硬化は熱硬化でも良いが、光硬化に
より瞬時に紫外線または遠紫外線を照射して硬化
せしめるものである。有機接着材料２４として導
電性粒子やせんいを分散させたものを用いること
もできる。 For example, the electrode of the semiconductor element 1 has a height of 10 to
A protrusion 15 made of Au with a thickness of 30 μm is formed, and this protrusion is joined to leads 21 and 21' protruding into the opening 22 of the film 20 by an alloy of Au and Sn. Further, a protective resin 23 is dripped onto the surface of the semiconductor element 1 through the opening 22, thereby further increasing the reliability of the semiconductor element. The connection between the electrode 12 of the display panel 10 and the extended lead 21 bonded to the semiconductor element 1 is made by interposing an organic adhesive material 24 between the electrode 12 and the lead 21, as shown in FIG. It tightens, hardens, and fixes. The organic adhesive material 24 may be applied and attached in advance to the electrode 12 side, the lead side 21 including the film 20, or both sides, and the electrode 12 and the lead 21 may be pressed together and cured. Curing may be done by heat curing, but photocuring involves instantaneous irradiation with ultraviolet rays or deep ultraviolet rays. As the organic adhesive material 24, a material in which conductive particles or fibers are dispersed can also be used.
また、他の方法を述べれば、第２図c′の如く電
極１２とフイルム２０のリード２１とをお互いに
位置合せし、圧接せしめ、光硬化性樹脂２５でフ
イルム２０と電極１２の接合領域を覆い、しかる
のち光を照射２６し硬化させることもできる。こ
の構成は著じるしく簡便で、実装コストも安価に
なる。 Another method is to align the electrode 12 and the lead 21 of the film 20 with each other as shown in FIG. It can also be covered and then irradiated with light 26 to be cured. This configuration is extremely simple and inexpensive to implement.
第２図ｄの構成は、デイスプレイパネル１０の
電極１２と半導体素子１の電極に接合され、延在
したリード２１とを互いに圧接するのではなく、
電極１２の電極ピツチもしくはリード２１のピツ
チと同ピツチあるいはこのピツチよりも更に狭い
ピツチで構成した導電体のストライプ２８を有す
るフレキシブル基板である。フレキシブル基板
は、数100〜数10μmの厚さのフレキシブルな、フ
イルム基体２７に導電体のストライプ２８を形成
したものである。 The configuration shown in FIG. 2d does not press the electrodes 12 of the display panel 10 and the extended leads 21 connected to the electrodes of the semiconductor element 1 to each other.
It is a flexible substrate having conductor stripes 28 having the same pitch as the electrode pitch of the electrodes 12 or the pitch of the leads 21 or narrower than this pitch. The flexible substrate has conductive stripes 28 formed on a flexible film base 27 with a thickness of several hundred to several tens of micrometers.
図に示すように、フイルム基体２７に形成した
導電体のストライプ２８はフイルム２０上のリー
ド群２１とデイスプレイパネルの電極１２に圧接
される。フイルム基体２７に接着性を有する有機
材料を塗布または貼付しておけば、フイルム基体
２７を圧接するのみで完全な接合が得られるもの
である。この構成にあつては、フイルム基体２７
が可撓性を有しているので、温度変動によりフイ
ルム２０が膨張したりそりが発生しても、この歪
に対して追従しやすい。したがつて、温度変化に
より、接合の信頼性が劣化することがないもので
ある。 As shown in the figure, the conductor stripes 28 formed on the film base 27 are pressed against the lead group 21 on the film 20 and the electrode 12 of the display panel. If an organic material having adhesive properties is coated or pasted on the film base 27, complete bonding can be obtained simply by pressing the film base 27 together. In this configuration, the film base 27
Since the film 20 has flexibility, even if the film 20 expands or warps due to temperature fluctuations, it can easily follow this distortion. Therefore, the reliability of the bonding does not deteriorate due to temperature changes.
次に第３図で本発明の実装体の製造方法のひと
つの実施例を説明する。例えば、ポリイミドまた
はガラス入りエポキシフイルム２０は数10ｍの長
尺で巾35mmを有し、巾の両端にフイルム２０の搬
送用のスプロケツト孔を形成し、半導体素子１を
接合する領域には、少なくとも前記半導体素子１
より大き目の開孔部２２が設けられ、この開孔部
にはSnメツキ処理したCu箔のリード２１，２
１′が形成されているものである。 Next, one embodiment of the method for manufacturing a package according to the present invention will be described with reference to FIG. For example, the polyimide or glass-filled epoxy film 20 has a length of several tens of meters and a width of 35 mm, and sprocket holes for transporting the film 20 are formed at both ends of the width, and at least the above Semiconductor element 1
A larger opening 22 is provided, and the Sn-plated Cu foil leads 21 and 2 are provided in this opening.
1' is formed.
一方半導体素子１には既に説明したようにAu，
Cu，Ag，半田等による突起１５があらかじめ形
成されている。フイルム２０のリード群２１，２
１′と半導体素子１の突起１５とを位置合せし、
ボンデイングツール４０で加熱加圧せしめる（第
３図ａの左）。ボンデイングツール４０での加熱
加圧により半導体素子１はリード群２１，２１′
に接合される（第３図ａ）。第３図ａの状態で電
気的測定を行ない、打抜き金型４１で所定の寸法
にフイルム２０を切断するｂ。打抜き金型４１を
下降４２せしめれば、フイルム２０は半導体素子
１を含めて第３図ｃの状態に切断されるものであ
る。 On the other hand, as already explained, the semiconductor element 1 includes Au,
Protrusions 15 made of Cu, Ag, solder, etc. are formed in advance. Lead groups 21 and 2 of film 20
1' and the protrusion 15 of the semiconductor element 1,
Heat and pressure is applied using a bonding tool 40 (left in FIG. 3a). The semiconductor element 1 is bonded to the lead groups 21, 21' by heating and pressing with the bonding tool 40.
(Fig. 3a). Electrical measurements are performed in the state shown in FIG. 3a, and the film 20 is cut into predetermined dimensions using a punching die 41b. When the punching die 41 is lowered 42, the film 20 including the semiconductor element 1 is cut into the state shown in FIG. 3c.
次いでデイスプレイパネル１０の電極１２とフ
イルム２０のリード群２１とを位置合せし、ツー
ル４３で圧接せしめ（第３図ｄ）、光硬化性を有
する樹脂２５を滴下し、光照射２６すれば第３図
ｅの如くの実装体を製造することができるもので
ある。 Next, the electrodes 12 of the display panel 10 and the lead group 21 of the film 20 are aligned and pressed together using a tool 43 (FIG. 3d), a photocuring resin 25 is dropped, and light is irradiated 26 to form the third It is possible to manufacture a package as shown in Figure e.
また、ツール４３で圧接する前に前記光硬化性
を有する樹脂をリード群かもしくはデイスプレイ
パネル１０の電極１２に塗布あるいは貼付してお
き、ツール４３で圧接しながら、光照射を行なう
こともできる。さらに、前記リード群とデイスプ
レイパネル１０の電極１２の重なり部分近傍にお
いて、前記リード群と電極１２の露出部分の一部
を第２図ｃの如く覆う２５′ことにより、前記重
なり部分の信頼性を著じるしく向上できるもので
ある。 It is also possible to apply or adhere the photocurable resin to the lead group or the electrodes 12 of the display panel 10 before pressing with the tool 43, and then irradiate with light while pressing with the tool 43. Further, in the vicinity of the overlapping portion of the lead group and the electrodes 12 of the display panel 10, a part of the exposed portion of the lead group and the electrode 12 is covered 25' as shown in FIG. 2c, thereby increasing the reliability of the overlapping portion. This can be significantly improved.
発明の効果
(1) 同一フイルム上に形成した同一リード群同志
でデイスプレイパネルの電極と半導体素子の電
極との接合を行なうので、実装体の構成材料が
フイルムのみで著じるしく少ないので実装コス
トを安価にできる。Effects of the invention (1) Since the electrodes of the display panel and the electrodes of the semiconductor element are bonded to each other using the same lead group formed on the same film, the mounting cost is reduced because the material used to construct the mounting body is only the film, which is significantly reduced. can be done inexpensively.
(2) 接続の箇所が第２図ａ，ｂ，ｃの構造で２箇
所，ｄの構造で３箇所と著じるしく少ないので
接続の信頼性が著じるしく高い。(2) The reliability of the connection is extremely high because the number of connection points is extremely small: 2 in the structures shown in Figure 2 a, b, and c, and 3 in the structure d.
(3) すでにのべたように接続箇所が少ないので、
従来必要としていた接続のための領域（面積）
が不必要となるから実装面積が小さくなり、小
型化、薄型化の商品的価値を高めることができ
る。(3) As already mentioned, there are few connection points, so
Area (area) for connections that were previously required
Since this becomes unnecessary, the mounting area becomes smaller, and the commercial value of miniaturization and thinning can be increased.
(4) 長尺のフイルムに半導体素子を接合し、これ
を連続して所定の寸法に打抜き、デイスプレイ
パネルの電極に接合するのみであるから、生産
設備の投資が著じるしく少なく、実装コストが
安価になる効果を有する。(4) Since semiconductor elements are simply bonded to a long film, continuously punched out to the specified dimensions, and bonded to the electrodes of the display panel, investment in production equipment is significantly reduced, and mounting costs are reduced. This has the effect of making it cheaper.
第１図は従来の実装体の構成断面図、第２図ａ
〜ｄは本発明の一実施例の実装体の製造工程断面
図、第３図ａ〜ｅは本発明の他の実施例の実装体
の製造方法を示す工程断面図である。
１……半導体素子、１０……デイスプレイパネ
ル、１２……デイスプレイパネルの電極、１５…
…突起、２０……フイルム、２１，２１′……リ
ード群。
Figure 1 is a cross-sectional view of the structure of a conventional mounting body, Figure 2 a
3 to 3d are cross-sectional views showing the manufacturing process of a package according to an embodiment of the present invention, and FIGS. 3A to 3E are process cross-sectional views showing a method of manufacturing a package according to another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 10... Display panel, 12... Display panel electrode, 15...
...protrusion, 20...film, 21, 21'...lead group.
Claims (1)
の一方が半導体素子の電極パツドに接合され、延
在した前記リード群の他方が絶縁基板上に形成さ
れた相対する電極群と接触し、前記リード群と電
極群とが少なくとも光硬化を有する樹脂により固
定されるとともに、前記他方のリード群と絶縁基
板上に電極群の重なり部分の近傍において、前記
リード群および電極群の一部を前記光硬化を有す
る樹脂が覆つていることを特徴とする実装体。1. One of the lead groups formed on the flexible resin film is joined to the electrode pad of the semiconductor element, and the other extended lead group is in contact with the opposing electrode group formed on the insulating substrate. The lead group and the electrode group are fixed by at least a light-curable resin, and a part of the lead group and the electrode group is exposed to the light in the vicinity of the overlapping portion of the other lead group and the electrode group on the insulating substrate. A mounting body characterized by being covered with a hardening resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59118460A JPS60262436A (en) | 1984-06-08 | 1984-06-08 | Packaged body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59118460A JPS60262436A (en) | 1984-06-08 | 1984-06-08 | Packaged body |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60262436A JPS60262436A (en) | 1985-12-25 |
| JPH0330988B2 true JPH0330988B2 (en) | 1991-05-01 |
Family
ID=14737198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59118460A Granted JPS60262436A (en) | 1984-06-08 | 1984-06-08 | Packaged body |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60262436A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63151031A (en) * | 1986-12-16 | 1988-06-23 | Matsushita Electric Ind Co Ltd | Connection of semiconductor device |
-
1984
- 1984-06-08 JP JP59118460A patent/JPS60262436A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60262436A (en) | 1985-12-25 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |