JPH033037A - Microprogram control system - Google Patents

Abstract

PURPOSE:To shorten processing time without increasing the number of hardwares by providing a system with a registering means for storing a microinstruction and controlling the updating, storage and generation of the microinstruction stored in the register means to execute a microprogram. CONSTITUTION:The system is constituted of a microprogram control part 8 provided with a microprogram storing area 1 storing microinstructions, a microsequence control mechanism 2 for reading out the microinstructions in the previously set order and a register 3 for storing the read microinstructions and a controlled part 7 provided with D latches 4 to 6. The microprogram is executed by controlling the register 3 storing the contents of microinstructions mu4 to mu6 and the microinstructions mu4 to mu6 stored in the register 3 by microinstructions mu2, mu3. Consequently, the overhead or the like of processing time following the call branch and restoration of a subsequence in a microflow is reduced and rapid microprogram control can be attained by the compact constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to microprogram control systems. More specifically, regarding digital logic circuit control methods, micro instructions, which are coded information corresponding to so-called micro operations, are used as a means to realize combinational and sequential logic circuits. The present invention relates to the configuration of a microprogram control system that defines circuit operations based on a microprogram, which is a sequence of microinstructions stored in a storage device in advance and read out according to a processing procedure.

Conventional microprogram control methods break down a series of operations associated with data processing, so-called macro operations, into micro operations that are more detailed, and define micro instructions, which are information codes that specify these micro operations. By arranging and executing these microinstructions in accordance with the order of processing, it is a means of specifying large operations such as processing that requires steps.

Here, it is desirable that the defined microinstructions have commonality in the sense of realizing various processes, and are formalized so that combinations and orders can be flexible.

Therefore, microinstructions not only define basic unit operations, but also generally include those that define the order of the microinstructions themselves.

On the other hand, in order to realize various macro operations using the same microprogram control mechanism, the macro operation to be executed must be drawn into a microprogram sequence that defines the macro operation, that is, a micro sequence.

This means that in boat fishing, a specified microprogram storage area is specified to implement the corresponding macro operation, the first address of the so-called microprogram storage device (hereinafter referred to as en).
This is done by giving the IJ address. and,
The subsequent order is configured to be controlled by the microprogram itself, and processing is executed according to the microsequence.

The above microsequence order control methods include the microprogram counter method, in which a branch destination address is specified only when a branch occurs, and the address of the next microinstruction is normally indicated sequentially by a counter, and the microprogram counter method, as shown in Figure 5. Among these instructions, there is a netast address method in which the address of the next instruction is always included. However, because microinstructions are often not made available to the general public and formalization is not a concern due to emphasis on performance, the netast address method, which increases the control bit width but does not generate idle periods associated with branches, is an invention. In the microprogram control method described above, from the perspective of processing performance, it is required to reduce the overhead associated with branching as much as possible for efficiency, and from the perspective of scale, it is necessary to reduce the overhead associated with branching as much as possible. There is a demand to share as much as possible, even as much as possible. Flora sharing is similar to subroutine call branching in general programming methods, but when an operation corresponding to call branching or returning from a subroutine to the original sequence (hereinafter referred to as return) is inserted into a microsequence, the overhead is Therefore, the processing sequence appears long.

In other words, it is difficult to achieve both performance and scale.

When considering shortening the time required to generate and process the entry address and standardizing the flora, if processing that requires particularly high speed is realized using a microprogram method, it will be easier to process or separate the entry address. I don't have much time to do it. Therefore, methods have been adopted to hide the overhead through pre-decoding, pipeline processing, etc. until the type of flora is assigned. The reason for this will be explained with reference to FIG.

FIG. 6 shows a conceptual diagram of the microprogram flora. As shown in FIG. 6, the boat fishing flow is made up of sequences unique to each macro process and parts common to several flora. Now, for n types of macro processing, n
Given a unique entry address for a type,
There are also flora groups such as M+, M2, and M3 that enter common processing from the first sequence. The first step of this flora group is simply a call branch to the first address SI of these common sequences (referred to as subsequences). This becomes an obstacle to shortening the time required to generate and process the entry address described above.

Furthermore, when using the above-mentioned next address method, branching to Sl is ! It is sufficient to simply write S in the netast address control section of vL, M2, and M3, but R1 and
Since information for returning to R2 and R1 (referred to as return) must be saved, an additional area indicating return information is required in the microprogram control field. These results resulted in an increase in the amount of hardware.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a microprogram control method that solves the problems of the prior art, has a short processing time, and does not require an increase in hardware.

Means for Solving the Problems According to the present invention, in a microprogram control method in which microinstructions are read out in a predetermined order from a storage device in which the microinstructions are stored and various circuit operations are controlled based on the microprogram, the storage device microprogram order control means for defining the order in which microinstructions are read out; register means for storing the read microinstructions; and first control means for determining whether or not to update the contents of the register means and whether to retain the contents. and a second control means for controlling whether or not the microinstruction stored in the register means takes effect, and the first and second control means are controlled by the microprogram order control means. A microprogram control method is provided that is characterized by executing a microprogram.

Operation The microprogram control system of the present invention includes register means for storing microinstructions, and controls the updating, retention, activation, etc. of the microinstructions stored in the register means, thereby controlling the microprogram execution. There are main characteristics.

Furthermore, the microinstruction stored in the register may be the same information code as the microprogram order setting information, which is information other than the readout information of the microprogram storage area. According to this configuration, instead of the return destination address information R,, R2, and R3 shown in FIG. 6, M+,
It becomes possible to save control information specific to M2 and M3 in register means. By performing control to enable this content at the time of return, there is no need for an additional area or save area in the microprogram field that specifies the information for return, and there is no overhead associated with call branching or return execution. is also reduced.

Further, in the microprogram control method of the present invention, even if the above control means is realized by hardware,
It may be realized by microinstructions.

Therefore, in the conventional example shown in FIG. 6, a return instruction had to be written in Fl, but in the microprogram control method of the present invention, Fl controls the register contents, or performs simple hardware control. The process ends with just that.

EXAMPLES Hereinafter, the present invention will be explained in more detail with reference to Examples, but the following disclosure is merely an example of the present invention and does not limit the technical scope of the present invention in any way.

Embodiment 1 FIG. 1 shows a logical block diagram of a device implementing an embodiment of the microprogram control system of the present invention, and FIG. 2 shows a timing diagram showing operation timing. The device shown in FIG. 1 is composed of a storage device and the like, and includes a microprogram storage area l that stores microinstructions, a microsequence control mechanism 2 that controls the microinstructions to be read out in a preset order, and a readout area L that stores microinstructions. The microprogram control section 8 includes a microprogram control section 8 that includes a register 3 for holding microinstructions, and a controlled section 7 that includes D latches 4 to 6.

In this embodiment, M1, M2, and M3 are defined as follows.

M1 → AAB M2 → AA””E M3→-7'rAB However, A is C or D, but M1 to M.

It is commonly C. Also, B is E or Av
E, but in Ml ""-M3, AvE
It is.

Also, the microinstruction μ. ~μ6 is defined as follows.

μ. A logical value of “0” selects D, and a logical value of “1” selects C.

Logic value “0” is E, “1” is AVE Select.

Activate register contents.

μ2 μ μ3 Load the μ4 to μ6 codes into the register.

μ, ~ μ6 gate control.

As mentioned above, in the processing related to A and A specified by M1 to M3, B, which is a function of A and A, is common. Also, μ. ~Define the microfield of μ6,
The functions are realized by the microprogram control section 8 and the controlled section 7.

The operation of the above device will be explained below with reference to FIG. The code that defines the macro operation is sent to the synchronization signal CI as the entry address of the microprogram storage area 1.
Entries are made in synchronization with Entry address M1
The contents of the program described in μ. ~μ6 and NA are
The next synchronization signal C2 is output from the microprogram storage area 1.

At this time, in the first step, the next address NAI common to M+-M3 and the control information μ6 specific to M1 processing are
is valid. μ6 cannot be used unless A and B are generated, and since the procedure for generating A and B is common to M1 to M, it is programmed in the sequence following NAI. At the same time, the register fetch control signal .mu. is activated, and the contents of the control information .mu.4 to .mu.6 are saved in the register 3.

Subsequently, the microsequence control mechanism 2 switches the N
Netast address information NA2 and μ which are the contents of the microprogram storage storage device 1 addressed by AI.

will take effect at the next C2. Next, the netast address information N^3 and μm addressed by NA2 are activated and A and B are generated.

Finally, μ2 written in NA3 is activated and the output of register 3 is activated. Here, since the contents of the first step .mu.4 to .mu.s have been saved in the register 3, the operation specified by Ml is executed with the logic value "100". In this step, it is possible to specify N^ for the next macro entry.

That is, in this embodiment, the microprogram control method of the present invention is implemented by controlling the register 3 that holds the contents of microinstructions μ4 to μ6 and the microinstructions held in register 3 using microinstructions μ2 and μ. has been realized.

Embodiment 2 FIG. 3 shows a logical block diagram of an apparatus implementing a second embodiment of the present invention, and FIG. 4 shows a timing diagram showing its operation timing. The device shown in FIG. 3 is composed of a storage device and the like, and includes a microprogram storage area 10 that stores microinstructions, and a microsequence control mechanism 2 that controls the microinstructions to be read out in a preset order.
The microprogram control section 50 includes a microprogram control section 50 having a register 30 for holding 0 and read microinstructions, and a controlled section 40. The controlled section 40 is exactly the same as the controlled section 7 of the first embodiment. In this embodiment, M, -M, and Ml, which are information codes that define macro operations and indicate entry addresses of microprograms, are set to logical values "too,""010," and "001," respectively. This code can be distinguished from other codes, and since the microflora can be stored at any position in the microprogram storage area 10, a unique code can be arbitrarily assigned.

Also, the microinstruction μ. ~μ2 is defined as follows.

μ. Logic value “0” and Dl “1” select C.

μm Logic value “0” and El “1” selects AV'E.

μ2 Update the contents of the register with logical value “0” and “1”
” to hold.

Activate the contents of the μm register.

μ0 and μm are completely the same as those in the first embodiment, and μ2 is a control signal that prevents updating of the register 30. Also,
Although μm is not shown, it is equal to μ2 in Example 1.

The operation of the above device will be explained with reference to FIG. The code that defines the macro operation is entered as an entry address in the microprogram storage area 10 in accordance with the synchronization signal CI. Content μ of the program written in entry address M1.

~μ2 and N^ are output from the microprogram storage area 10 with the next synchronization signal C2, but in this embodiment, the next address NAI and μ. , μ2, which prevents register contents from being updated, is effective. Furthermore, in this embodiment, MI-M,
, the first step of this micro-throw is quite common. In other words, “
The same content is written at addresses 100, 010, and 001.

In the initial state, μ2 is normally "0" at the same time as input according to the synchronizing signal C1, and the register 30 is in an updatable state. Therefore, the register 30 contains a logic "10" which is the macro information code and the entry address itself.
0" is fetched. Subsequently, the microsequence control mechanism 20 switches the netast address information NA2 and μm, which are the contents of the microprogram storage area IO addressed by NAI, into effect at the next 02, and A,
B is being generated.

During this time, since μ2 prohibits updating the contents of the register 30, "100" is saved in the register 30. Therefore, for the controlled unit 40, μ6~ of the first embodiment is
This means that a control signal corresponding to μ is given, and at the end of the process, the register is released in preparation for the next process at μm, which was written in NA2. In this embodiment, this last step is also common to the processing flora of M1 to M3.

That is, in this embodiment, the microprogram control system of the present invention is realized by holding the entry address itself, which is a macro information code, in the register 30 and controlling it with micro instructions μ2 and μ3.

Effects of the Invention As explained above, the microprogram control method of the present invention reduces processing time overhead required for branching and saving address information associated with call branching and return to micro-throw subsequences, and reduces hardware costs. It is extremely effective in reducing additional assets and realizing high-speed microprogram control with a small-scale configuration.

[Brief explanation of drawings]

1 is a logical block diagram of a device that implements one embodiment of the microprogram control method of the present invention; FIG. 2 is a timing diagram showing the operation timing of the device of FIG. 1; 5 is a logical block diagram of a device that implements the second embodiment of the present invention, FIG. 4 is a timing diagram showing the operation timing of the device of FIG. 3, and FIG. 5 is a diagram of a conventional micro FIG. 6 is a block diagram showing a program control mechanism, and FIG. 6 is a conceptual diagram showing a micro sequence. [Main reference number] 110...Microprogram storage area, 2.20.
...Micro sequence control mechanism, 3.30...Register, 4-6...D latch, 7.40...Controlled section,

Claims (5)

[Claims] (1) In a microprogram control method in which microinstructions are read out in a predetermined order from a storage means in which the microinstructions are stored and various circuit operations are controlled based on the microprogram, the reading order of the microinstructions in the storage means is defined. microprogram order control means for storing read microinstructions; first control means for determining whether or not to update the contents of the register means and whether to retain the contents; and register means for storing the read microinstructions; It is characterized by comprising a second control means for controlling whether or not an instruction is to take effect, and executing the microprogram by controlling the first and second control means by the microprogram order control means. Microprogram control method. (2) The microprogram control method according to claim 1, wherein the microinstruction stored in the register means is information other than read information of the storage means. (3) It comprises means for modifying information regarding the microprogram order control and means for setting fixed address information, and the microinstruction stored in the register means has the same information code as the microprogram order setting information. The microprogram control system according to claim 2, characterized in that: (4) Claims (1) to (3) characterized in that the first and second control means are realized by hardware.
) The microprogram control method according to any one of the above. (5) Claims (1) to (3) characterized in that the first and second control means are realized by microinstructions.
) The microprogram control method according to any one of the above.