JPH0330361A - Semiconductor device - Google Patents

Abstract

PURPOSE:To incorporate a semiconductor device properly into a package without deformation even thorugh heating while holding a bonding surface in constant height by forming the plated-heat sink(PHS) of the rear of the single chip of a via hole type high-output GaAs field-effect transistor in a pectinate shape. CONSTITUTION:A single chip 1 is fixed and incorporated into a package 4 by solder 3, but the single chip 1 and a PHS 5 are heated up to approximately the melting point of solder 3 together with the package 4 is that time. The single chip 1, the PHS 5 and the package 4 are expanded through the heating, but the PHS 5 is formed in a pectinate shape even when each thermal expansion coefficient differs, thus absorbing stress due to the difference of thermal expansion by stress-absorbing opening sections 6. The single chip 1 is fixed into the package 4 through solder 3 without bending. Accordingly, the height of a bonding surface is held uniformly.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a via-hole type high-power GaAs ft field effect transistor (hereinafter referred to as VH-H/P FET).
This relates to the plated heat sink (hereinafter referred to as PH8) structure on the back surface.

[Conventional technology]

Figure 3 is a plan view showing the PH3 structure on the back side of the chip of the conventional V)i,)i/P FET, and Figure 4 is the ■ and H in Figure 3.
FIG. 3 is a cross-sectional view showing a state in which a /P FET chip is assembled into a package.

In the figure, (1) is a single chip of VH-H/P FET, and the single chip (1) has PH3 on the back side of the GaAs substrate.
(2) is integrally formed into a plate shape. In addition, in order to lower the source resistance and thermal resistance of the single chip (1), the thickness is approximately 50 to 60 μm, and approximately 1
/2 thickness by plating, plate-shaped PHS (2)
is formed. (3) is solder, and the PHS (2) formed on the back side of the single chip (1) is fixed to the package (4) via this solder (3), and the chip (1) is attached to the package (4). incorporated within.

Next, the operation will be explained. When the single chip (1) is assembled into the package (4), the single chip (1) and the PH
The chip (1) and PH3 (2) are heated together with the package (4) to the temperature of the solder (3), and the chip (1) and PH3 (2) thermally expand.
(2) is cooled together with solder (3) and package (4). Once cooled, solder (3) sticks to P)[5 (2) and package (4), forming a single chip. (1) is fixed to the package (4).

[Problem to be solved by the invention]

Since conventional semiconductor devices were configured as described above,
When a single chip is assembled into a package, the single chip and PH8 are heated together with the package to a high temperature close to the melting point of solder.
Since there is a difference in the coefficient of thermal expansion from H5, a single chip cooled and fixed in the package is bent by stress due to thermal expansion, as shown in Figure 4, and the height of the bonding surface is deformed, causing Vl (-H/P There was a problem that the performance and assemblability of FE1' were degraded.

This invention was made to solve the above-mentioned problems, and it is possible to properly incorporate a V)iH/)' FET into a package without deforming it even when heated, and to keep the bonding surface constant. The purpose is to obtain a semiconductor device that can be held at a height of .

[Means to solve the problem]

In the semiconductor device according to the present invention, in a single chip of VH, It is constructed by joining it to the back side.

[Effect]

In this invention, the back surface of the single-chip GaAs substrate of the VH, H/P FET is bonded only with the comb-shaped PH5 teeth, and these peaks allow the GaAs substrate to
Since the As substrate and PH3 are bonded at regular intervals, even if the chip is heated to a high temperature, the stress due to the difference in thermal expansion coefficients is absorbed, and deformation of a single chip is suppressed.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings. 1(a) and 1(b) are a plan view and a sectional view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the semiconductor device of FIG. 1 incorporated into a package. It is a diagram.

In the drawings, reference numerals (1, 3) and (4) indicate the same or corresponding parts as in the conventional one, and the explanation thereof will be omitted.

(5) is a comb-shaped PH formed on the back side of the single chip (1) of VH・)i/PFET. H51 (sa) is the toothed part of the comb-shaped PI-1s (5). GaA of
It is bonded to the back surface of the s-substrate. (6) is VH-H/P
FET single chip GaAs substrate and comb-like PHS
This is a stress absorbing gateway formed by joining the teeth (5a) of (5).

The P )i S (5) configured as above forms the back side of the single chip (1), and the solder (3)
(5) and the package (4) are firmly attached.

Next, the operation will be explained.

A single chip (1) is soldered (3) as shown in Figure 2.
The single chip (1) and the PHS (5) are fixedly assembled into the package (4) in the package (4).
) to about the melting point of solder (3). This heating results in a single chip (1), P )i S (5)
and the package (4) expand, but even if there is a difference in their expansion coefficients, the PH5 (5) has a comb-like structure, so the stress due to the difference in thermal expansion is absorbed by the stress absorbing opening (6). Absorbed. Then, the single chip (1) is soldered (3) in the package (4) without bending.
), and the height of the bonding surface is maintained uniformly.

Note that the shape of the teeth (5a) of the comb-like PHS (5) is such that the GaA of the single chip (1) has a good heat diffusion efficiency.
It is desirable to have a shape that extends in the left and right directions at 45 degrees from the back surface of the s-substrate.

〔Effect of the invention〕

As described above, according to the present invention, VH-)1/PFET
By forming the PH5 on the back surface of a single chip in a comb-like shape, the chip incorporated in the package is prevented from being deformed due to thermal expansion, which has the effect of contributing to improving the performance and assemblability of the semiconductor device.

[Brief explanation of drawings]

1(a) and 1(b) are a plan view and a sectional view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view showing a state in which the semiconductor device of FIG. 3 is a plan view showing a conventional semiconductor device, and FIG. 4 is a sectional view showing a state in which the semiconductor device of FIG. 3 is incorporated. In the figure, (1) is a single chip, (3) is solder, (4
) indicates the package, (5-inch comb-tooth plated heat sink, (5a) the teeth of the comb-tooth plated heat sink, and (6) the stress absorption opening. In the figures, the same symbols are Indicates the same or equivalent part. Agent Masuo Oiwa Figure 1 Ishitoto PH5 Figure 2 J3 Field 4 H1 Tsukeban

Claims (1)

[Claims] In a single chip of a via-hole type high-power GaAs field effect transistor, a plated heat sink structure on the back surface of the single chip is configured in a comb-like shape, and the comb-like teeth are formed on the GaAs field effect transistor of the single chip. A semiconductor device characterized by being configured by being bonded to the back surface of a substrate.