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JPH0329348A - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPH0329348A
JPH0329348A JP16294889A JP16294889A JPH0329348A JP H0329348 A JPH0329348 A JP H0329348A JP 16294889 A JP16294889 A JP 16294889A JP 16294889 A JP16294889 A JP 16294889A JP H0329348 A JPH0329348 A JP H0329348A
Authority
JP
Japan
Prior art keywords
semiconductor element
film
brazed
base plate
stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16294889A
Other languages
Japanese (ja)
Other versions
JP2604470B2 (en
Inventor
Yasumasa Saito
斉藤 安正
Kazuo Matsuzaki
松崎 一夫
Akira Amano
彰 天野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TOTTORI DENKI SEIZO KK
Fuji Electric Co Ltd
Original Assignee
TOTTORI DENKI SEIZO KK
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TOTTORI DENKI SEIZO KK, Fuji Electric Co Ltd filed Critical TOTTORI DENKI SEIZO KK
Priority to JP1162948A priority Critical patent/JP2604470B2/en
Publication of JPH0329348A publication Critical patent/JPH0329348A/en
Application granted granted Critical
Publication of JP2604470B2 publication Critical patent/JP2604470B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Die Bonding (AREA)

Abstract

PURPOSE:To obtain an intermediate layer which is insulated electrically but which can conduct heat by a method wherein individual films laminated on a base plate are formed in a state that functions of electrical insulation between a semiconductor element and its base, of relaxation of stress, and of formation of a brazable face. CONSTITUTION:At least an insulating film 2 and a film 6 capable of being brazed well via stress-relaxing metal films 4, 5 are laminated on a container metal base plate 1; a semiconductor element 11 is brazed on the film 6 capable of being brazed well. That is to say, to films 4 to 6 which are provided individually with individual functions to insulate the semiconductor element 11 and the base plate 1, to absorb a thermal stress and an external stress due to a difference in a coefficient of thermal expansion between the semiconductor element 11 and the base plate 1 and to form a face capable of being brazed of the semiconductor element 11 are laminated between the semiconductor element 11 and the container metal base plate 1. Thereby, a thin intermediate layer which guarantees a good heat-conductive property can be formed; the degree of freedom to select a material is made high; the cost can be low.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体素体が容器の放熱板を兼ねた金属底板
上に絶縁して固定される半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device in which a semiconductor element is insulated and fixed onto a metal bottom plate that also serves as a heat sink of a container.

(従来の技術〕 半導体素体を容器に収容し、電極への接続導体を容器か
ら引き出す場合も、半導体素体を支持する底板は放熱体
を兼ねる必要があるため、金属により形成する必要があ
る.この底仮と半導体素体とは電気的に絶縁されねばな
らないので、半導体素体と底板の間に絶縁板が挿入され
る.この絶縁板は半導体素体からの放熱のために高絶縁
性であると共に良熱伝導性を有することが要求される.
そのような材料として酸化ベリリウムなどの良熱伝導性
セラミックが用いられる.さらにこのセラミック板は、
半導体素体および底仮とのろう付けのため、両面に熱圧
着で銅などがメタライズされる. 〔発明が解決しようとする課題〕 上記のような従来の半導体装置を製造・するには、先ず
セラミック板のメタライズ面に半導体素体をろう付けし
、次にこれを底仮にろう付けする.この場合、双方のろ
う付けに用いるろう材、例えばはんだは融点が異なる必
要があり、作業が複雑になる.また、上述のように高絶
縁性,良熱伝導性の双方を有するセラミンクは高価であ
り、その上メタライズ加工をしなければならないのでコ
スト高になる問題がある. 本発明の目的は、上述の問題を解決し、放熱板を兼ねる
金属底板上に電気的には絶縁されるが熱伝導可能なよう
に半導体素体が支持され、かつコストの低い半導体装置
を提供することにある.〔謀題を解決するための手段〕 上記の目的を達威するために、本発明の半導体装置は、
容器の金属底板上に少なくとも絶縁性膜,応力緩和金属
膜を介して良ろう付性被膜が積層され、この良ろう付性
被膜上に半導体素体がろう付けされたものとする. 〔作用〕 放熱板を兼ねる容器底坂上に積層される各膜が、半導体
素体と底板との間の電気絶縁,応力緩和ならびに半導体
素体のろう付可能面の形或の各機能を全体として良熱伝
導性を保持した状態で形威する.各膜の材料は独立して
選択できるので選択の範囲が広い. 〔実施例〕 第1図,第2図は本発明の一実施例を示す.この半導体
装置は、トランジスタチップ11を容器内に収容したも
のである.容器はCuあるいはMからなる底板1を有し
、底Fil上にはSiO,Si(h.siJ4,アモル
ファスSiあるいは多結晶シリコン等の中から選ばれる
絶縁膜2を化学あるいは物理気相戒長法.スバンタ法等
により被覆する.例えばチソプ1lと底板1の間に4k
Vの絶縁耐量が必要なときには5Itmの厚さのSiJ
a膜を設ける.絶縁性から考えれば厚い方が望ましいが
、熱伝導性の点からは薄い方が望ましい.この絶!!膜
2の上に絶縁膜と上層膜との接着のため、双方に密着性
の良いバインダ膜3をスパンタ法あるいは蒸着法などに
より積層する。バインダ膜3はCr,Ti などの薄膜
からなる.この上に、半導体チフブ11と底板1との熱
膨張係数の差に基づく熱応力あるいは機械的応力の緩和
のための応力緩和膜を設ける。この場合の応力緩和膜は
、C u + P d + A u等の比較的柔らかい
材料からなる応力吸収膜4をスパッタ法,蒸着法,めっ
き法あるいはコーティング法等により形成し、その上に
半導体と熱膨張係数の近いMo, W等からなる低熱膨
張係数膜5を化学あるいは物理的気相成長法.スパンタ
法,蒸着法などにより積層したものである.最後に、は
んだ付け可能な良ろう付性被膜6を蒸着法,スバンタ法
あるいはめっき法等によるNi等の薄膜により被覆する
.これらの多層膜2.3,4,5.6の全体の厚さは1
0fIa程度であり、絶縁膜2による絶縁性と共に良熱
伝導性を有する.なお、これらの絶&![2を除く他の
膜3.4.5.6は底坂上に全面被着後、選択エッチン
グによりチップ支持部,チップの各電極接続部の各N域
をパタニングする。トランジスタチップ11はチップ支
持部の良ろう付性被膜6上にはんだ等のろう7によりろ
う付けする。良ろう付性被膜6にNiを用いればはんだ
付けの場合のSnの下層への拡散を防止する効果がある
.トランジスタチソブ11の工果フタiitil2は、
工ξソタ接続部13の良ろう付性被膜6とAj線21の
ボンディングで接続し、エミッタ接続部13にはエミッ
タ引出しりー114をろう付けする.チップ11のベー
ス電極151は、ベース接続部15の良ろう付性被膜と
M線21のボンディングで接続し、ベース接続部にはベ
ース引出しり一ド16をろう付けする.チップ11の下
面のコレクタ電極は多11119最上層の良ろう付性被
IP16とろう付けされているが、多層膜のバインダl
I!3および応力吸収膜4をm縁膜2の上で延長し、コ
レクタ接続部l7との間のコレクタ取出しリード22を
形威する.コレクタ接続部17にはコレクタ引出しリー
ド18をろう付けする.第1図に概念的に図示したよう
に、容器底板1の縁部には容器上部8を接着する.〔発
明の効果〕 本発明によれば、半導体素体と放熱板を兼ねる容器金属
底板の間に半導体素体と底板間の絶縁、半導体素体と底
抜との熱膨張係数の差による熱応力および外部応力の吸
収、半導体素体のろう付可能面の形成の各a能を個々に
有する膜を積層することにより、良熱伝導性を保証する
薄い中間層として形成することができ、材料選択の自由
度が大となり、材料費,工数の節減が可能となって低コ
ストの半導体装置が得られた.
(Prior art) Even when a semiconductor element is housed in a container and a conductor connected to an electrode is drawn out from the container, the bottom plate that supports the semiconductor element needs to also serve as a heat sink, so it must be made of metal. .Since this base plate and the semiconductor body must be electrically insulated, an insulating plate is inserted between the semiconductor body and the bottom plate.This insulating plate has high insulation properties to dissipate heat from the semiconductor body. It is also required to have good thermal conductivity.
Ceramics with good thermal conductivity such as beryllium oxide are used as such materials. Furthermore, this ceramic plate
In order to braze the semiconductor body and base temporary, copper and other materials are metallized on both sides by thermocompression bonding. [Problems to be Solved by the Invention] To manufacture the conventional semiconductor device as described above, first a semiconductor element is brazed to the metallized surface of a ceramic plate, and then this is temporarily brazed to the bottom. In this case, the brazing materials used for both brazing, such as solder, must have different melting points, which complicates the work. Furthermore, as mentioned above, ceramics having both high insulation properties and good thermal conductivity are expensive, and on top of that, they have to be metallized, which increases the cost. An object of the present invention is to solve the above-mentioned problems and provide a low-cost semiconductor device in which a semiconductor body is electrically insulated but supported on a metal bottom plate that also serves as a heat sink in a manner that allows heat conduction. It's about doing. [Means for solving the problem] In order to achieve the above object, the semiconductor device of the present invention has the following features:
A film with good brazeability is laminated on the metal bottom plate of the container via at least an insulating film and a stress-relaxing metal film, and a semiconductor element is brazed onto this film with good brazeability. [Function] Each film laminated on the slope of the bottom of the container, which also serves as a heat dissipation plate, provides electrical insulation between the semiconductor element and the bottom plate, stress relaxation, and the shape and function of the brazable surface of the semiconductor element as a whole. Appears while maintaining good thermal conductivity. Since the material for each membrane can be selected independently, there is a wide range of choices. [Example] Figures 1 and 2 show an example of the present invention. This semiconductor device has a transistor chip 11 housed in a container. The container has a bottom plate 1 made of Cu or M, and an insulating film 2 selected from SiO, Si (h.siJ4, amorphous Si, polycrystalline silicon, etc.) is deposited on the bottom film by chemical or physical vapor deposition method. .Cover by Svantha method etc. For example, 4K between 1l of chisop and bottom plate 1.
When a dielectric strength of V is required, SiJ with a thickness of 5Itm is used.
a. Provide a membrane. Thicker is better from an insulation standpoint, but thinner is better from a thermal conductivity standpoint. This absolute! ! In order to bond the insulating film and the upper film onto the film 2, a binder film 3 having good adhesion to both is laminated by a spunter method or a vapor deposition method. The binder film 3 is made of a thin film of Cr, Ti, or the like. On top of this, a stress relaxation film is provided to relieve thermal stress or mechanical stress based on the difference in thermal expansion coefficients between the semiconductor chip 11 and the bottom plate 1. In this case, the stress-relaxing film is formed by forming a stress-absorbing film 4 made of a relatively soft material such as Cu + P d + Au by sputtering, vapor deposition, plating, coating, etc., and then depositing a semiconductor layer thereon. A low thermal expansion coefficient film 5 made of Mo, W, etc. having similar thermal expansion coefficients is formed by chemical or physical vapor phase growth. It is laminated using spunter method, vapor deposition method, etc. Finally, a solderable film 6 with good brazing properties is coated with a thin film of Ni or the like by vapor deposition, Svanta method, plating method, or the like. The total thickness of these multilayer films 2.3, 4, 5.6 is 1
0fIa, and has good thermal conductivity as well as insulation due to the insulating film 2. In addition, these absolute &! [After the other films 3.4.5.6 except 2 are deposited on the entire surface of the bottom slope, the N regions of the chip support part and each electrode connection part of the chip are patterned by selective etching. The transistor chip 11 is brazed onto the well-brazed coating 6 of the chip support portion using a solder 7 such as solder. The use of Ni in the good brazeability coating 6 has the effect of preventing Sn from diffusing into the lower layer during soldering. The product lid iiitil2 of the transistor Chisob 11 is
The well-brazed coating 6 of the solder joint 13 is connected to the Aj wire 21 by bonding, and the emitter drawer 114 is brazed to the emitter joint 13. The base electrode 151 of the chip 11 is connected to the well-brazed coating of the base connection part 15 by bonding with the M wire 21, and the base drawer board 16 is brazed to the base connection part. The collector electrode on the bottom surface of the chip 11 is brazed to the uppermost layer of IP16, which has good brazing properties, but the binder l of the multilayer film is
I! 3 and the stress-absorbing film 4 are extended on the edge film 2, and a collector lead 22 is formed between it and the collector connection part 17. A collector lead 18 is brazed to the collector connection part 17. As conceptually illustrated in FIG. 1, a container top 8 is glued to the edge of the container bottom plate 1. [Effects of the Invention] According to the present invention, there is insulation between the semiconductor element and the bottom plate of the container that also serves as a heat sink, and thermal stress due to the difference in thermal expansion coefficient between the semiconductor element and the bottom plate. By laminating films that individually have the functions of absorbing external stress and forming a brazable surface of the semiconductor element, it can be formed as a thin intermediate layer that guarantees good thermal conductivity. The degree of freedom was increased, and material costs and man-hours could be reduced, resulting in a low-cost semiconductor device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図.第2図は本発明の一実施例の半導体装置を示し
、第1図は断面図、第2図は平面図である.
Figure 1. FIG. 2 shows a semiconductor device according to an embodiment of the present invention, FIG. 1 is a sectional view, and FIG. 2 is a plan view.

Claims (1)

【特許請求の範囲】[Claims] 1)容器の金属底板上に少なくとも絶縁性膜、応力緩和
金属膜を介して良ろう付性被膜が積層され、その良ろう
付性被膜上に半導体素体がろう付けされたことを特徴と
する半導体装置。
1) A film with good brazeability is laminated on the metal bottom plate of the container via at least an insulating film and a stress-relaxing metal film, and a semiconductor element is brazed onto the film with good brazeability. Semiconductor equipment.
JP1162948A 1989-06-26 1989-06-26 Semiconductor device Expired - Fee Related JP2604470B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1162948A JP2604470B2 (en) 1989-06-26 1989-06-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1162948A JP2604470B2 (en) 1989-06-26 1989-06-26 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0329348A true JPH0329348A (en) 1991-02-07
JP2604470B2 JP2604470B2 (en) 1997-04-30

Family

ID=15764309

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1162948A Expired - Fee Related JP2604470B2 (en) 1989-06-26 1989-06-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2604470B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5455453A (en) * 1991-07-01 1995-10-03 Sumitomo Electric Industries, Ltd. Plastic package type semiconductor device having a rolled metal substrate
CN117119696A (en) * 2023-08-22 2023-11-24 南通威斯派尔半导体技术有限公司 Manufacturing process suitable for silicon nitride ceramic copper-clad substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57159033A (en) * 1981-03-27 1982-10-01 Hitachi Ltd Semiconductor device and manufacture thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57159033A (en) * 1981-03-27 1982-10-01 Hitachi Ltd Semiconductor device and manufacture thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5455453A (en) * 1991-07-01 1995-10-03 Sumitomo Electric Industries, Ltd. Plastic package type semiconductor device having a rolled metal substrate
US5643834A (en) * 1991-07-01 1997-07-01 Sumitomo Electric Industries, Ltd. Process for manufacturing a semiconductor substrate comprising laminated copper, silicon oxide and silicon nitride layers
CN117119696A (en) * 2023-08-22 2023-11-24 南通威斯派尔半导体技术有限公司 Manufacturing process suitable for silicon nitride ceramic copper-clad substrate

Also Published As

Publication number Publication date
JP2604470B2 (en) 1997-04-30

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