JPH03289802A - Electronic circuit - Google Patents
Electronic circuitInfo
- Publication number
- JPH03289802A JPH03289802A JP2091617A JP9161790A JPH03289802A JP H03289802 A JPH03289802 A JP H03289802A JP 2091617 A JP2091617 A JP 2091617A JP 9161790 A JP9161790 A JP 9161790A JP H03289802 A JPH03289802 A JP H03289802A
- Authority
- JP
- Japan
- Prior art keywords
- electronic circuit
- power supply
- current
- circuit
- electronic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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- Amplifiers (AREA)
- Circuits Of Receivers In General (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、低消費電流動作を可能とする回路構成の電子
回路に関し、特に低消費電流動作が必要な携帯電話等の
受信機に使用する低雑音増幅器および周波数変換器から
成る受信フロントエンド回路等に好適な電子回路に関す
るものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an electronic circuit having a circuit configuration that enables low current consumption operation, and particularly for use in receivers such as mobile phones that require low current consumption operation. The present invention relates to an electronic circuit suitable for a reception front-end circuit consisting of a low-noise amplifier and a frequency converter.
[従来の技術]
従来の一般的な電子回路の構成を第3図のブロック図に
示す。この従来例の電子回路の構成において、101.
102は2つの独立な電子回路であり、+03は電源、
104は電源+03から各電子回路101,102に電
流供給を行う電流線、105は電子回路101の入力端
子、106は電子回路1の出力端子、+07は電子回路
2の入力端子、108は電子回路2の出力端子である。[Prior Art] The configuration of a conventional general electronic circuit is shown in the block diagram of FIG. In the configuration of this conventional electronic circuit, 101.
102 is two independent electronic circuits, +03 is a power supply,
104 is a current line that supplies current from the power supply +03 to each electronic circuit 101, 102, 105 is an input terminal of electronic circuit 101, 106 is an output terminal of electronic circuit 1, +07 is an input terminal of electronic circuit 2, and 108 is an electronic circuit This is the second output terminal.
上記において、各電子回路101.102は、電流線1
04を通し電源103から直流電流109110がそれ
ぞれに並列に供給されて駆動され、入力端子105,1
07よりRF倍信号を人力して、出力端子106,10
8に各々の出力信号を発生する。入出力端子106 、
+ + 07は、用途により接続される場合もある。In the above, each electronic circuit 101.102 has a current line 1
DC current 109110 is supplied in parallel from the power supply 103 through 04 to drive the input terminals 105 and 1.
From 07, the RF multiplied signal is manually output to output terminals 106 and 10.
8 to generate respective output signals. Input/output terminal 106,
+ +07 may be connected depending on the purpose.
このような電子回路の一例として、受信フロントエンド
回路がある。第4図は、その受信フロントエンド回路の
従来例を示すブロック図である。An example of such an electronic circuit is a reception front end circuit. FIG. 4 is a block diagram showing a conventional example of the receiving front end circuit.
この受信フロントエンド回路の構成において、111は
低雑音増幅器であって上記電子回路+01に相当し、+
12は周波数変換器であって上記電子回路102に相当
している。この実施例のその他の要素は第3図で示した
同一符号の要素と同様である。この実施例では、低雑音
増幅器IIIの出力端子+06か周波数変換器112の
入力端子107に接続され、第3図の場合と同様に、両
者の回路111,112は、電流線104を通し電源1
03からそれぞれに直流電流109,110が並列に供
給されて駆動され、入力端子105より受信したRF倍
信号周波数変換して、出力端子108にIF倍信号発生
する。In the configuration of this reception front-end circuit, 111 is a low noise amplifier and corresponds to the above electronic circuit +01;
12 is a frequency converter, which corresponds to the electronic circuit 102 described above. The other elements of this embodiment are similar to the elements shown in FIG. 3 with the same reference numerals. In this embodiment, the output terminal +06 of the low noise amplifier III is connected to the input terminal 107 of the frequency converter 112, and as in the case of FIG.
DC currents 109 and 110 are supplied in parallel from 03 to drive the RF multiplied signal received from the input terminal 105, and an IF multiplied signal is generated at the output terminal 108.
なお、入出力端子106,10.7の間には、用途によ
り帯域外信号除去用のフィルタを挿入する場合もある。Note that a filter for removing out-of-band signals may be inserted between the input and output terminals 106 and 10.7 depending on the purpose.
[発明が解決しようとする課題]
しかしながら、上記従来の技術における電子回路では、
第3図、第4図のいずれの場合にも、各電子回路101
.102(または111,112)に、駆動用の直流電
流109.110が個別に必要であるために、電子回路
全体に流れる電流は、両回路101,102(または1
11.112)の電流109,110の和となり、消費
電流が大きいという問題点があった。このため、電池を
電源とするような携帯用電話等への応用では、使用可能
時間が短くなり、長時間使用が可能な装置の実現を困難
にしていた。[Problem to be solved by the invention] However, in the electronic circuit in the above-mentioned conventional technology,
In either case of FIG. 3 or FIG. 4, each electronic circuit 101
.. 102 (or 111, 112) requires separate DC currents 109 and 110 for driving, so the current flowing through the entire electronic circuit is limited to both circuits 101, 102 (or 1
11.112), which is the sum of the currents 109 and 110, which poses a problem in that the current consumption is large. For this reason, when applied to mobile phones and the like that use batteries as a power source, the usable time is shortened, making it difficult to realize a device that can be used for a long time.
本発明は、上記問題点を解決するために創案されたもの
で、特に受信フロントエンド回路などに好適な、消費電
流の少ない電子回路を提供することを目的とする。The present invention was devised to solve the above-mentioned problems, and an object of the present invention is to provide an electronic circuit with low current consumption, which is particularly suitable for reception front-end circuits and the like.
[課題を解決するための手段]
上記の目的を達成するための本発明の電子回路の構成は
、
第1の電子回路と第2の電子回路とを有し、前記第1の
電子回路の電源線の正極側を高周波的に高抵抗かつ低電
圧な特性を有する第1の非線形素子を介して電源に接続
し、
前記第1の電子回路の電源線の正極側を高周波的に高抵
抗かつ低電圧な特性を有する第2の非線形素子を介して
前記第1の電子回路の電源線の負極側に接続することを
特徴とする。[Means for Solving the Problems] The configuration of an electronic circuit of the present invention for achieving the above object includes a first electronic circuit and a second electronic circuit, and a power source for the first electronic circuit. A positive side of the line is connected to a power source via a first nonlinear element having high resistance and low voltage characteristics at high frequencies, and a positive side of the power line of the first electronic circuit is connected to a power source having high resistance and low voltage characteristics at high frequencies. It is characterized in that it is connected to the negative electrode side of the power supply line of the first electronic circuit via a second nonlinear element having voltage characteristics.
[作用j
本発明は、第1の電子回路の電源線と第2の電子回路の
電源線を電源に対して直列になるように接続することに
より、双方の電子回路を共通の直流電流で動作させるこ
とにより、従来のように並列に直流電流を供給する場合
に比へ、消費電流をほぼ1/2以下に減少させて、低消
費電流化を図る。このときに、各電子回路の正極側へは
高周波的に高抵抗かつ低電圧降下な特性を有する非線形
素子を挿入することにより、第1の電子回路と第2の電
子回路とを高周波的に分離し、一方の電子回路の動作が
他方の電子回路の動作に悪影響を及ぼさないようして、
各電子回路が良好に動作できるようにする。[Operation j] The present invention connects the power line of the first electronic circuit and the power line of the second electronic circuit in series with the power supply, thereby operating both electronic circuits with a common DC current. By doing so, the current consumption can be reduced to approximately 1/2 or less compared to when direct current is supplied in parallel as in the conventional case, thereby achieving low current consumption. At this time, the first electronic circuit and the second electronic circuit are separated at high frequency by inserting a nonlinear element having high resistance and low voltage drop characteristics at high frequency into the positive electrode side of each electronic circuit. and ensure that the operation of one electronic circuit does not adversely affect the operation of the other electronic circuit.
Enable each electronic circuit to operate well.
[実施例コ
以下、本発明の実施例を図面に基づいて詳細に説明する
。[Embodiments] Hereinafter, embodiments of the present invention will be described in detail based on the drawings.
第1図は本発明の基本的な実施例を示すブロック図であ
る。本実施例の構成において、■は一つの電子回路、2
はもう一つの電子回路、IXは電子回路1の正極側の電
源線、1yは電子回路1の負極側の電源線、2Xは電子
回路2の正極側の電源線、2yは電子回路2の負極側の
電源線、3は電源、4.5は例えば搬送周波数帯のよう
な高周波において高周波的に高抵抗でかつ低電圧降下な
特性を有する非線形抵抗素子、6は電子回路1の入力端
子、7は電子回路lの出力端子、8は電子回路2の入力
端子、9は電子回路2の出力端子、IOは電源3より供
給される電流、11は電源線2bに流れる電流である。FIG. 1 is a block diagram showing a basic embodiment of the present invention. In the configuration of this embodiment, ■ is one electronic circuit,
Another electronic circuit, IX is the power line on the positive side of electronic circuit 1, 1y is the power line on the negative side of electronic circuit 1, 2X is the power line on the positive side of electronic circuit 2, and 2y is the negative side of electronic circuit 2. side power supply line, 3 is a power supply, 4.5 is a nonlinear resistance element having high resistance and low voltage drop characteristics at high frequencies such as the carrier frequency band, 6 is an input terminal of the electronic circuit 1, 7 is an output terminal of the electronic circuit 1, 8 is an input terminal of the electronic circuit 2, 9 is an output terminal of the electronic circuit 2, IO is a current supplied from the power supply 3, and 11 is a current flowing through the power supply line 2b.
上記構成の接続において、電子回路2の正極側の電源線
2xは非線形抵抗素子4を通して電源3に接続され、電
子回路lの正極側の電源線lxは非線形抵抗素子5を通
して電子回路2の負極側の電源線2yに接続され、電子
回路1の負極側の電源線lyは回路グランドに接続され
る。また、用途によって、電子回路Iの出力端子7は、
電子回路2の入力端子8に接続される。In the connection of the above configuration, the power line 2x on the positive side of the electronic circuit 2 is connected to the power source 3 through the nonlinear resistance element 4, and the power line lx on the positive side of the electronic circuit l is connected to the negative side of the electronic circuit 2 through the nonlinear resistance element 5. The negative electrode side power line ly of the electronic circuit 1 is connected to the circuit ground. Depending on the application, the output terminal 7 of the electronic circuit I may be
It is connected to the input terminal 8 of the electronic circuit 2.
以上のように構成した第1の実施例の動作および作用を
述へる。The operation and effect of the first embodiment configured as above will be described.
上記の電源線lx、Iy、2x、2yの接続によって、
電源3から非線形抵抗素子4を通して電子回路2に供給
された電流IOは、電子回路2−電源線2y−非線形抵
抗素子5−電源線IXを通して電子回路1へ供給される
。従って、その供給電流11は上記電流IOに等しいも
のとなる。即ち、本実施例では、双方の電子回路1.2
が共通の直流電流で駆動される。その結果、第3図の従
来例に示すように、各電子回路に並列に直流電流を供給
する場合に比べ、消費電流をほぼI/2に減少させるこ
とができる。このときに、各電子回路1.2の正極側に
挿入した非線形抵抗素子4゜5は高周波的に高抵抗かつ
低電圧降下な特性を有しているので、2つの電子回路1
.2は高周波的に分離され、一方の電子回路1(または
2)の動作が他方の電子回路2(またはl)の動作に影
響与えることがなく、各電子回路1,2は良好に動作す
ることができる。By connecting the power lines lx, Iy, 2x, and 2y above,
A current IO supplied from the power supply 3 to the electronic circuit 2 through the nonlinear resistance element 4 is supplied to the electronic circuit 1 through the electronic circuit 2 - power line 2y - nonlinear resistance element 5 - power line IX. Therefore, the supply current 11 is equal to the current IO. That is, in this embodiment, both electronic circuits 1.2
are driven by a common DC current. As a result, the current consumption can be reduced to approximately I/2 compared to the case where direct current is supplied to each electronic circuit in parallel, as shown in the conventional example of FIG. At this time, since the nonlinear resistance element 4.5 inserted into the positive electrode side of each electronic circuit 1.2 has characteristics of high resistance and low voltage drop at high frequencies, the two electronic circuits 1.
.. 2 are separated in terms of high frequency, the operation of one electronic circuit 1 (or 2) does not affect the operation of the other electronic circuit 2 (or l), and each electronic circuit 1, 2 operates well. I can do it.
第2図は、本発明の第2の実施例を示す回路図である。FIG. 2 is a circuit diagram showing a second embodiment of the invention.
本実施例は、本発明を受信フロントエンド回路に適用し
て具体化した例を示しており、基本的には第1の実施例
と対応して構成されている。This embodiment shows an example in which the present invention is applied to a reception front-end circuit, and basically has a configuration corresponding to the first embodiment.
即ち、本実施例も、電子回路lと電子回路2とを有し、
電子回路2の電源線の正極側(2x)は非線形抵抗素子
4を通して電源3に接続され、電子回路lの電源線の正
極側(IX)は非線形抵抗素子5を通して電子回路2の
電源線の負極側(2y)に接続されて成る。本実施例に
おいて、電子回路1は低雑音増幅器であり、電子回路2
は周波数変換器である。That is, this embodiment also includes an electronic circuit 1 and an electronic circuit 2,
The positive side (2x) of the power line of the electronic circuit 2 is connected to the power source 3 through the nonlinear resistance element 4, and the positive side (IX) of the power line of the electronic circuit l is connected to the negative side of the power line of the electronic circuit 2 through the nonlinear resistance element 5. It is connected to the side (2y). In this embodiment, the electronic circuit 1 is a low noise amplifier, and the electronic circuit 2
is a frequency converter.
低雑音増幅器lは、・電界効果トランジスタ(以下FE
Tと記す)Iaをソース接地FETとして用い、その入
力端子であるゲート端子6に回路の分布定数回路あるい
は整合回路を介してRF倍信号入力し、出力端子である
トレイン端子7から回路の整合回路を介してRF倍信号
出力するように構成される。The low noise amplifier l is a field effect transistor (hereinafter FE).
Ia (denoted as T) is used as a source-grounded FET, and the RF multiplied signal is input to its input terminal, the gate terminal 6, via the circuit's distributed constant circuit or matching circuit, and from the output terminal, the train terminal 7, to the circuit's matching circuit. It is configured to output an RF multiplied signal via the RF signal.
次に、周波数変換器2は、FET2a、2bの対と、F
ET2aに接続されたFET2c、2dの対と、FET
2bに接続されたFET2e、2fの対と、これらの回
路のFET2c、2eを結ふ出力とFET2d、2fを
結ぶ出力とを各ゲート端子に接続したFET2g、2h
の対とから成り、FET2a、2bのゲート端子をRF
入力端子8として、そのゲート端子の各々に互いに逆相
の関係としたRF倍信号入力し、FET2c、2fのゲ
ート端子同士およびFET2d、2eのケート端子同士
の対を局部発振入力端子12として、それらのゲート端
子同士の対の各々に互いに逆相の関係の局部発振信号を
入力し、さらに、上記局部発振信号てRF倍信号周波数
変換されたIF倍信号、FET2g、FET2hの対の
出力に接続されたIP出力端子9の対から出力するよう
に構成される。Next, the frequency converter 2 includes a pair of FETs 2a and 2b, and a pair of FETs 2a and 2b.
A pair of FET2c and 2d connected to ET2a, and a FET
A pair of FETs 2e and 2f connected to FET 2b, and FETs 2g and 2h whose outputs connect FETs 2c and 2e of these circuits and outputs that connect FETs 2d and 2f are connected to each gate terminal.
The gate terminals of FETs 2a and 2b are connected to RF
As input terminals 8, RF multiplied signals having mutually opposite phases are input to each of the gate terminals, and pairs of gate terminals of FETs 2c and 2f and gate terminals of FETs 2d and 2e are used as local oscillation input terminals 12. A local oscillation signal having a phase opposite to each other is inputted to each pair of gate terminals of the circuit, and an IF multiplied signal obtained by converting the frequency of the RF multiplied signal from the local oscillation signal is connected to the output of the pair of FET2g and FET2h. It is configured to output from a pair of IP output terminals 9.
上記において、低雑音増幅器lのドレイン端子側は、F
ET5aを通してFET2a、2bの対のソース端子へ
接続され、かつFET5 bを通してFET2g、2h
の対のソース端子へ接続される。これらのFET5a、
5bは、非線形抵抗素子5を構成している。また、FE
T2c、2eのトレイン端子はFET4aを通し、FE
T2d2fのトレイン端子はFET4bを通し、FET
2gのトレイン端子はFET4cを通し、FET2hの
トレイン端子はFET4dを通して、それぞれ電源3に
接続される。これらのFET4a4b、4c、4dは、
非線形抵抗素子4を構成している。In the above, the drain terminal side of the low noise amplifier l is F
Connected to the source terminals of the pair of FETs 2a and 2b through ET5a, and connected to the source terminals of FETs 2g and 2h through FET5b.
is connected to the source terminal of the pair. These FET5a,
5b constitutes the nonlinear resistance element 5. Also, FE
The train terminals of T2c and 2e pass through FET4a and connect to the FE
The train terminal of T2d2f passes through FET4b, and the FET
The train terminal of FET 2g is connected to the power supply 3 through FET 4c, and the train terminal of FET 2h is connected to power supply 3 through FET 4d. These FETs 4a4b, 4c, 4d are
It constitutes a nonlinear resistance element 4.
以上のように構成した第2の実施例の動作および作用を
説明する。The operation and effect of the second embodiment configured as above will be explained.
上記回路構成におし)で、低雑音増幅器1と周波数変換
器2とはFET5a、5bを通して接続されているため
、電源3により本回路を駆動すると、周波数変換器2の
直流電流はFET5a、5bを介して低雑音増幅器lを
構成するFET I aに流れ込む。従って、低雑音増
幅器1及び周波数変換器2の直流電流が共通化され、低
消費電流化することが可能になる。一方、FET5a、
FET5bは高周波的に極めて大きな抵抗として働くた
め、非線形抵抗素子として動作し、低雑音増幅器1と周
波数変換器2は高周波的には分離されて、両者のRF倍
信号互いに影響を及ぼすことがない。さらに、本実施例
の回路では、すべて低電圧動作に適したFETにより構
成されており、各々のFETの電圧降下はIV以下の低
電圧とすることが可能である。また、本実施例の回路で
は、PET 5段縦積み構成のため、電源電圧を5v以
下で使用でき、電源3として電池を使用することが充分
可能である。以上のことから、本実施例による受信フロ
ントエンド回路は、電池動作が可能な5v印加の電源3
で動作可能であり、直流電流は低雑音増幅器1と周波数
変換器2で共通となっているため、従来に比べ低電流化
でき、さらに高周波的には低雑音増幅器1と周波数変換
器2は影響を及ぼし合うことがなく、従来の回路と同等
の高周波性能を有する特徴を持つ。In the above circuit configuration, the low noise amplifier 1 and frequency converter 2 are connected through FETs 5a and 5b, so when this circuit is driven by the power supply 3, the DC current of the frequency converter 2 is flows into the FET Ia that constitutes the low-noise amplifier l. Therefore, the direct current of the low noise amplifier 1 and the frequency converter 2 is shared, making it possible to reduce current consumption. On the other hand, FET5a,
Since the FET 5b acts as an extremely large resistance in terms of high frequency, it operates as a nonlinear resistance element, and the low noise amplifier 1 and frequency converter 2 are separated in terms of high frequency, so that their RF multiplied signals do not affect each other. Furthermore, the circuit of this embodiment is constructed entirely of FETs suitable for low voltage operation, and the voltage drop of each FET can be set to a low voltage of IV or less. Further, in the circuit of this embodiment, since the PET is stacked in five stages vertically, the power supply voltage can be used at 5 V or less, and it is fully possible to use a battery as the power supply 3. From the above, the reception front end circuit according to this embodiment has a 5V power supply 3 that can be operated by a battery.
Since the DC current is common to the low noise amplifier 1 and the frequency converter 2, the current can be lower than before, and in terms of high frequencies, the low noise amplifier 1 and the frequency converter 2 have no influence. It has the characteristic of having high frequency performance equivalent to conventional circuits without affecting each other.
なお、第1の実施例において、電子回路1.2はその位
置を入れ替えても良いことは明らかで、その場合は、電
源3側に近い電子回路へ信号の入力を行い、グランド側
に近い電子回路から出力を行うことができる。また、第
2の実施例で示したように、各非線形抵抗素子は、各電
子回路部分の回路構成に応じて、複数素子で構成しても
良い。Note that in the first embodiment, it is clear that the positions of the electronic circuits 1 and 2 may be interchanged; in that case, the signal is input to the electronic circuit closer to the power supply 3 side, and the electronic circuit closer to the ground side is inputted. Output can be made from the circuit. Further, as shown in the second embodiment, each nonlinear resistance element may be composed of a plurality of elements depending on the circuit configuration of each electronic circuit portion.
また、本発明は上記受信フロントエンド回路以外にも適
用可能であることは当然である。このように、本発明は
その主旨に沿って種々に応用され、種々の実施性様を取
り得るものである。Furthermore, it is obvious that the present invention can be applied to other circuits other than the reception front-end circuit described above. As described above, the present invention can be applied in various ways in accordance with the spirit thereof, and can be implemented in various ways.
[発明の効果]
以上の説明で明らかなように、本発明の電子回路によれ
ば、従来に比べ大幅に低消費電流化が可能となり、無線
装置の受信機の応用の中で、特に電池を電源とする携帯
電話用の回路の長時間使用を容易にする利点が得られる
。[Effects of the Invention] As is clear from the above explanation, the electronic circuit of the present invention allows for significantly lower current consumption compared to the conventional one, and is particularly suitable for use with batteries in receiver applications of wireless devices. The advantage is that it facilitates the long-term use of a circuit for a mobile phone as a power source.
第1図は本発明の第1の実施例を示すブロック図、第2
図は本発明の第2の実施例を示すブロック図、第3図は
一般的な従来例を示すブロック図、第4図は受信フロン
トエンド回路の従来例を示すブロック図である。
1.2・・電子回路、lx、Iy、2x、2y・電源線
、3 電源、4
5・非線形抵抗素子。
第1図FIG. 1 is a block diagram showing a first embodiment of the present invention;
FIG. 3 is a block diagram showing a second embodiment of the present invention, FIG. 3 is a block diagram showing a general conventional example, and FIG. 4 is a block diagram showing a conventional example of a reception front-end circuit. 1.2...Electronic circuit, lx, Iy, 2x, 2y・Power line, 3 Power supply, 4 5・Nonlinear resistance element. Figure 1
Claims (1)
第1の電子回路の電源線の正極側を高周波的に高抵抗か
つ低電圧な特性を有する第1の非線形素子を介して電源
に接続し、 前記第1の電子回路の電源線の正極側を高周波的に高抵
抗かつ低電圧な特性を有する第2の非線形素子を介して
前記第1の電子回路の電源線の負極側に接続することを
特徴とする電子回路。(1) A first nonlinear element having a first electronic circuit and a second electronic circuit, and having high resistance and low voltage characteristics at high frequencies on the positive electrode side of the power supply line of the first electronic circuit. The positive electrode side of the power supply line of the first electronic circuit is connected to the power supply through the second nonlinear element, which has high resistance and low voltage characteristics at high frequencies. An electronic circuit characterized by being connected to the negative electrode side.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2091617A JPH03289802A (en) | 1990-04-06 | 1990-04-06 | Electronic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2091617A JPH03289802A (en) | 1990-04-06 | 1990-04-06 | Electronic circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03289802A true JPH03289802A (en) | 1991-12-19 |
Family
ID=14031535
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2091617A Pending JPH03289802A (en) | 1990-04-06 | 1990-04-06 | Electronic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03289802A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0923166A (en) * | 1995-07-10 | 1997-01-21 | Hidenori Sato | Battery driving type electronic equipment |
JP2009545915A (en) * | 2006-08-04 | 2009-12-24 | アナログ・デバイシズ・インコーポレーテッド | Stacked buffer |
JP2013150162A (en) * | 2012-01-19 | 2013-08-01 | Goyo Electronics Co Ltd | Radio receiver |
-
1990
- 1990-04-06 JP JP2091617A patent/JPH03289802A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0923166A (en) * | 1995-07-10 | 1997-01-21 | Hidenori Sato | Battery driving type electronic equipment |
JP2009545915A (en) * | 2006-08-04 | 2009-12-24 | アナログ・デバイシズ・インコーポレーテッド | Stacked buffer |
JP2013150162A (en) * | 2012-01-19 | 2013-08-01 | Goyo Electronics Co Ltd | Radio receiver |
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