JPH03288217A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the malfunctions of an internal circuit and at the same time to increase the margin of the internal voltage by providing a means which generates the voltage that has the comparatively small reliance onto the voltage of an external power supply and a means which generates the voltage having the comparatively large reliance onto the voltage of the external power supply. CONSTITUTION:An initialization signal generator means 100 outputs an initialization signal which is set at a 1st level for a fixed period after application of an external power supply and then at a 2nd level after the fixed period. A voltage converter A converts the voltage of the external power supply and applies it to an internal circuit 73. That is, the 1st voltage having the comparatively small reliance onto the voltage of the external power supply is applied to the circuit 73 in response to the 1st level for a fixed period after application of the external power voltage. Then the 2nd voltage having the comparatively large reliance onto the voltage of the external power supply is applied to the circuit 73 in response to the 2nd level after the fixed time from the application of the external power supply. Thus the malfunctions of the circuit 73 are prevented and at the same time the margin of the circuit 73 is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device having a voltage conversion circuit that lowers a power supply voltage by a predetermined value and applies the voltage to an internal circuit.

[Conventional technology]

Even if the elements of a semiconductor integrated circuit are miniaturized to 1/K, if the external power supply voltage is left unchanged, the electric field will double. Further, the current density and power consumption density are K times higher. Therefore, problems such as reliability problems due to electromigration and destruction due to heat generation become apparent in semiconductor integrated circuits.

In particular, if the channel length of the NMO8FET is set to submicron while the power supply voltage is 5V, a high electric field will be generated near the drain, and the hot carriers that are accelerated there and gain high energy will fluctuate the threshold voltage of the NMO5FET. This so-called hot carrier problem becomes a major problem when miniaturizing elements while keeping the external power supply voltage constant.

In order to solve these problems, a voltage conversion circuit is provided to apply a voltage lower than the external power supply voltage to the internal circuit.

FIG. 6 is a block diagram showing a semiconductor integrated circuit device provided with a voltage conversion circuit (step-down circuit) as described above. External power supply voltage V applied to power supply pad 71. 0 is the internal voltage vio determined in advance by the step-down circuit 72.
The voltage is stepped down to t and applied to the internal circuit 73.

FIG. 7 is a circuit diagram of a conventional voltage step-down circuit. Resistance 81.8
2 is connected in series between the power supply pad 71 and GND. The common connection point of resistors 81 and 82 is the differential amplifier circuit 86
It is connected to the power of ten people.

Furthermore, diode-connected nMOS transistors 83, 84 and 85 are connected in series between this common connection point and GND. nMOS transistors 83, 84 .
85 constitutes a clamp circuit that maintains the potential at a common connection point of resistors 81 and 82 at a constant value. The step-down nMO5) transistor 87 has its gate connected to the output of the differential amplifier circuit 86, its drain connected to the power supply pad 71, and its source connected to the single power of the differential amplifier circuit 86 and also to the internal circuit 73. has been done.

FIG. 8 is a circuit diagram showing an example of the configuration of the differential amplifier circuit 86. 41 is a constant current source, and 42 and 43 are human-powered nMOS transistors to which input voltages are applied to the gates from human power and human power, respectively. nM OS transistor 42.4
The three sources are connected together. 44 and 45 are PMOS transistors for load. The pMOS transistor 44 has a drain connected to a gate and an n
It is connected to the drain of the MOS transistor 42, and its source is connected to the power supply voltage vcc. The pMOS transistor 45 has a gate connected to the gate of the pMOS transistor 44, a source connected to the power supply voltage Vcc, and a drain connected to the nMOS transistor 44.
3) They are each connected to the drain of the transistor 43.

nMO3) transistor 43 and 9MO3) transistor 45
The common drain connection point of is connected to the input of a CMOS inverter 300 consisting of a pMO5) transistor 46 and an nMO5) transistor 47. The output of the differential amplifier circuit 86 configured in this way will be at a low level when the input voltage to the ten-man power is low, and will be at a high level when the input voltage to the ten-man power is high, with reference to the input voltage to the ten-man power. becomes. In this way, the difference in input terminals between two human forces is amplified.

Next, the operation of the circuit shown in FIG. 7 will be explained. The power supply voltage V applied to the power supply pad 71 is connected to the common connection point of the resistors 81 and 82. A reference voltage V ef determined by the resistance ratio of 0 and the resistors 81 and 82 is generated. Diode connected nMO3) transistor 83
, 84.85, the upper limit of the reference voltage V is clamped to a constant value. The reference voltage V is applied to the differential amplifier circuit 86.
However, the internal voltage Vint is applied to the human power. Therefore, the internal voltage Vint is the reference voltage V
If it is lower than , the output type ref' voltage of the differential amplifier circuit 86 becomes high, and accordingly, the source current of the nMO5) transistor 87 becomes large, and the internal voltage vInt becomes high. Conversely, when the internal voltage V is higher than the reference voltage nt (2), the output voltage ev of the differential amplifier circuit 86 becomes low, and accordingly, the source current of the nMO5) transistor 87 becomes small and the internal voltage V nt becomes small. That is, the source-drain resistance of the nMO transistor 87 changes in accordance with the voltage difference between the reference voltage V 1 and the internal voltage ef Vint, and the internal voltage V 2 corresponding to the reference voltage vrer is supplied to the internal circuit 73nt.

[Invention or problem to be solved]

By the way, in a semiconductor integrated circuit device, when the power is turned on,
Power supply voltage V for internal voltage V. 0 dependence +nt is large (power supply voltage V. Internal voltage V with respect to change of 0
, has a large change, that is, the Int of the power supply voltage V
Int (dotted line in FIG. 9)), where the internal voltage V rises steeply with respect to the rise in cC, and in the internal circuit 73, CMO
Problems arise in that latch-up occurs in the 3-type O3 circuit and that the internal flip-flop circuit malfunctions. Therefore, when the power is turned on, the power supply voltage V is the internal voltage viot. 0 (the change in the internal voltage C vjnt with respect to the change in the power supply voltage V is small, that is, the internal voltage V increases slowly with respect to the increase in the current voltage Vcc) (No. 9
The solid line in the figure)) is preferable.

On the other hand, when the internal circuit 73 is operating, the internal voltage V
If the dependence of int on the power supply voltage Vcc is small, then int the power supply voltage ■. 0 changes at a relatively low voltage (for example, when changing from point a to point b shown in FIG. 9 +nt
When the internal voltage V, decreases from (1) to (2), the internal voltage V, becomes (ret'ref'b), and there is a problem that the margin of the internal voltage V, decreases to 1n. If the dependence of the internal voltage V on the power supply voltage Vco is large (dotted line in Figure 9), even if the power supply voltage VCC changes from point a to point B, the internal voltage V
does not change from the reference voltage V.

int ref Therefore, when the internal circuit 73 is operating, the internal voltage V,
The power supply voltage V. It is desirable for int to have a large dependence on 0. Incidentally, the dashed line in FIG. 9 shows the relationship between the power supply voltage V 1 and the internal voltage v1ntC in the case where the step-down circuit 72 is not provided.

This invention was made to solve the above-mentioned problems, and the voltage applied to the internal circuit is set to a voltage that has little dependence on the power supply voltage during the period from when the power is turned on until the internal circuit operates. , it is an object of the present invention to obtain a semiconductor integrated circuit device in which the voltage is highly dependent on the power supply voltage during operation of the internal circuit. , an initialization signal generating means for outputting a first initialization signal for a certain period from when the external power supply is turned on and a second initialization signal after the elapse of the certain period; a voltage conversion circuit for supplying a voltage to the circuit, the voltage conversion circuit comprising a first voltage generating means for generating a first voltage having a relatively small dependence on the voltage of the external power supply; a second voltage generating means for generating a second voltage having a relatively large dependence on the second voltage; and selective means for selectively applying the second voltage to the internal circuit.

[Effect]

The voltage integrated circuit according to the present invention supplies a first voltage that is relatively small in dependence on the voltage of the external power source to the internal circuit in response to the first initialization signal for a certain period of time after turning on the external power source. This avoids malfunction of the internal circuit, and after a certain period of time has elapsed since the external power supply is turned on, the second initialization signal, which is relatively dependent on the voltage of the external power supply, is A voltage of 2 is applied to the internal circuit, and the internal voltage margin for this increases.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of a drop-down circuit in a semiconductor integrated circuit according to the present invention. In the figure, the difference from the conventional drop-down circuit shown in FIG. 7 is that the initialization signal generation circuit 100. Inverter 56, nMOS transistor 9
0 and resistor 89 are newly provided. Initialization signal generation circuit 100 provides initialization signal 63 to the gate of nMOS transistor 90 via inverter 56 . resistance 8
9 is connected between resistor 88 and ground. n M OS
The gate and drain of transistor 90 are each connected to both ends of eight resistors. The other configurations are the same as the conventional circuit.

FIG. 2 is a circuit diagram showing an example of the configuration of the initialization signal generation circuit 100. The resistor 51 and capacitor 52 are connected to the power supply voltage V.

It is connected in series between 0 and ground.

A common connection point between the resistor 51 and the capacitor 52 is connected to the input of a CMOS inverter 200 composed of a pMOS transistor 53 and an nMOS transistor 54. The output of CMOS inverter 200 is given to impeller 56 via drive inverter 55.

First, the operation of the initialization signal generation circuit 100 will be explained with reference to FIG. In FIG. 3, the horizontal axis is time t and the vertical axis is voltage V. In the figure, 61 is the power supply voltage V, 62 is the voltage at the CO2 common connection point of the resistor 51 and capacitor 51, and 63 is the initialization signal. . When the power is turned on, the power supply voltage V rises. Furthermore, the voltage 62 also rises slowly with a time constant determined by the values of the resistor 51 and capacitor 52.

This voltage 62 is the threshold value V of the CMOS inverter 2aO.
When t is exceeded, the output of the CMOS inverter 200 is inverted, and this output is output as the initialization signal 63 via the driving inverter 55. The initialization signal 63 rises after a certain period of time has elapsed since the power was turned on, as shown in FIG.

Returning to FIG. 1, since the inverted signal of the initialization signal 63 is applied to the gate of the nMO3h transistor 90, when the initialization signal 63 is at a low level, the nMO3h transistor 90
becomes conductive, and when the initialization signal 63 is at a high level, the nMO3) transistor 90 becomes non-conductive. As described above, the initialization signal 63 is at a low level for a certain period of time after the power is turned on, and then is at a high level, so that the nMOS transistor 90 is in a conductive state for a certain period of time after the power is turned on, and then becomes a non-conductive state. As a result, the supply voltage V of the internal voltage V. The dependence on 0 is determined by the ratio R81/R88 of the resistance value R81 of the resistor 81 and the resistance value R88 of the resistor 88 for a certain period after the power is turned on, and when the internal circuit 73 operates after a certain period of time, the resistance 81 resistance value R8
1, the resistance value R88 of resistor 88, and the resistance value R8 of resistor 8
It is determined by the ratio R81/(R88+R89) of the sum with 9. The relationship between the power supply voltage V and the internal voltage Vjot in this case is shown in FIG. For a certain period of time from the time the power is turned on, the relationship is as shown by the solid line 31. In other words, for a certain period of time from when the power is turned on, the dependence of the internal voltage V on the power supply voltage vcc becomes small (that is, the change in the internal voltage V with respect to a change in the power supply voltage V.0 is small, and the increase in the internal voltage vint ), when the power is turned on, CMO8 type O
Inconveniences such as the occurrence of latch-up in the 8 circuits and malfunction of internal flip-flops can be avoided.

On the other hand, after the certain period of time has elapsed (when the internal circuit 73 is operating)
The relationship is as shown by the solid line 32. In other words, after a certain period of time has passed since the power was turned on, the power supply voltage V is the internal voltage V. The dependence on 0 increases and nt (i.e., the power supply voltage V. Internal voltage V with respect to a change in 0,
When the internal circuit 73 is operating, the power supply voltage V.

Even if 0 fluctuates in a relatively low range (for example, between points a and b), the internal voltage V 1 does not fluctuate, and the voltage nt voltage margin becomes larger than in the case of the solid line 31.

FIG. 5 is a diagram showing another embodiment of the voltage step-down circuit according to the present invention. In this embodiment, two circuits (reference voltage generation port ef circuit) for generating the reference voltage (2) are provided in parallel on the 10-power side of the differential amplifier circuit 86.
Depending on the level of the initialization signal 63, one of the two reference voltage generating circuits is selectively connected to the differential amplifier circuit 86.

Resistors 21 and 22 are connected to the power supply voltage V. connected in series between 0 and ground. A diode-connected nMOS transistor 23 is connected between the common connection point of the resistors 21 and 22 and the ground.
, 24, 25 are connected in series. Resistance 21.22
There is n between the common connection point and the power of the differential amplifier circuit 86.
MO3) A transistor 27 is connected, and an initialization signal 63 is applied to its gate via an inverter 28. An nMO3) transistor 26 is connected between the common connection point of the resistors 81 and 82 and the terminal of the differential amplifier circuit 86, and the initialization signal 63 is directly applied to its gate. The other configurations are the same as the conventional circuit shown in FIG.

Next, the operation will be explained. When the initialization signal 63 is at a low level (for a certain period of time after the power is turned on), the nMOS transistor 26 is non-conductive, the nMOS transistor 27 is conductive, and the differential amplifier circuit 86 is supplied with the power supply voltage V. A reference voltage V determined by the ratio of the resistance values of the resistors 21 and 22 to er2 is given. On the other hand, when the initialization signal 63 is at a high level (when the internal circuit 73 is operating after the certain period of time has elapsed), the nMOS transistor 26 is in a conductive state, and the nMOS transistor 2 is in a conductive state.
7 becomes non-conductive, and the differential amplifier circuit 86 receives the power supply voltage ■. 0 and the resistance value of the resistor 8182 is applied. Here, the ratio of the resistance values of resistors 21 and 22 is determined by resistor 8
If it is set larger than the ratio of resistance values of 1 and 82, the same effect as in the above embodiment can be obtained.

In the embodiment shown in FIG. 1, there are eight resistors.

Although the nMOS transistor 90 is provided between the resistor 88 and the ground, it may also be provided between the resistor 81 and the power supply voltage vco.

In this case, inverter 56 is not necessary.

Further, in the embodiment shown in FIG. 5, two reference voltage generation circuits are provided to perform this switching, but the nMOS
) A clamp circuit consisting of transistors 23, 24, 25 (nMOs) and a clamp circuit consisting of transistors 8384.85 (nMOs) are shared, and this shared clamp circuit is connected to the differential amplifier circuit 86 and nMOs) transistors 26, 27. Even if it is connected to a connection point, the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, the first voltage generating means generates the first voltage that has a relatively small dependence on the voltage of the external power source, and the first voltage generating means that generates the first voltage that has a relatively high dependence on the voltage of the external power source. an internal circuit that selectively generates the first voltage in response to the first initialization signal and the second voltage in response to the second initialization signal; Since the power supply voltage converter circuit is provided with a selection means for selecting the voltage, the internal circuit does not malfunction when the power is turned on, and the margin of the internal voltage increases when the internal circuit operates.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of an initialization signal generation circuit, and FIG. 3 is a circuit diagram showing an example of the configuration of an initialization signal generation circuit. 4 is a diagram for explaining the operation of the device shown in FIG. 1, FIG. 5 is a circuit diagram showing another embodiment of the invention, and FIG. 6 is a semiconductor integrated circuit diagram. Schematic configuration diagram of circuit device, seventh
8 is a circuit diagram showing a conventional voltage step-down circuit, FIG. 8 is a circuit diagram showing an example of the configuration of a differential amplifier circuit, and FIG. 9 is a diagram for explaining the operation of the circuit shown in FIG. 7. In the figure, 73 is an internal circuit, 81, 88 and 89 are resistors, 86 is a differential amplifier circuit, 87 is a step-down nMO3) transistor, 90 is an nMOs) transistor, and 100 is an initialization signal generation circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) Initialization signal generation means that outputs a first initialization signal for a certain period of time from the time when the external power supply is turned on, and outputs a second initialization signal after the elapse of the certain period of time, and converts the voltage of the external power supply. and a voltage conversion circuit that supplies the voltage to the internal circuit, and the voltage conversion circuit includes: a first voltage generating means that generates a first voltage that has relatively low dependence on the voltage of the external power source; a second voltage generating a second voltage having a relatively large voltage dependence;
voltage generating means, and selection for selectively applying the first voltage to the internal circuit in response to the first initialization signal and the second voltage in response to the second initialization signal. A semiconductor integrated circuit device equipped with means.