JPH03285436A - Test device for asynchronizing circuit - Google Patents

Abstract

PURPOSE:To evaluate output data even at an asynchronizing circuit by electrically separating a hand shake part and a data processing part at the time of a test, processing test data synchronized with a prescribed clock in the data processing part and synchronizing the output signal with the test data. CONSTITUTION:Asynchronizing circuits 5a and 5b are interfaces interposing between an external part and a microprocessor 1. The asynchronizing circuit 5a is equipped with a hand shake part 3a and a data processing part 4a, and the asynchronizing circuit 5b is equipped with a hand shake part 3b and a data processing part 4b. When executing the test, mode select signals are applied from test signal generation circuits 8 and 10 to mode select circuits 7 and 9. In response to these mode select signals, the mode select circuits 7 and 9 separate the hand shake parts and the data processing parts, and the test data synchronized to the prescribed clock are applied to the data processing parts. A signal exerting a prescribed processing upon the test data of the data processing part is applied to an output data evaluation circuit 12. Based on this prescribed clock, the output data evaluation circuit 12 evaluates signals from the data processing parts.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an asynchronous circuit testing device, and in particular, a handshake section that changes the response time of an output signal to an input signal, and a handshake section that processes the output signal from the handshake section. The present invention relates to an asynchronous circuit testing device capable of testing an asynchronous circuit including a signal processing section.

[Prior art and problems to be solved by the invention] Conventionally, when testing a system in which input signals and output signals are synchronized, the system is kept in the same state as the normal system operating state, and simulation data is input to the system. and evaluated the output data from the system.

However, as shown in FIG. 5, there is a handshake section 3 and a data processing section 4 between the microprocessor 1 and the external circuit 2.
When the asynchronous circuit 5 including the The output signal is asynchronous with the simulation data. Therefore, the test device 16 cannot synchronize with the output signal and cannot compare the output data with preset data for determining the display of test results.

For this reason, output data cannot be evaluated in the asynchronous circuit.

The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to provide a test device for an asynchronous circuit that allows accurate evaluation of output data even in an asynchronous circuit.

[Means for Solving the Problems] To achieve the above object, the asynchronous circuit testing device of the present invention includes a handshake unit for changing the response time of an output signal to an input signal, and an output from the handshake unit. A test device for testing an asynchronous circuit including a signal processing section that processes signals, the test signal generating means generating a mode select signal for switching between a test mode and a normal mode, and test data synchronized with a predetermined clock. and a mode select means for switching the normal mode to the test mode in response to a switching signal from the mode select signal to the test mode and transmitting the test data to the data processing section; 1. An asynchronous circuit testing device comprising: output data evaluation means for performing evaluation in synchronization with a predetermined clock.

[Operation of the Invention] In the present invention having the above-mentioned configuration, when performing a test, a mode select signal is applied from the test signal generating means to the mode switching means. The mode switching means disconnects the handshake section and the data processing section in response to this mode select signal, and provides the data processing section with test data synchronized with a predetermined tarok. The data processing section applies a signal obtained by subjecting the test data to predetermined processing to the output data evaluation means. The output data evaluation means evaluates the signal from the data processing section based on the predetermined clock. In other words, except for the handshake section of the asynchronous circuit, the data processing section performs signal processing in a synchronous state, so the output signal of this data processing section and the test data are synchronized, and evaluation can be performed in this synchronous state. This makes it possible to perform tests.

[Embodiments of the Invention] Hereinafter, testing of an asynchronous circuit according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In normal operation, the microprocessor 1 performs processing according to the data flow and the signal I
Output N. The asynchronous circuits 5a and 5b are interfaces interposed between the outside and the microprocessor 1, and the asynchronous circuit 5a has a handshake section 3a and a data processing section 4a, and the handshake section 3a receives signals from the microprocessor 1. In response to IN, a signal A asynchronous with this signal IN is output to the mode selection circuit 7. Furthermore, the asynchronous circuit 5b includes a handshake section 3b1 and a data processing section 4.
b, receives the signal B from the data processing section 4a, and outputs a signal C asynchronous thereto to the mode select circuit 9. The test device 6 includes mode selection circuits 7 and 9, test signal generation circuits 8 and 10 that generate simulation data synchronized with a test clock signal, and a mode selection signal, a test clock signal, and a reset signal.

It has a control device 11 that outputs control signals and the like (see FIGS. 3 and 4 for each signal).

A pattern of good results is set in the output data evaluation circuit in advance, and based on a comparison between the set pattern and the output data from the data processing units 4a and 4b, the data processing units 4a and 4b are evaluated. This is a circuit that evaluates quality.

FIG. 2 is a circuit diagram of the test mode selection circuits 7 and 9 and the test signal generation circuits 8 and 10.

Referring to FIG. 2, when the mode select signal from the control circuit 11 is at a high level, the test mode selection circuit 7 selects a high level. The signal A from the handshake section 3a is selected and given to the data processing section 4a. Conversely, when the mode select signal is at a low level, simulation data synchronized with the test clock from the test signal generation circuit 8 is provided to the data processing section 4a. Note that the test mode selection circuit 9 also performs the same operation as the test mode selection circuit 7 described above.

The test signal generation circuits 8 and 10 include a JK flip-flop circuit 17, an inverter 18, an AND gate 19, 20,
OR Gate 21 or Ranal.

The test signal generation circuits 8 and 10 select either the test data clock CKI or the clock signal CK2 obtained by dividing the clock signal by half as the simulation data D by the control signal from the control circuit 11. When the control signal is set to low level, the test clock signal CKI is passed through the AND gate 20 and the OR gate 21 to the mode selection circuit 7 as the simulation data D, as shown in FIG.
．． given to 9.

When the control signal is set to high level, the JK flip-flop circuit 17 divides the test clock signal CKI into half as shown in FIG. This test clock signal CK2 is used as simulation data D.
The signal is applied to mode selection circuits 7 and 9 through an ND gate 19 and an OR gate 21.

The operation of the asynchronous circuit testing apparatus shown in FIGS. 1 and 2 will be described. In the normal operation mode, the mode select signal is set to high level, and the input signal IN from the microprocessor 1 is sent to the mode select circuit 7 after the response time is changed by the handshake section 3a.
The signal is applied to the data processing section 4a through the ND gate 14 and the OR gate 16. At this time, since the output of the inverter 13 is at a low level, the AND gate 15 is in an inhibited state and the signal from the test signal generation circuit 8 is cut off.

The data given to the data processing section 4a is subjected to predetermined processing and then given to the adjacent handshake section 3b. The signal applied to the handshake section 3b is applied to the test mode selection circuit 9 after a predetermined response time. The test mode selection circuit 9 is the test mode selection circuit 7 described above.
A signal from the handshake section is given to the data processing section 4b by an operation similar to that shown in FIG. After the data processing section 4b performs predetermined processing, a signal is given to the adjacent handshake section.

As described above, the signal IN from the microprocessor 1
are processed one after another asynchronously.

Next, in the test mode, the mode select signal is set to low level, and the AND gate 14 of the test mode selection circuit 7 is in a prohibited state. On the other hand, the output of the inverter 13 becomes high level, and the simulation data synchronized with the test clock from the test signal generation circuit 8 is transferred to the AND gate 15. The signal is applied to the data processing section 4a via the OR gate 16. The data processing section 4a processes the simulation data synchronized with the test clock, and provides the processed signal to the evaluation circuit 12 and the handshake section 3b.

At this time, the adjacent test mode selection circuit 9 also operates in the same manner as the test mode selection circuit 7, and the AND gate 14 of the test mode selection circuit 9 is disabled.
No signal is input from the handshake section 3b. Then, the simulation data synchronized with the test clock from the test signal generation circuit 10 is input to the AND gate 15,
The signal is applied to the data processing section 4b through the R gate 16.

Therefore, the data processing section 4a and the data processing section 4b
Data is given to the output data evaluation circuit 12 at the same timing. The data evaluation circuit 12 compares output data from a plurality of data processing units with a test pattern and evaluates the quality of the output data. Note that in this case, it is also possible to evaluate all output data simultaneously, and it is also possible to evaluate them individually.

In the above embodiment, the mode selection circuits 7 and 9 separate the handshake section 3 and the data output section 4, respectively, and
Since simulation data synchronized with the test clock from the test signal generation circuits 8 and 10 can be given to the data processing section 4, even an asynchronous circuit including an asynchronous handshake section can be used as a test pattern. It becomes possible to perform a based evaluation.

Additionally, in general, when evaluating a data processing unit, in order to change the frequency of the test signal during the evaluation,
A test pattern corresponding to this frequency is prepared in advance on the evaluation circuit 1.
2 side, and it is necessary to evaluate the output data pattern from the data processing units 4a and 4b based on this described frequency. However, if the control signal from the control circuit 11 is set to low level or high level, the test signal generating circuit 8. The frequency of the signal to be evaluated by the evaluation circuit 12 can be automatically changed by IO. Therefore, it is no longer necessary to write the signal to be evaluated in the evaluation circuit 12 in advance, and the operation can be facilitated when it is necessary to change the frequency and perform evaluation.

In the above embodiment, the simplest lock signal is shown as the simulation data synchronized with the test clock, but various simulation data may be generated based on the synchronization clock.

[Effects of the Invention] According to the present invention, the handshake section and the data processing section are electrically separated by the test mode switching means, the data processing section is made to process test data synchronized with a predetermined clock, and the data processing section is Since the output signal from the processing section and the test data can be synchronized, a unique effect can be obtained in that even an asynchronous circuit can be tested in a synchronous state.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram of the mode selection circuit and test signal generation circuit of FIG. 1, and FIGS. FIG. 2 is a timing chart, and FIG. 5 is a diagram for explaining inconveniences when connecting a conventional test device to an asynchronous circuit. In the figure, 1 is a microprocessor and 3a. 3b is a handshake unit, 4a and 4b are data processing units,
5a and 5b are asynchronous circuits, 6 is a test device 7.9 is a mode selection circuit, 8.10 is a test signal generation circuit, 11 is a control circuit, and 12 is an output data evaluation circuit. 'w-JD

Claims (1)

[Scope of Claims] A test device for testing an asynchronous circuit including a handshake section for changing the response time of an output signal to an input signal, and a signal processing section for processing the output signal from the handshake section, a mode select signal for switching between the test mode and the normal mode, and a test signal generating means for generating test data synchronized with a predetermined clock; mode selection means for switching the data processing unit to a test mode and outputting the test data to the data processing unit; and output data evaluation means for evaluating the signal from the data processing unit in synchronization with a predetermined clock. Asynchronous circuit test equipment with special features.