JPH03283646A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03283646A JPH03283646A JP2085382A JP8538290A JPH03283646A JP H03283646 A JPH03283646 A JP H03283646A JP 2085382 A JP2085382 A JP 2085382A JP 8538290 A JP8538290 A JP 8538290A JP H03283646 A JPH03283646 A JP H03283646A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- conductor
- plate
- lead frame
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の［１的〕
（産業上の利用分野）
本発明は、半導体装置に係り、特に半導体集積チップを
実装するリードフレーム構体の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Object 1] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to the structure of a lead frame structure on which a semiconductor integrated chip is mounted.
（従来の技術）
パワートランジスタ等のパワーデバイスを集積化してな
る半導体集積回路の分野では、高いパワーを用いるため
に、電流供給のためのリードはワイヤとの接続部におけ
るインダクタンスの増大を防ぐために、ボンディングワ
イヤに代えてパワープレートを介してチップのポンディ
ングパッドに接続するという方法が取られることが多い
。また、高集積化に従い、リードの本数を低減する目的
から、複数のパッドから接地ラインに落とすような場合
、接地用のプレートを設けこれにすべて接続するという
方法が有力となってきている。(Prior Art) In the field of semiconductor integrated circuits that integrate power devices such as power transistors, in order to use high power, leads for current supply are required to prevent an increase in inductance at the connection with wires. Instead of bonding wires, a method of connecting to the chip's bonding pads via a power plate is often used. Furthermore, as devices become more highly integrated, and in order to reduce the number of leads, a method of providing a grounding plate and connecting all of them to this has become popular when connecting multiple pads to a grounding line.
さらにまた、発熱量も大きいため、ダイパッドに代えて
放熱性の良好な金属板からなる大きな放熱板を必要とす
る傾向にある。Furthermore, since the amount of heat generated is large, there is a tendency to require a large heat sink made of a metal plate with good heat dissipation properties in place of the die pad.
このようなパワーデバイスでは、−例を第３図に示すよ
うに、通常、接地用のグランドプレート１２とパワープ
レート１４とがリードフレーム本体１５に対して各々所
定の部位に設けられた舌片を介して溶接により一体的に
接続されリードフレーム構体を構成している。In such a power device, as shown in FIG. 3, normally, the ground plate 12 and the power plate 14 for grounding each have a tongue piece provided at a predetermined position relative to the lead frame body 15. They are integrally connected via welding to form a lead frame structure.
このため、舌片の折り曲げ精度や、溶接位置精度の影響
により溶接箇所がはがれたり各構成体に歪みを生じたり
することがあった。Therefore, due to the bending accuracy of the tongue piece and the accuracy of the welding position, the welded area may peel off or each component may become distorted.
（発明が解決しようとする問題点）
このように、従来のパワーデバイスでは、接地用のグラ
ンドプレートやパワープレート等とリードフレーム本体
との接続が、各々所定の部位に設けられた舌片を介して
溶接によりなされているため、接続不良や変形を生じ昌
く、これがデバイスとしての信頼性低下の原因となって
いた。(Problems to be Solved by the Invention) As described above, in conventional power devices, the connection between the ground plate, power plate, etc. for grounding and the main body of the lead frame is through tongue pieces provided at predetermined positions. Since they are made by welding, poor connections and deformation often occur, which causes a decrease in reliability as a device.
本発明は、前記実情に鑑みてなされたもので、製造が容
品で信頼性の高い半導体装置を提供することを［１的と
する。The present invention has been made in view of the above-mentioned circumstances, and has one object to provide a semiconductor device that is easy to manufacture and has high reliability.
（課題を解決するための手段）
そこで、本発明の半導体装置では、複数のインナーリー
ドを配列してなるリードフレーム本体に絶縁層を介して
少なくとも１つの導電性プレートを固着し、絶縁層に形
成されたスルーホールに充填された導体を介してこのリ
ードフレーム本体の少なくとも１つのリードと前記導電
性プレートとが接続されるようにしている。(Means for Solving the Problems) Therefore, in the semiconductor device of the present invention, at least one conductive plate is fixed to a lead frame body formed by arranging a plurality of inner leads via an insulating layer, and formed on the insulating layer. At least one lead of the lead frame body is connected to the conductive plate via a conductor filled in the through hole.
（作用）
上記構成により、リードと導電性プレートとが絶縁層に
形成されたスルーホールに充填された導体を介して接続
されているため、歪みや剥がれもなく、高精度の接続を
確実に行うことが可能となる。(Function) With the above configuration, the leads and the conductive plate are connected via the conductor filled in the through hole formed in the insulating layer, ensuring a high-precision connection without distortion or peeling. becomes possible.
すなわち、第３図に示した従来例のリードフレームで用
いられていたような舌片は不要となり、折り曲げ加工の
必要がなくなるため、機械的応力がかからず、剥がれや
歪みを生じることもない。In other words, there is no need for tongues like those used in the conventional lead frame shown in Figure 3, and there is no need for bending, so no mechanical stress is applied and no peeling or distortion occurs. .
（実施例）
以下本発明の実施例について、図面を参照しつつ詳細に
説明する。(Example) Examples of the present invention will be described in detail below with reference to the drawings.
実施例１
第１図は、本発明の第１の実施例のパワーデバイスの要
部を示す断面図である。Embodiment 1 FIG. 1 is a sectional view showing essential parts of a power device according to a first embodiment of the present invention.
このデバイスは、半導体チップ１を載置すると共にグラ
ンドプレートとしての役割を行う第１の導電板２と、こ
の上層に接着剤３を介して固着され、電源ラインに接続
されるパワープレートとしての第２の導電板４と、さら
にこの上層に接着剤３を介して固着され、前記第１の導
電板２の半導体チップ搭載部を囲むように複数のインナ
ーリードを配設してなるリードフレーム本体５とから構
成され、封止樹脂Ｐによって封止せしめられてなるもの
である。This device includes a first conductive plate 2 on which a semiconductor chip 1 is placed and which functions as a ground plate, and a second conductive plate fixed to the upper layer of the first conductive plate 2 via an adhesive 3 and connected to a power supply line. a lead frame main body 5 formed by a second conductive plate 4 and a plurality of inner leads fixed to the upper layer through an adhesive 3 so as to surround the semiconductor chip mounting portion of the first conductive plate 2; and is sealed with a sealing resin P.
このリードフレーム本体５と第１および第２の導電板は
貫通孔Ｈに充填された導電性ペーストを介して電気的に
接続されており、半導体チップ上の各ポンディングパッ
ドとそれぞれを接続するようにボンディングワイヤを介
して接続がなされている。This lead frame main body 5 and the first and second conductive plates are electrically connected via conductive paste filled in the through hole H, and are connected to each bonding pad on the semiconductor chip. Connections are made via bonding wires.
次に、このデバイスの製造］二程について説明する。Next, the second step of manufacturing this device will be explained.
ます、第２図（ａ）に示すように、通常のスタンピング
法により、帯状材料を加−１−シ、半導体チップ載置領
域ｄと対峙す°るインナーリード６、アウターリード７
、タイバー８なとを含む通常のり一ドフレームの形状に
成型する。９はサイドバーである。次いで、コイニング
処理を行い、インナーリート先端部の平用幅を確保した
のち、先端部にめっきを行うめっきを行う。Ｍはめっき
領域を示す。このとき必要に応じて、インナーリード先
端部のボンディングエリアを避けるように熱硬化性樹脂
を介して絶縁性テープを貼着し、加熱工程を経て映化さ
せ、固定するようにしてもよい。First, as shown in FIG. 2(a), a strip of material is stamped using a normal stamping method to form inner leads 6 and outer leads 7 facing the semiconductor chip mounting area d.
, mold into the shape of a normal glued frame including 8 tie bars. 9 is a sidebar. Next, a coining process is performed to ensure a flat width at the tip of the inner reed, and then plating is performed on the tip. M indicates a plating area. At this time, if necessary, an insulating tape may be attached via a thermosetting resin so as to avoid the bonding area at the tip of the inner lead, and the tape may be visualized and fixed through a heating process.
一方、第２図（ｂ）および第２図（Ｃ）に示すように、
また通常のスタンピング法により、放熱性の良好な銅板
を加工し、グランドプレートとしての役割を行う第１の
導電板２と、電源ラインに接続されるパワープレートと
しての第２の導電板４とを形成する。これらの内箱２の
導電板４に対しては、打ち抜き後、表面を絶縁性のポリ
イミド膜１１で被覆すると共に、所定の位置にポリイミ
ド膜１１のみを貫通する第１の貫通穴Ｗと、ポリイミド
膜１１および板本体を貫通する第２の貫通穴Ｈとを配設
し、第２の貫通穴Ｈの側壁は絶縁膜Ｓて被覆するように
する。また、第１の導電板２に対しては、打ち抜き後、
表面を絶縁性のポリイミド膜１１で被覆すると共に、半
導体チップ載置部および、ダイパッドに接続するための
インナーリードの先端の所定の位置にポリイミド膜１１
のみを貫通する第１の貫通穴Ｗを配設する。On the other hand, as shown in FIG. 2(b) and FIG. 2(C),
In addition, a copper plate with good heat dissipation is processed using a normal stamping method, and a first conductive plate 2 that serves as a ground plate and a second conductive plate 4 that serves as a power plate connected to a power supply line are formed. Form. After punching out the conductive plates 4 of the inner box 2, the surface is covered with an insulating polyimide film 11, and a first through hole W that penetrates only the polyimide film 11 is formed at a predetermined position. A second through hole H passing through the film 11 and the plate body is provided, and the side wall of the second through hole H is covered with an insulating film S. Moreover, for the first conductive plate 2, after punching,
The surface is covered with an insulating polyimide film 11, and the polyimide film 11 is coated at a predetermined position on the semiconductor chip mounting part and the tip of the inner lead for connection to the die pad.
A first through hole W is provided that penetrates only through the hole.
そして、第２図（ｄ）に示すように、第１の導電板２の
中央部に半導体チップ１を導電性接着剤１２を介して固
着すると共に、前記第１および第２の導電板の第１およ
び第２の貫通穴Ｈ，Ｗに導電性ペーストＤを充填し、第
１の導電板、第２の導電板、リードフレーム本体５を順
次積層し、絶縁性接着剤３によって一体的に固着する。Then, as shown in FIG. 2(d), the semiconductor chip 1 is fixed to the center of the first conductive plate 2 via a conductive adhesive 12, and the The first and second through holes H and W are filled with conductive paste D, and the first conductive plate, second conductive plate, and lead frame main body 5 are sequentially laminated and fixed together with an insulating adhesive 3. do.
この後、ワイヤボンディングを行い、樹脂封止を行って
、′１８１図に示したようなデバイスが完成する。Thereafter, wire bonding and resin sealing are performed to complete a device as shown in Figure '181.
このようにして形成されたデバイスは、リードと導電性
プレートとが絶縁層に形成されたスルーホールに充填さ
れた導電性ペーストを介して接続されているため、歪み
や剥がれもなく、高精度の接続を確実に行うことが可能
となる。Devices formed in this way have high precision and no distortion or peeling because the leads and conductive plates are connected via conductive paste filled in through holes formed in the insulating layer. It becomes possible to perform the connection reliably.
また、第３図に示した従来例のリードフレームのように
、折り曲げ加工時の機械的応力による剥がれや歪みを生
じることもなく信頼性の高いデバイスを得ることが可能
となる。Furthermore, unlike the conventional lead frame shown in FIG. 3, it is possible to obtain a highly reliable device without peeling or distortion due to mechanical stress during bending.
なお前記実施例では、パワープレートや接地プレートは
、−枚の導電性の板状体で構成したが、絶縁性基板上に
所望のパターンを形成することによって行っても良い。In the above embodiment, the power plate and the ground plate are made of two conductive plate-shaped bodies, but they may be formed by forming a desired pattern on an insulating substrate.
このとき信号線およびグランド線のパターンは、スパッ
タリングおよび電解めっきによって形成された銅薄膜を
フォトリソ法によりパターニングして形成する方法、樹
脂フィルノ、表面に表面処理を行った後、薄い銅箔を直
接圧着したり、接着剤を介して固着したりして銅薄膜を
形成した後パターニングしたりまた、薄い銅箔の表面に
ポリイミド樹脂等の絶縁性樹脂を塗布しこれを硬化する
ことによって銅薄膜を形成した後、同様にフォトリソ法
によりパターニングするなどの方法をとることも可能で
ある。At this time, the signal line and ground line patterns are formed by patterning a copper thin film formed by sputtering and electrolytic plating using photolithography, or by directly pressing a thin copper foil after surface treatment using resin filno. A thin copper film can be formed by attaching it with an adhesive or by patterning it, or by applying an insulating resin such as polyimide resin to the surface of a thin copper foil and curing it. After that, it is also possible to use a similar method such as patterning by photolithography.
また、前記実施例では、ワイヤボンディング方式のリー
ドフレームを用いた例について説明したが、集積Ｈ路チ
ップ載置部に向かって突出する舌片を備えたインナーリ
ードを用いることにより、ダイレクトボンディング方式
にも適用可能である。In addition, in the above embodiment, an example using a wire bonding lead frame was explained, but by using an inner lead having a tongue protruding toward the integrated H-way chip mounting section, a direct bonding method can be used. is also applicable.
さらにまた、複数のインナーリードと、これら複数のイ
ンナーリードのそれぞれに対応して外方に突出する舌片
からなるアウターリードとを配設してなる樹脂フィルム
からなり、表面および裏面の導体層が前記樹脂フィルム
に形成されたスルーホールを介して接続されていると共
に、該舌片を集積回路チップのポンディングパッドに直
接接続するように構成されたいわゆるＴＡＢ技術を用い
たフィルムキャリアにも適用可能である。Furthermore, the resin film is composed of a plurality of inner leads and an outer lead consisting of a tongue piece projecting outward corresponding to each of the plurality of inner leads, and the conductor layer on the front and back surfaces is It is also applicable to a film carrier using so-called TAB technology, which is connected via a through hole formed in the resin film and configured to directly connect the tongue piece to a bonding pad of an integrated circuit chip. It is.
以上説明してきたように、本発明によれば、複数のイン
ナーリードを配列してなるリードフレーム本体に絶縁層
を介して少なくとも１つの導電性プレートを固着し、絶
縁層に形成されたスルーホールに充填された導体を介し
てリードと導電性プレートとが接続されるようにしてい
るため、位置すれや歪みや剥がれもなく、高精度の接続
を確実に行うことが可能となる。As described above, according to the present invention, at least one conductive plate is fixed to a lead frame body formed by arranging a plurality of inner leads via an insulating layer, and the through holes formed in the insulating layer are connected to the lead frame body. Since the leads and the conductive plate are connected through the filled conductor, there is no misalignment, distortion, or peeling, and it is possible to reliably connect with high precision.
第１図は、本発明実施例の半導体装置を示す図、第２図
（ａ）乃至第２図（ｄ）は、同半導体装置の製造］、稈
図、第３図は従来例の半導体装置を示す図である。
１・パ１′導体チップ、２・・・第１の導電板、３・・
・接着剤、４・・・第２の導電板、５・・・リードフレ
ーム本体、Ｐ・・・封止樹脂、ａ・・・半導体チップ載
Ｗ領域、６・・・インナーリード、７・・・アウターリ
ード、８・・・タイバー ９・・・サイドバー、Ｗ・・
・第１の貫通穴、１１・・ポリイミド膜、Ｓ・・・絶縁
膜、Ｈ・・・第２の貫過大。FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention, FIGS. 2(a) to 2(d) are a diagram showing the manufacture of the same semiconductor device, and FIG. 3 is a diagram of a conventional semiconductor device. FIG. 1.Pa1' conductor chip, 2..first conductive plate, 3..
- Adhesive, 4... Second conductive plate, 5... Lead frame body, P... Sealing resin, a... Semiconductor chip mounting W area, 6... Inner lead, 7...・Outer lead, 8...Tie bar 9...Side bar, W...
- First through hole, 11... polyimide film, S... insulating film, H... second through hole.
Claims (2)
と、前記半導体チップ載置部上に第１の絶縁層を介して
積層された導電性プレートと、前記導電性プレート上に
第２の絶縁層を介して積層され、前記半導体チップの周
縁に先端がくるように、複数のリードを表面に配設して
なるリードフレーム本体とを具備し、前記導電性プレー
トは前記第２の絶縁層に形成されたスルーホールに充填
された導体を介してリードフレーム本体の少なくとも１
つのリードに接続されるようにしたことを特徴とする半
導体装置。(1) A semiconductor chip placed on a semiconductor chip rest, a conductive plate laminated on the semiconductor chip rest via a first insulating layer, and a second insulating layer laminated on the conductive plate. a lead frame body formed by laminating a plurality of leads on the surface thereof such that the leads are laminated with an insulating layer interposed therebetween so that the tips thereof are located at the periphery of the semiconductor chip, and the conductive plate is connected to the second insulating layer. At least one of the lead frame bodies is connected through a conductor filled in a through hole formed in the lead frame body.
A semiconductor device characterized in that it is connected to two leads.
、接地導体を構成していることを特徴とする請求項（１
）に記載の半導体装置。(2) Claim (1) characterized in that the semiconductor chip mounting portion is made of a conductor plate and constitutes a ground conductor.
).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8538290A JP2740977B2 (en) | 1990-03-30 | 1990-03-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8538290A JP2740977B2 (en) | 1990-03-30 | 1990-03-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03283646A true JPH03283646A (en) | 1991-12-13 |
| JP2740977B2 JP2740977B2 (en) | 1998-04-15 |
Family
ID=13857191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8538290A Expired - Fee Related JP2740977B2 (en) | 1990-03-30 | 1990-03-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2740977B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06283655A (en) * | 1993-03-26 | 1994-10-07 | Kyocera Corp | Package for housing semiconductor element |
| US5438478A (en) * | 1992-10-20 | 1995-08-01 | Ibiden Co., Ltd. | Electronic component carriers and method of producing the same as well as electronic devices |
| JPH07509729A (en) * | 1992-12-16 | 1995-10-26 | シェリング−プラウ・ヘルスケア・プロダクツ・インコーポレーテッド | How to tan without sunlight |
| US5864173A (en) * | 1995-04-05 | 1999-01-26 | National Semiconductor Corporation | Multi-layer lead frame |
| US5895977A (en) * | 1996-08-08 | 1999-04-20 | Intel Corporation | Bond pad functional layout on die to improve package manufacturability and assembly |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63188962A (en) * | 1987-01-31 | 1988-08-04 | Sumitomo Electric Ind Ltd | Packages for integrated circuits |
| JPH01251743A (en) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | Package for semiconductor integrated circuit |
-
1990
- 1990-03-30 JP JP8538290A patent/JP2740977B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63188962A (en) * | 1987-01-31 | 1988-08-04 | Sumitomo Electric Ind Ltd | Packages for integrated circuits |
| JPH01251743A (en) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | Package for semiconductor integrated circuit |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5438478A (en) * | 1992-10-20 | 1995-08-01 | Ibiden Co., Ltd. | Electronic component carriers and method of producing the same as well as electronic devices |
| JPH07509729A (en) * | 1992-12-16 | 1995-10-26 | シェリング−プラウ・ヘルスケア・プロダクツ・インコーポレーテッド | How to tan without sunlight |
| JPH06283655A (en) * | 1993-03-26 | 1994-10-07 | Kyocera Corp | Package for housing semiconductor element |
| US5864173A (en) * | 1995-04-05 | 1999-01-26 | National Semiconductor Corporation | Multi-layer lead frame |
| US5994768A (en) * | 1995-04-05 | 1999-11-30 | National Semiconductor Corporation | Multi-layer lead frame |
| US6087204A (en) * | 1995-04-05 | 2000-07-11 | National Semiconductor Corporation | Method of making a multi-layer lead frame |
| US5895977A (en) * | 1996-08-08 | 1999-04-20 | Intel Corporation | Bond pad functional layout on die to improve package manufacturability and assembly |
| US6214638B1 (en) | 1996-08-08 | 2001-04-10 | Intle Corporation | Bond pad functional layout on die to improve package manufacturability and assembly |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2740977B2 (en) | 1998-04-15 |
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