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JPH03283532A - Silicon substrate for discrete element - Google Patents

Silicon substrate for discrete element

Info

Publication number
JPH03283532A
JPH03283532A JP8346690A JP8346690A JPH03283532A JP H03283532 A JPH03283532 A JP H03283532A JP 8346690 A JP8346690 A JP 8346690A JP 8346690 A JP8346690 A JP 8346690A JP H03283532 A JPH03283532 A JP H03283532A
Authority
JP
Japan
Prior art keywords
etching
silicon wafer
lapping
silicon substrate
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8346690A
Other languages
Japanese (ja)
Other versions
JP2541680B2 (en
Inventor
Yasushi Yoshimura
康 吉村
Zenichi Igarashi
五十嵐 善市
Koichi Nishimaki
宏一 西巻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Naoetsu Electronics Co Ltd
Original Assignee
Naoetsu Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Naoetsu Electronics Co Ltd filed Critical Naoetsu Electronics Co Ltd
Priority to JP8346690A priority Critical patent/JP2541680B2/en
Publication of JPH03283532A publication Critical patent/JPH03283532A/en
Application granted granted Critical
Publication of JP2541680B2 publication Critical patent/JP2541680B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Weting (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To reduce crystal defects after diffusion and also precipitates by performing a predetermined thickness etching on one side of a silicon wafer after lapping. CONSTITUTION:A portion of a silicon wafer 1, 0.5 to 1.5mum from the surface thereof, is removed by alkali etching. The range of the alkali etching is the removal of a crushed layer 2 formed by lapping. An etching allowance should be 0.5 to 1.5mum, and preferably 1.0+ or -0.5mum. As a consequence, the crushed layer formed on the lapped wafer can be removed completely, permitting contamina tion in the crushed layer to be removed. In addition, the amount of precipitates is small. A decrease in the yield of devices can be prevented and crystal characteristics can be improved.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はディスクリート素子用シリコン基板の改良に関
する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to improvements in silicon substrates for discrete devices.

(従来の技術) 一般的に、ディスクリート素子用シリコン基板は、イン
ゴット→切断→面取り→ラッピングの工程を経た後、洗
浄を行なってコレクタ拡散工程に投入され、表面に不純
物拡散層が形成されて製品となる。
(Prior technology) Generally, silicon substrates for discrete devices go through the steps of ingot → cutting → chamfering → lapping, then are cleaned and put into the collector diffusion process, where an impurity diffusion layer is formed on the surface and the product is manufactured. becomes.

(発明が解決しようとする課題) 上記した従来のディスクリート素子用シリコン基板は、
拡散工程に投入される前に洗浄処理されて供給されるが
、その洗浄は表面から0.1μ位(第1図中のa線)ま
でを洗浄するだけであるため、破砕層中の汚染物の除去
が困難であると共に、ラップ面から生成する析出物(粒
子)が極端に多くなり、デバイス歩留りを低下させると
いった問題点を有する。
(Problem to be solved by the invention) The conventional silicon substrate for discrete elements described above is
The products are cleaned and supplied before being put into the diffusion process, but this cleaning only cleans up to about 0.1μ from the surface (line a in Figure 1), so contaminants in the crushed layer are removed. There are problems in that it is difficult to remove, and the amount of precipitates (particles) generated from the lapped surface becomes extremely large, reducing device yield.

本発明は上述した如き従来の技術の有する問題点に鑑み
てなされたもので、その目的とする処は、拡散後の結晶
欠陥の発生が少なく、且つ析出物の生成も少ない結晶特
性の改善されさたディスクリート素子用シリコン基板を
提供することにある。
The present invention has been made in view of the problems of the conventional technology as described above, and its purpose is to improve crystal properties with less generation of crystal defects and less generation of precipitates after diffusion. Another object of the present invention is to provide a silicon substrate for a discrete element.

(課題を解決するための手段) 上記目的を達成するために、本発明におけるディスクリ
ート素子用シリコン基板は、ラッピング後のシリコンウ
ェハを片面で0.5〜1.5μmエツチング処理したこ
とを特徴とする。
(Means for Solving the Problems) In order to achieve the above object, the silicon substrate for discrete elements in the present invention is characterized in that the silicon wafer after lapping is etched by 0.5 to 1.5 μm on one side. .

上記のエツチング処理としてはアルカリエッチ、酸エッ
チ等が用いられ、そのエツチング代はラッピング後にお
けるシリコンウェハの表面層に存在する破砕層(0,5
〜1.0μm)を完全に除去する0、5〜1.5μmと
する。
Alkali etching, acid etching, etc. are used as the above etching process, and the etching depth is the same as the fracture layer (0,5
~1.0 μm) to completely remove 0.5 to 1.5 μm.

上記のエツチング化が0.5μm以下の場合は、シリコ
ン基板表面に破砕層が残り、拡散後に生成する析出物が
極端に多くなり、デバイス歩留りを低下させるため好ま
しくない。
If the etching is less than 0.5 .mu.m, a fractured layer remains on the surface of the silicon substrate, and the amount of precipitates generated after diffusion becomes extremely large, which is undesirable because it reduces device yield.

又、エツチング化が1.5μmm以上の場合は、拡散後
に生じる結晶欠陥(線欠陥)が高密度になり、品質が低
下するといった不具合を有し好ましくない。
Furthermore, if the etching thickness is 1.5 .mu.mm or more, crystal defects (line defects) generated after diffusion become dense, which is undesirable since quality deteriorates.

(作用) 上記手段によれば、ラッピング後のシリコンウェハを表
面より0.5〜1.5μmエツチング処理することによ
り、ラップ後のシリコンウェハに形成される破砕層(0
,5〜1.0μm)は完全に除去され、その結果、拡散
後に生成する析出物は少なくなり、結晶特性が改善され
る。
(Function) According to the above means, by etching the silicon wafer after lapping by 0.5 to 1.5 μm from the surface, the fracture layer (0
, 5-1.0 μm) are completely removed, resulting in fewer precipitates forming after diffusion and improved crystal properties.

(発明の効果) オ発明のディスクリート素子用シリコン基板は、以上詳
述したように、ラッピング後のシリコンウェハを片面で
0.5〜1.5μmエツチング処理したものであるから
、ラップ後のウェハに形成されている破砕層は完全に除
去でき、従って破砕層中の汚染物を除去できる。
(Effects of the Invention) E. As detailed above, the silicon substrate for discrete elements of the invention is a silicon wafer that has been lapped and is etched by 0.5 to 1.5 μm on one side. The fractured layer that has been formed can be completely removed and therefore the contaminants in the fractured layer can be removed.

又、エツチング化を0.5〜1.5μmとしたことによ
り、拡散後に生成する析出物は少なく、デバイス歩留り
の低下を防止できると共に、結晶特性を改善できて高品
位のシリコン基板を提供することが出来る。
In addition, by setting the etching depth to 0.5 to 1.5 μm, there are few precipitates generated after diffusion, which prevents a decrease in device yield, and improves crystal characteristics, thereby providing a high-quality silicon substrate. I can do it.

(実施例) 以下、本発明の実施例を図面に基づいて説明すると、図
中、1はラッピング後のシリコンウェハを示し、そのシ
リコンウェハ1の表面から0.5〜1.5μmをアルカ
リエツチングで除去する。
(Example) Hereinafter, an example of the present invention will be described based on the drawings. In the figure, 1 indicates a silicon wafer after lapping, and 0.5 to 1.5 μm from the surface of the silicon wafer 1 is etched by alkali etching. Remove.

アルカリエツチングで除去する範囲はラッピングによっ
て形成された破砕層(0,5〜1.0μm)2を除去す
るものである。
The range to be removed by alkali etching is to remove the crushed layer (0.5 to 1.0 μm) 2 formed by lapping.

尚、アルカリエツチングによるエツチング化と拡散後の
シリコンウェハ表面におけるエッチピットの数(密度)
及び析出物密度は第2図の如くなり、これからもエツチ
ング化が0.5〜1.5μm1好ましくは1.0±0.
5μmの範囲がもっとも効果的であることが理解される
In addition, the number (density) of etch pits on the silicon wafer surface after etching and diffusion by alkali etching.
The precipitate density is as shown in Figure 2, and the etching is 0.5 to 1.5 μm, preferably 1.0±0.
It is understood that a range of 5 μm is most effective.

又、上記のアルカリエツチングとしては、水酸化カリウ
ムの水溶液(KOH)を用いる。
Further, for the above-mentioned alkaline etching, an aqueous solution of potassium hydroxide (KOH) is used.

次に、本発明品と従来品との不純物の付着量を調べた実
験結果について説明する。
Next, the results of an experiment in which the amount of impurities deposited between the product of the present invention and the conventional product will be explained.

〔実験サンプル〕[Experiment sample]

本発明品:ラッピング後のシリコンウェハを水酸化カリ
ウム(KOH)のエツチング液 で破砕層を除去する1、0μmmエツチングした。
Product of the present invention: After lapping, the silicon wafer was etched to a depth of 1.0 μm using a potassium hydroxide (KOH) etching solution to remove the fractured layer.

従来品:ラッピング後のシリコンウェハを水酸化ナトリ
ウム(NaOH)の1%水溶 液で0.1μ以下の洗浄を行なったも の。
Conventional product: A silicon wafer that has been wrapped and cleaned with a 1% aqueous solution of sodium hydroxide (NaOH) to a thickness of 0.1μ or less.

〔不純物の分析法〕[Impurity analysis method]

シール袋中に純水を入れ、その中に実験サンプル(本発
明品、従来品)を入れて加熱し、サンプルのウェハ表面
の不純物を純水中に溶かし、その純水を分析して不純物
の量を調べる マド法)。
Put pure water in a sealed bag, put the experimental sample (invention product, conventional product) in it, heat it, dissolve the impurities on the sample wafer surface in the pure water, and analyze the pure water to find out the impurities. (Mad method for determining quantity).

〔分析結果〕〔result of analysis〕

下記に示す表の通りである。 As shown in the table below.

(イオンクロ 以上の実験結果より明らかなように、従来品は破砕層が
残り、その破砕層に不純物が沢山入っているが、本発明
品は破砕層を除去し、クラック層3が残るだけであるた
め不純物の量は大幅に少なく高品位のシリコン基板が得
られる。
(As is clear from the experimental results of Ionchrome and above, the conventional product leaves a fractured layer and contains many impurities, but the product of the present invention removes the fractured layer and only crack layer 3 remains. Therefore, the amount of impurities is significantly reduced and a high-quality silicon substrate can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

図面は本発明の実施例を示し、第1図はラッピング後の
シリコンウェハを示す断面図1.第2図はエツチング化
と拡散後のエッチピット密度及び析出物密度の関係を示
す線図である。 図中、 1 : シリコンウェハ :破砕層
The drawings show an embodiment of the present invention, and FIG. 1 is a cross-sectional view showing a silicon wafer after lapping. FIG. 2 is a diagram showing the relationship between etch pit density and precipitate density after etching and diffusion. In the figure, 1: Silicon wafer: fracture layer

Claims (1)

【特許請求の範囲】[Claims]  ラッピング後のシリコンウェハを片面で0.5〜1.
5μmエッチング処理してなることを特徴とするディス
クリート素子用シリコン基板。
The silicon wafer after lapping is 0.5~1.
A silicon substrate for discrete devices characterized by being etched by 5 μm.
JP8346690A 1990-03-30 1990-03-30 Silicon substrate for discrete device Expired - Fee Related JP2541680B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8346690A JP2541680B2 (en) 1990-03-30 1990-03-30 Silicon substrate for discrete device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8346690A JP2541680B2 (en) 1990-03-30 1990-03-30 Silicon substrate for discrete device

Publications (2)

Publication Number Publication Date
JPH03283532A true JPH03283532A (en) 1991-12-13
JP2541680B2 JP2541680B2 (en) 1996-10-09

Family

ID=13803247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8346690A Expired - Fee Related JP2541680B2 (en) 1990-03-30 1990-03-30 Silicon substrate for discrete device

Country Status (1)

Country Link
JP (1) JP2541680B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06349795A (en) * 1993-06-08 1994-12-22 Shin Etsu Handotai Co Ltd Manufacture of semiconductor wafer
EP0945530A1 (en) * 1998-03-26 1999-09-29 Naoetsu Electronics Company A production method for a discrete structure substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06349795A (en) * 1993-06-08 1994-12-22 Shin Etsu Handotai Co Ltd Manufacture of semiconductor wafer
EP0945530A1 (en) * 1998-03-26 1999-09-29 Naoetsu Electronics Company A production method for a discrete structure substrate
US6093648A (en) * 1998-03-26 2000-07-25 Naoetsu Electronics Company Production method for a discrete structure substrate

Also Published As

Publication number Publication date
JP2541680B2 (en) 1996-10-09

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