JPH03283195A - Sample and hold circuit - Google Patents

Abstract

PURPOSE:To attain a high speed operation by feeding back the output of an emitter follower to the base of a second transistor in a first differential circuit through a first resistance and inputting an input signal through a second resistance. CONSTITUTION:A circuit operates as an inversion amplifier by a pair of differential transistors 1 and 2, a current mirror circuit consisting of transistors 8 and 9, transistors 3, 10, 4 and 7, constant current sources 31, 32 and 33 and resistances 50 and 51 both of which respectively have resistance values Rs and Rf. Namely, the output of the emitter follower is fed back to the base of the second transistor 8 of the first differential circuit 1 through the first resistance 50 and the input signal is inputted through the second resistance 52. Thus, the high speed operation can stably be executed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a sample and hold circuit, and in particular has a function of sampling and holding the instantaneous value of an analog signal, handles high-speed analog signals, and is suitable for integrated circuits. Regarding sample and hold circuits suitable for.

[Conventional technology]

As a conventional sample-and-hold circuit of this type, there is a circuit as shown in FIG.

In FIG. 4, the sample and hold circuit of the present invention includes transistors 1 to 8, diodes 21 to 24, constant current sources 31 to 34, input terminal 11, output terminal 12, and control input terminals 13 and 14. We are prepared.

Sample and hold control input terminals 13 and 14 (normally, input terminal 14 has a phase of 180° with respect to input terminal 13)
°The control input signals (SH, SH) of the inverted inputs of different rectangular waves are each in a high level state “H”.
Low level state “L” (hereinafter simply referred to as “H” and “L”)
”), the differential transistor pair 4, 5
Of the differential transistor pair 6, 7, transistors 4, 7 are both in a conductive state, transistors 5, 6 are both in a cut-off state, and the state of this circuit is in a sample mode.

That is, the analog input signal V input from the input terminal 11
ln is applied to the base of transistor 1, and transistor 1 operates as an emitter follower. transistor 1
The diodes 21, 22, and 23 connected to the emitters operate as a level shift circuit, and the current is supplied by a constant current source 34. Assuming that the base-emitter voltage of transistor 1 is VBEI and the forward voltages V of diodes 21, 22, and 23 are all equal, the voltage applied to the base of transistor 20 is [V +,,\sz+
+3 Vn] and Naru. A current obtained by adding the current of the constant current source 34 and the operating current of the transistor 1 becomes the current of the constant current source 31 via the transistor 4. The transistor 2 with a hold capacitor 40 connected to its emitter and operating as an emitter follower is shown above [vlfi-VBE1+3VD]
The receiving capacity 40 is charged based on the voltage of . If the voltage between the base and emitter of the transistor 20 at this time is vB8□, the potential of the capacitor 40 becomes [V +, (VBx+ + V
nl2) +3VD], and the potential follows the input voltage (2) by being level-shifted by C3VD (VBEI1 +VBE2)).

Further, as shown in FIG. 4, an emitter follower circuit consisting of a transistor 8 whose base is connected to the emitter of the transistor 2 and a constant current 33 is connected, and an output signal v0 is output from the emitter of the transistor 8, that is, the output terminal 2.
When the base-emitter voltage of transistor 8 is VBxa'), CCV, =
V + - (VBIII + VB+!2 +VBxi
) + 3 Vnl. Here, transistor 1.
If the current densities of the elements 2, 8 and diodes 21, 22, and 23 are set to be equal, [V, 10Vnz2+
Vnxs#3 Vn), resulting in CV
,, average Vゎ]. That is, in the sample mode, the output signal V0 is the input signal V; will follow equally.

Next, when the signals SH and SR are 'L' and '■', both the transistors 4 and 7 are cut off, and the transistors 5 and 6 are both turned on, and the circuit enters the hold mode. That is, Since the transistor 7.2 is cut off, the charging operation of the capacitor 4o is stopped, and the base is connected to the capacitor 4o.
The transistor 3 connected to one end other than the ground side of the capacitor 40 starts operating, and the value of the potential [V, , +Vゎ] of the capacitor 40 is maintained. At this time, the current of the constant current sources 31 and 32 is supplied from the constant current source 34 via the diode 24 and the transistors 5 and 6, and from the power supply line 15 via the transistor 3.5.6. As stated above,
In sample mode, input signal V and output signal v
0 follows (v, = v + n) and the response switches to hold mode, the input signal V1. ．． The function of the sample and hold circuit is to hold the instantaneous value of .

[Problem to be solved by the invention]

In the conventional sample-and-hold circuit described above, in the hold mode, the output signal V is caused by the bias current (base current) IB of the transistor connected to the hold capacitor 40. shows a so-called droop characteristic in which the ratio of In/Cm gradually decreases.

On the other hand, when handling high-speed input signals, it is generally necessary to set the operating current of the element to a large value, and the bias current also becomes large, so in the conventional example shown in Figure 4, the droop becomes large. If it becomes too much, the sample and hold circuit loses its original holding function.

Furthermore, in order to reduce droop, a junction field effect transistor or a transistor with a large current amplification factor is often used as the transistor connected to the hold capacitor 40 with the intention of reducing the bias current factor 3; In addition to the standard integrated circuit manufacturing process, this requires a process to simultaneously fabricate the specialized transistors mentioned above, making the process complex and expensive just to address this droop problem. The inconvenience of becoming a thing arises.

Furthermore, there are cases in which circuit techniques such as using a Darlington connection type for the transistor connected to the capacitor 40 or newly providing a bias current compensation circuit, and cases in which the transistor connected to the capacitor 40 is
Although they do not require complex and expensive integrated circuit fabrication processes, such as increasing the value of This results in a problem that the circuit response cannot follow the current.

SUMMARY OF THE INVENTION An object of the present invention is to provide a sample-and-hold circuit which overcomes the above-mentioned drawbacks, has a simple manufacturing process, has a good sample-and-hold operation function, and is capable of high-speed operation.

[Means to solve the problem]

The sample and hold circuit of the present invention includes a current mirror circuit, a first transistor whose base is biased to a constant voltage and whose collector is connected to a diode-type connection point of the current mirror circuit, and whose collector is the output of the current mirror circuit. a first differential circuit having a second transistor connected to a point; and a third transistor having a base connected to the output point of the current mirror circuit, a collector connected to a power supply, and an emitter connected to a hold capacitor. ,
7 a diode element consisting of a single or plural diodes or diode-connected transistors whose node side is connected to the common emitter of the first differential circuit and whose cathode side is connected to the output point of the current mirror circuit;
a second differential circuit having a fourth transistor whose collector is connected to the common emitter of the first differential circuit; and a fifth transistor whose collector is connected to the output point of the current mirror circuit; a third differential circuit having a sixth transistor having a collector connected to the power supply and a seventh transistor having a collector connected to the emitter of the third transistor; and a base receiving the voltage of the hold capacitor. and an operative emitter follower, the pressure of the emitter follower being applied to the second differential circuit of the first differential circuit.
It is characterized in that an input signal is fed back to the base of the transistor via the first resistor and is input via the second resistor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a sample and hold circuit according to a first embodiment of the present invention. In FIG. 1, the sample hold circuit of this embodiment includes transistors 1 to 10, a diode 21, a constant current source 31°32.33, and a capacitor 40.
, a resistor 50.51, a control input terminal 13.14, an input terminal 11, an output terminal 12, and a power supply line 15.16.

Now, the input signals SH and SR of the sample hold control input terminal 13 and its inverted input terminal 14 are "
When the state of H"L", that is, the state of this sample and hold circuit is in sample mode, transistor 4 of differential transistor pair 4, 5 and differential transistor pair 6, 7
, 7 are both in a conductive state, and both transistors 5 and 6 are in a cut-off state.

In this case, this circuit includes a differential transistor pair 1.2, a current mirror circuit consisting of transistors 8 and 9, transistors 3, 10, 4.7, and constant current sources 31, 32.3.
3, and a resistor 50.5 having resistance values R= and Rr, respectively.
1, it operates as an inverting amplifier. Input signal Vl
n and output signal■. and CRt-R1:l], then (
: V, = V l fi) and tx F), gain [
-1] operates as an inverting amplifier.

When the signals SH and SH are "L" and "H" respectively,
That is, when transistors 4 and 7 are both cut off and transistors 5 and 6 are both turned on, the circuit enters the hold mode. In the sample mode, the transistor 3, which operates as an emitter follower and charges and discharges the capacitor 40, becomes cut off due to conduction of the diode 21, stops charging and discharging, and the instantaneous value of the potential of the capacitor 40 is held. . At this time, the condition for turning off transistor 3 is that the voltage between the base and emitter of transistors 1, 3, and 10 is Vsz+y Vszz, respectively.

V. and the forward voltage of diode 21 is ■.

Assuming that (V.+V1v+o+Vi+ms=
Vl, +VBEIO+VBE3>Vl, VBP! l
VD]. Therefore, (Vi+g++VBx3+
It is sufficient if Vnx+o+Vn>2・Vl,). For example, when [vl, , = 2 [■]], the direction of the inequality is reversed, but in this case, it is sufficient to connect as many diodes 21 as necessary.

In the hold mode, the operating currents of the transistors 5 and 6 in the conductive state are such that for transistor 5, the current of transistor 8 passes through the diode 21, and that of transistor 9 passes through the diode 21, and for transistor 6, the current flows through the power supply line. 15.

In the above description, it is assumed that CRt = R, :], but it is of course possible to use [Rf #R= ) with a gain other than [-1] in the sample mode.

In the first embodiment shown in FIG. 1, assuming that the leakage current of the hold capacitor 40 is negligible, and assuming that the current amplification factor of the transistor 8 is hyx, in the droop play example, the current amplification factor of the transistors 3 and 8 is C8], so let's assume that the values of each constant current source 31, 32.33 are CI I = I
2 = I + 3. I l = 2・I4], then [dV--5・-E-! -/CH:l becomes dthpx. The droop plate of the embodiment shown in FIG. 1 can significantly reduce the droop plate compared to 215 of the conventional example. Here, the capacitance value of the capacitor 40 is assumed to be CT1.

FIG. 2 is a circuit diagram of a sample and hold circuit according to a second embodiment of the present invention. In FIG. 2, the sample and hold circuit of this embodiment is a circuit in which resistors 52 and 53 are added to the circuit of FIG. 1.

Other parts are the same as in FIG. In this embodiment, due to the influence of the potential drop of the power supply line 15, the differential transistor pair 1, 2
In order to prevent the balance from being upset, resistors 52 and 53 are added.

FIG. 3 is a circuit diagram showing a sample and hold circuit according to a third embodiment of the present invention. In FIG. 3, the sample-and-hold circuit of this embodiment solves the problem between the base and collector of transistor 8 in FIG. to add. Other circuit parts are the same as in FIG. 2.

In this embodiment, a transistor Q21 is added to improve the balanced state of the differential transistor pair 1 and 2.

Above is the first aspect of the present invention. Second. According to the third embodiment, switching between the sample mode and the hold mode is performed using a circuit in which the operating current is controlled by a differential switch,
The operating current of one differential transistor pair in the hold mode is supplied by the input current of the current mirror circuit through the diode switch and the output current of the current mirror circuit, and the operating current of the other differential transistor pair is By supplying power directly from the power supply line, the hold capacitor charging transistor is cut off and droop caused by bias current is eliminated.

〔Effect of the invention〕

As explained above, according to the present invention, especially when considering integrated circuits, it is possible to simultaneously fabricate special elements such as junction field effect transistors without impairing tracking speed during sampling. There is no need for a complicated or expensive integrated circuit manufacturing process, and the retention characteristic can be improved by more than twice that of conventional circuits using a standard manufacturing process.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a sample hold circuit according to a first embodiment of the present invention, and FIGS.
．． A circuit diagram showing a sample hold circuit of a third embodiment,
FIG. 4 is a circuit diagram showing a conventional sample and hold circuit. 11...Input terminal, 12...Output terminal, 13°14...Control input terminal, 15.16.
...Power supply line, 1 to 10.60...Transistor, 21゜22.23.24...Diode, 40...Hold capacitance, 50,51, 5
2.53... Resistance, 31.32, 33.34.
... Constant current source.

Claims (1)

[Claims] a current mirror circuit; a first transistor whose base is biased to a constant voltage and whose collector is connected to a diode-type connection point of the current mirror circuit; and a second transistor whose collector is connected to an output point of the current mirror circuit; a first differential circuit having a base connected to the output point of the current mirror circuit, a third transistor having a collector connected to a power supply and an emitter connected to a hold capacitor, and a third transistor having an anode side connected to the first differential circuit; a diode element consisting of a single or a plurality of diodes or diode-connected transistors connected to a common emitter of the first differential circuit and whose cathode side is connected to the output point of the current mirror circuit; a second differential circuit having a fourth transistor connected to a common emitter, a fifth transistor having a collector connected to the output point of the current mirror circuit, and a sixth transistor having a collector connected to the power source. and a seventh transistor having a collector connected to the emitter of the third transistor, and an emitter follower whose base receives the voltage of the hold capacitor and operates, The output of the emitter follower is fed back to the base of the second transistor of the first differential circuit via the first resistor, and the input signal is input via the second resistor. Features a sample and hold circuit.