JPH03280441A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03280441A JPH03280441A JP2078823A JP7882390A JPH03280441A JP H03280441 A JPH03280441 A JP H03280441A JP 2078823 A JP2078823 A JP 2078823A JP 7882390 A JP7882390 A JP 7882390A JP H03280441 A JPH03280441 A JP H03280441A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pads
- area
- memory cell
- bonding
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000002184 metal Substances 0.000 claims 2
- 238000001259 photo etching Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明はボンディングパッドによりチップと外部との接
続を行う半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device in which a chip is connected to the outside by bonding pads.
（従来の技術）
通常半導体集積回路チップにはメモリセル部周辺回路部
等の周辺に円形および正方形を組み合わせた形状のボン
ディングパッドが複数個配置されそれぞれのボンディン
グパッドは引出し配線を有し集積回路チップの保護の為
に形成された絶縁性保護膜の窓から外面に露出し電気的
接続を可能としている。(Prior Art) Normally, a semiconductor integrated circuit chip has a plurality of bonding pads in a combination of circular and square shapes arranged around the memory cell, peripheral circuit, etc., and each bonding pad has a lead wire, and the integrated circuit chip It is exposed to the outside through the window of the insulating protective film formed to protect the electrical connection.
近年集積回路の高集積化に伴いメモリセル部の面積が増
し全体のチップ面積は大きくなる。これにより半導体集
積回路チップを接続するパッケージも大きくなる。パッ
ケージが大きくなることにより実装デザインの変更を必
要゛とされる場合がある。この為半導体集積回路チップ
の集積度が増しても同一パッケージに接続できるように
１個のメモリセル面積を減少させ、−メモリセル部全体
の面積を小さくする。これにより配線パターンは細くサ
ブミクロンからハーフミクロンの線幅となってきている
為、配線パターンを形成するホルトエツチング工程では
超微細によりパターン形成できない問題が生じる。In recent years, as integrated circuits have become more highly integrated, the area of memory cell portions has increased and the overall chip area has become larger. This also increases the size of the package to which the semiconductor integrated circuit chip is connected. As the package becomes larger, it may be necessary to change the implementation design. Therefore, even if the degree of integration of semiconductor integrated circuit chips increases, the area of one memory cell is reduced so that they can be connected to the same package, and - the area of the entire memory cell section is reduced. As a result, wiring patterns have become thinner and have line widths ranging from sub-micron to half-micron, resulting in the problem that patterns cannot be formed due to ultra-fineness in the hole etching process for forming wiring patterns.
また１以上の問題を解決する為にメモリセル部の面積を
十分に与えるためボンディングパッド部の面積を小さく
することが試みられているがその結果ボンディングワイ
ヤの接続強度は十分でなく或いは接触抵抗が高くなり信
頼性や特性の面で問題が生じる。In addition, in order to solve one or more problems, attempts have been made to reduce the area of the bonding pad part in order to provide a sufficient area for the memory cell part, but as a result, the connection strength of the bonding wire is not sufficient or the contact resistance is high. This causes problems in terms of reliability and characteristics.
（発明が解決しようとする課Ｍ）
以上のように半導体集積回路ではメモリセル部面積の増
大を防ぐ為配線パターン幅を超微細によりパターン形成
できない問題が生じてきている。(Problem M to be Solved by the Invention) As described above, in semiconductor integrated circuits, a problem has arisen in which it is not possible to form patterns by making the wiring pattern width ultra-fine in order to prevent an increase in the area of the memory cell portion.
又、メモリセル部面積を十分に与える為ボンディングパ
ッドの面積縮小により機械的な或いは電気的なボンディ
ング特性に問題が生じてきている。Furthermore, problems have arisen in mechanical or electrical bonding characteristics as the area of the bonding pad is reduced in order to provide a sufficient area for the memory cell portion.
本発明はこの様な問題を解決してボンディングパッドの
面積を減少させずにメモリセル部の面積増加を実現した
半導体装置を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that solves these problems and increases the area of a memory cell portion without reducing the area of a bonding pad.
（課題を解決するための手段）
本発明にかかる半導体装置は素子形成された半導体チッ
プのボンディングパッドをメモリセル領域内に多層構造
により形成することを特徴とする。(Means for Solving the Problems) A semiconductor device according to the present invention is characterized in that bonding pads of a semiconductor chip on which elements are formed are formed in a memory cell region in a multilayer structure.
（作 用）
ボンディングパッド面をメモリセル領域内に集積構造に
よって設けることによりボンディングパッド面積をチッ
プ面積から除くことができる。(Function) By providing the bonding pad surface within the memory cell region using an integrated structure, the bonding pad area can be removed from the chip area.
これにより、メモリセル部の面積を大きくすることによ
り配線パターンの微細化を防ぐことができる。又、ボン
ディングワイヤとポンプイングツ（ラドの接合面積を大
きくすることができる。従ってボンディングパッド材料
ボンディング性に拘らず十分なボンディング接続強度を
得ることができる。Thereby, by increasing the area of the memory cell portion, miniaturization of the wiring pattern can be prevented. Furthermore, the bonding area between the bonding wire and the pumping wire can be increased. Therefore, sufficient bonding connection strength can be obtained regardless of the bonding properties of the bonding pad material.
（実施例）
以下、本発明の実施例を図面を参照して説明する。第１
図は、実施例の半導体素子のボンディング接続部の構造
を示す断面図である。多数の素子が集積形成された半導
体チップ■のＭＯＳ ＦＥＴを構成するゲート電極２
上にＳｉｏ２やＰＳＧ等の絶縁膜３を形成する。チップ
周辺の絶縁膜上にＦＥＴの拡散層４へ接続されるアルミ
ニウム配線５と同時にボンディングパッドと接続される
電極６を形成する。このアルミニウムの配線５．電極６
形成後、Ｓｉｏ、やＰＳＧ等の２層目の絶縁膜７が形成
され、電極６部分のみホ＊トエッチングによりコンタク
トホール８を形成する。次にスパッタ法により２層目の
１２膜を形成しホ叡トエッチングによりボンディングパ
ッド９が形成される。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a cross-sectional view showing the structure of a bonding connection part of a semiconductor element of an example. Gate electrode 2 constituting a MOS FET of a semiconductor chip (■) in which a large number of elements are integrated
An insulating film 3 such as Sio2 or PSG is formed thereon. An aluminum wiring 5 connected to the diffusion layer 4 of the FET and an electrode 6 connected to the bonding pad are formed on the insulating film around the chip. This aluminum wiring5. Electrode 6
After the formation, a second layer insulating film 7 such as Sio, PSG, etc. is formed, and contact holes 8 are formed by photo-etching only the electrode 6 portions. Next, a second layer of 12 films is formed by sputtering, and bonding pads 9 are formed by photo etching.
これによりワイヤｌＯを電極パッドに接続する。This connects the wire IO to the electrode pad.
第２図は上記実施例を用いた半導体集積回路チップの平
面図を示す、１は半導体集積回路チップである。コンタ
クトホール８から引き出し配線１１を有しメモリセル部
１２領域内にボンディングパッド９が形成されている。FIG. 2 shows a plan view of a semiconductor integrated circuit chip using the above embodiment. Reference numeral 1 indicates the semiconductor integrated circuit chip. A bonding pad 9 is formed in the memory cell portion 12 region with a wiring 11 extending from the contact hole 8 .
この実施例によればボンディングパットの面積をなくす
ことによりメモリセル部の面積を大きくすることができ
る。これにより従来より１０膜程度の配線パターンを太
めることができる。又テストパターンを入れることやボ
ンディングワイヤとボンディングパッドの接合に要する
チップ上の面積は実質的に従来より大きくとることがで
きる。According to this embodiment, the area of the memory cell portion can be increased by eliminating the area of the bonding pad. As a result, the wiring pattern can be made thicker by about 10 layers than before. Further, the area on the chip required for inserting the test pattern and bonding the bonding wire and the bonding pad can be substantially larger than that of the conventional method.
以上述べたように本発明によれば、ボンディングパッド
をメモリセル領域内に多層構造で形成することによりメ
モリセル部の面積を大きくすること、また、ボンディン
グパッド面積を大きくしボンディングの接続強度を実現
した半導体装置を得ることができる。As described above, according to the present invention, the area of the memory cell part can be increased by forming the bonding pad in a multilayer structure within the memory cell area, and the bonding pad area can be increased to achieve bonding connection strength. A semiconductor device can be obtained.
第１図は本発明の実施例の一つのボンディング接続部の
構造を示す断面図、第２図は平面図である。
図において、
１・・半導体集積回路チップ、
２・・ゲート電極、 ３・・・絶縁膜、４・・・拡
散層、 ５・・・アルミニウム配線、６・・
電極、 ７・・・２層目の絶縁膜、８・・・
コンタクトホール。
９・・・ボンディングパッド。
１０・・・ワイヤ、 １１・・・引き出し
配線、１２・・・メモリセル部。FIG. 1 is a sectional view showing the structure of a bonding connection part according to an embodiment of the present invention, and FIG. 2 is a plan view. In the figure, 1. Semiconductor integrated circuit chip, 2. Gate electrode, 3. Insulating film, 4. Diffusion layer, 5. Aluminum wiring, 6.
Electrode, 7... Second layer insulating film, 8...
contact hole. 9...Bonding pad. DESCRIPTION OF SYMBOLS 10... Wire, 11... Leading wiring, 12... Memory cell part.
Claims (2)
ィングパッドが素子上に形成されたことを特徴とする半
導体装置。(1) A semiconductor device characterized in that a bonding pad formed on a semiconductor chip on which an element is formed is formed on the element.
成された第１の絶縁膜と、第１の電極部に形成されたコ
ンタクトホールを通して接続され素子上に延長する、ボ
ンディングパッドを構成する金属膜よりなる第２の電極
とを備えたことを特徴とする請求項１記載の半導体装置
。(2) Bonding that connects a first electrode made of a metal film, a first insulating film formed on the first electrode, and a contact hole formed in the first electrode portion and extends over the element. 2. The semiconductor device according to claim 1, further comprising a second electrode made of a metal film constituting a pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2078823A JPH03280441A (en) | 1990-03-29 | 1990-03-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2078823A JPH03280441A (en) | 1990-03-29 | 1990-03-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03280441A true JPH03280441A (en) | 1991-12-11 |
Family
ID=13672554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2078823A Pending JPH03280441A (en) | 1990-03-29 | 1990-03-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03280441A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5834849A (en) * | 1996-02-13 | 1998-11-10 | Altera Corporation | High density integrated circuit pad structures |
-
1990
- 1990-03-29 JP JP2078823A patent/JPH03280441A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5834849A (en) * | 1996-02-13 | 1998-11-10 | Altera Corporation | High density integrated circuit pad structures |
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