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JPH03280420A - Method for manufacturing semiconductor thin film - Google Patents

Method for manufacturing semiconductor thin film

Info

Publication number
JPH03280420A
JPH03280420A JP2081625A JP8162590A JPH03280420A JP H03280420 A JPH03280420 A JP H03280420A JP 2081625 A JP2081625 A JP 2081625A JP 8162590 A JP8162590 A JP 8162590A JP H03280420 A JPH03280420 A JP H03280420A
Authority
JP
Japan
Prior art keywords
thin film
layer
glass substrate
tin
film layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2081625A
Other languages
Japanese (ja)
Other versions
JPH0760807B2 (en
Inventor
Takeshi Saito
毅 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
G T C KK
GTC Corp
Original Assignee
G T C KK
GTC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by G T C KK, GTC Corp filed Critical G T C KK
Priority to JP8162590A priority Critical patent/JPH0760807B2/en
Publication of JPH03280420A publication Critical patent/JPH03280420A/en
Publication of JPH0760807B2 publication Critical patent/JPH0760807B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To make it possible to form a thin film, having large crystal diameter and excellent crystallinity, on a substrate having a large area by a method wherein a silicon thin film layer is formed on a glass substrate, and after the paste, which is formed by dispersing tin fine particles into an organic solvent, has been applied on the silicon thin film layer, the glass substrate is heated up to 232 deg.C or higher, and then the substrate is slowly cooled down. CONSTITUTION:The surface of a glass substrate having smooth surface is cleaned, and a silicon thin film layer 2 is formed thereon. Then the paste, formed by dispersing tin fine particles, is applied on the layer 2, and a tin-coated layer 3 is formed in matrix form. Then, the glass substrate 1 is heat-treated at 232 deg.C or higher, and a matrix-shaped melt layer 4 is formed. Subsequently, the above material is slowly cooled down, and a polysilicon thin film layer 5 is formed in the silicon thin film 2 in matrix form. The above-mentioned polysilicon thin film layer 5 is grown using the crystal, deposited on the surface of the melt layer 4, as a nucleus, the layer 5 has large crystal grain diameter and also has excellent crystallinity.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は半導体薄膜の製造方法、詳しくは大面積のガ
ラス基板上にポリシリコンの結晶薄膜を形成する方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor thin film, and more particularly to a method for forming a polysilicon crystal thin film on a large-area glass substrate.

[従来技術とその課題] 液晶デイスプレィ等の表示素子の駆動方法として種々の
ものがあるが、なかでもマトリクス方式は高画質化、大
表示容量化が可能なことから近年、注目を集めている。
[Prior Art and Its Issues] There are various methods for driving display elements such as liquid crystal displays, and among them, the matrix method has been attracting attention in recent years because it allows for high image quality and large display capacity.

この方式は、透明なガラス基板上に半導体薄膜を形成し
、この半導体薄膜中にマトリクス状に薄膜ダイオードや
薄膜トランジスタ等のスイッチング素子を配列してなる
基板を作成し、スイッチング素子によって各画素となる
液晶セルを直接駆動するものである。
In this method, a semiconductor thin film is formed on a transparent glass substrate, and switching elements such as thin film diodes and thin film transistors are arranged in a matrix in this semiconductor thin film to create a substrate. It directly drives cells.

第9図は、スイッチング素子として薄膜トランジスタ1
0を用いたマトリクス駆動型液晶デイスプレィの等価回
路を示したものである。第9図中、符号11・・は走査
線、符号12・・は信号線、符号13・・・は液晶セル
である。そして各走査線+1と信号線12とによって区
画された部分に、スイッチング素子としての薄膜トラン
ジスタlOと、それに接続された液晶セル13とを、そ
れぞれ配設して液晶デイスプレィの一画素か構成されて
いる。
FIG. 9 shows a thin film transistor 1 as a switching element.
This figure shows an equivalent circuit of a matrix-driven liquid crystal display using 0. In FIG. 9, numerals 11, . . . are scanning lines, numerals 12, . . . are signal lines, and numerals 13, . . . are liquid crystal cells. A thin film transistor 10 as a switching element and a liquid crystal cell 13 connected thereto are respectively disposed in a portion divided by each scanning line +1 and signal line 12, thereby forming one pixel of a liquid crystal display. .

このような液晶デイスプレィの等価回路は、透明なガラ
ス基板上に形成された半導体薄膜中に形成される。この
半導体薄膜の材料としては、プラズマCVD法による水
素化アモルファスシリコン薄膜が主に用いられる。これ
はプラズマCVD法によれば、対角の大きさが数インチ
程度で、走査線11および信号線12が各々数百本、全
画素数が数十五個程度の液晶デイスプレィの基板となる
大面積のアモルファスシリコン薄膜をガラスの軟化点以
下の低温で形成が可能であるためである。
The equivalent circuit of such a liquid crystal display is formed in a semiconductor thin film formed on a transparent glass substrate. As a material for this semiconductor thin film, a hydrogenated amorphous silicon thin film produced by a plasma CVD method is mainly used. According to the plasma CVD method, this is a large substrate for a liquid crystal display with a diagonal size of about several inches, several hundred scanning lines 11 and signal lines 12, and a total number of pixels of about several dozen. This is because an amorphous silicon thin film with a large area can be formed at a low temperature below the softening point of glass.

ところで近年、大画面のデイスプレィへの要求か高まり
つつあるが、走査線Ifと信号線12とが各々千木以上
で全画素数が数百五個以上にも達する大画面の液晶デイ
スプレィを製造するには、キャリア移動度が大きな半導
体薄膜中に、スイッチング速度の高い薄膜トランジスタ
IOを製造する必要がある。
By the way, in recent years, the demand for large-screen displays has been increasing, and it is now possible to manufacture large-screen liquid crystal displays in which the scanning line If and the signal line 12 are each more than 1,000 gi, and the total number of pixels is several hundred and five or more. To achieve this, it is necessary to manufacture a thin film transistor IO with high switching speed in a semiconductor thin film with high carrier mobility.

ところが上記水素化アモルファスシリコン薄膜は、キャ
リア移動度が高々Icm’/vsと小さいので、スイッ
チング速度の向上に限界かある。よってキャリア移動度
かより大きなポリノリコン薄膜を用いることが提案され
ている。
However, since the hydrogenated amorphous silicon thin film has a small carrier mobility of at most Icm'/vs, there is a limit to the improvement in switching speed. Therefore, it has been proposed to use a polynolycon thin film with higher carrier mobility.

このポリシリコン薄膜は、LPCVD法(LowPre
ssure Che+n1cal Vapor Dep
osition)やレーザアニール法によって形成でき
る。
This polysilicon thin film is produced using the LPCVD method (Low Pre
ssure Che+n1cal Vapor Dep
It can be formed by a laser annealing method or a laser annealing method.

LPCVD法は、シランガスを原料として加熱されたガ
ラス基板上に直接ポリシリコン薄膜を形成する方法であ
る。ところが薄膜形成温度をガラスの軟化点以上にする
ことができないので、このLPCVD法ではポリシリコ
ン薄膜の結晶粒を十分に成長させることができない。半
導体薄膜のキャリア移動度は、結晶粒径の大きさとその
結晶性に依存しているので、LPCVD法によるポリシ
リコン薄膜のキャリア移動度もアモルファス薄膜のIO
倍程度が限界であった。
The LPCVD method is a method of directly forming a polysilicon thin film on a heated glass substrate using silane gas as a raw material. However, since the thin film forming temperature cannot be made higher than the softening point of glass, the crystal grains of the polysilicon thin film cannot be sufficiently grown using this LPCVD method. Since the carrier mobility of a semiconductor thin film depends on the size of crystal grains and its crystallinity, the carrier mobility of a polysilicon thin film produced by LPCVD is also similar to that of an amorphous thin film.
The limit was about double that.

一方、レーザアニール法は、ガラス基板上に予め形成さ
れた半導体薄膜にレーザ光を照射して溶融再結晶化させ
る方法であるため、結晶性の良L)結晶粒を十分に成長
させることができる。このためキャリア移動度を100
 cm’/ vs以上にすることかでき、画素数か数百
万個に達する液晶デイスプレィの駆動に十分なスイッチ
ング速度の素子を形成できる。しかしながらこのレーザ
アニール法は、各画素に対応してレーザ光を照射するの
で、たとえ一画素あ1こりの処理時間か1秒たとしても
数百万個の画素を有する基板を処理するには膨大な時間
を要するので、量産に適さないという問題があった。
On the other hand, the laser annealing method is a method in which a thin semiconductor film formed in advance on a glass substrate is irradiated with laser light to melt and recrystallize it, so it is possible to sufficiently grow L) crystal grains with good crystallinity. . Therefore, carrier mobility is reduced to 100
cm'/vs or higher, and an element with a switching speed sufficient for driving a liquid crystal display with several million pixels can be formed. However, this laser annealing method irradiates laser light corresponding to each pixel, so even if the processing time is 1 second for each pixel, it takes a huge amount of time to process a substrate with millions of pixels. Since it takes a long time, there is a problem that it is not suitable for mass production.

この発明は上記課題を解決するためになされ几ものであ
って、大面積のガラス基板上に結晶粒径が大きく、かつ
結晶性の良好なポリノリコン薄膜をマトリクス状に高ス
ループツトで形成する方法を提供することを目的として
いる。
This invention has been made to solve the above problems, and provides a method for forming a polynolycon thin film with large crystal grain size and good crystallinity in a matrix shape on a large-area glass substrate with high throughput. It is intended to.

5課題を解決するための手段〕 この発明の請求項1記載の半導体薄膜の製造方法は、カ
ラス基板上にノリコン薄膜層を形成し、スズ微粒子を有
機溶媒に分散させてなるペーストを上記シリコン薄膜層
上に塗布し1こ後、このガラス基板を232°C以上に
加熱した後、徐冷することを解決手段とし、さらにこの
発明の請求項2記載の製造方法は、スズ微粒子を有機溶
媒に分散させでなるペーストをシリコン薄膜層上にマト
リクス状に塗布することを解決手段とした。
Means for Solving 5 Problems] The method for manufacturing a semiconductor thin film according to claim 1 of the present invention includes forming a Noricon thin film layer on a glass substrate, and applying a paste made by dispersing tin fine particles in an organic solvent to the silicon thin film. The solution is to heat the glass substrate to 232° C. or higher and then slowly cool it after coating the layer. The solution was to apply a dispersed paste on a silicon thin film layer in a matrix.

1作用 ] スズを有機溶媒中に分散してなるペーストをシリコン薄
膜上に塗布した後、加熱すると、ペーストか塗布された
部分においてシリコン−スズの二元合金の融液層が形成
される。ついでこれを徐冷すると、ガラス基板よりも熱
伝導率の大きな融液層側から冷却されるので、融液層の
表面からガラス基板側へ向ってノリコンの結晶を成長さ
せることができる。
1 Effect] When a paste made by dispersing tin in an organic solvent is applied onto a silicon thin film and then heated, a melt layer of a silicon-tin binary alloy is formed in the area where the paste is applied. When this is then slowly cooled, it is cooled from the melt layer side, which has a higher thermal conductivity than the glass substrate, so that Noricon crystals can be grown from the surface of the melt layer toward the glass substrate side.

以下、この発明の詳細な説明する。The present invention will be explained in detail below.

この発明の半導体薄膜の製造方法は、■ガラス基板上に
ノリコン薄膜を形成する基板形成工程と、■上記ノリコ
ノ薄膜上にペーストを塗布する塗布工程と、■ペースト
が塗布され1こ基板を加熱する加熱工程と、■加熱され
た基板を徐冷する冷却工程とからなるものである。
The method for manufacturing a semiconductor thin film of the present invention includes: (1) a substrate forming step of forming a Noricon thin film on a glass substrate, (2) a coating step of applying a paste on the Noricon thin film, and (2) heating the substrate on which the paste is applied. This process consists of a heating process and (2) a cooling process in which the heated substrate is slowly cooled.

以下、工程順に説明する。The steps will be explained below in order.

第1図ないし第5図は、この発明の製造方法を工程順に
示したものである。
1 to 5 show the manufacturing method of the present invention in the order of steps.

■基板形成工程 まず第1図に示したように、表面が平滑なガラス基板l
を用意する。このガラス基板lを洗剤および酸の水溶液
で順次洗浄して、表面を清浄にする。
■Substrate forming process First, as shown in Figure 1, a glass substrate l with a smooth surface is used.
Prepare. This glass substrate 1 is sequentially washed with detergent and acid aqueous solutions to clean the surface.

ついでこのガラス基板l上に、第2図に示したように、
シリコン薄膜層2を1〜2μ會の膜厚にて形成する。こ
のシリコン薄膜層2は、アモルファスシリコン薄膜とポ
リシリコン薄膜のいずれであっても良い。このようなシ
リコン薄膜層2はプラズマCVD法やLPCVD法等の
公知手段によって形成するとかできる。
Then, as shown in FIG. 2, on this glass substrate l,
A silicon thin film layer 2 is formed to a thickness of 1 to 2 μm. This silicon thin film layer 2 may be either an amorphous silicon thin film or a polysilicon thin film. Such a silicon thin film layer 2 can be formed by a known method such as a plasma CVD method or an LPCVD method.

■塗布工程 次に第3図に示したように、シリコン薄膜層2上にスズ
塗布層3をマトリクス状に形成する。
(2) Coating process Next, as shown in FIG. 3, a tin coating layer 3 is formed in a matrix on the silicon thin film layer 2.

このようなスズ塗布層3を形成するには、粒径1μm以
下のスズ微粒子をポリビニルアルコール等の有機溶媒中
に分散させてなるペーストを、凸版印刷法、凹版印刷法
、スクリーン印刷法等の各種印刷法等によって塗布する
方法を好適に用いることができる。印刷法と塗布条件と
は、ペーストの厚さの制御性、各マトリクスに対応する
パターン形成能力、大面積基板上への塗布領域の位置制
御性等によって適宜選択することができる。またスズ塗
布層3のパターンおよびそのピッチは、スズ塗布層3が
溶融した際に周囲に広がることを考慮して、隣接したス
ズ塗布層3.3が互いに接触しないように設定する必要
がある。
In order to form such a tin coating layer 3, a paste made by dispersing fine tin particles with a particle size of 1 μm or less in an organic solvent such as polyvinyl alcohol is processed by various methods such as letterpress printing, intaglio printing, and screen printing. A coating method such as a printing method can be suitably used. The printing method and coating conditions can be appropriately selected depending on the controllability of the thickness of the paste, the ability to form patterns corresponding to each matrix, the controllability of the position of the coating area on the large-area substrate, and the like. Further, the pattern of the tin coating layer 3 and its pitch must be set so that adjacent tin coating layers 3.3 do not come into contact with each other, taking into consideration that the tin coating layer 3 will spread to the surrounding area when melted.

なお第3図に示した例にあっては、スズ塗布層3を、シ
リコン薄膜層2上にマトリクス状に塗布したが、この発
明の製造方法はこの例に限られるものではなく、シリコ
ン薄膜層2の全面にスズ塗布層3を形成しても良い。
In the example shown in FIG. 3, the tin coating layer 3 is coated on the silicon thin film layer 2 in a matrix, but the manufacturing method of the present invention is not limited to this example. The tin coating layer 3 may be formed on the entire surface of the substrate 2.

■加熱工程 次にスズ塗布層3が形成されたガラス基板lに加熱処理
を施す。この加熱工程は、ノリコン薄膜層2とスズ塗布
層3とを加熱して、シリコン−スズ二元合金の融液層4
を形成するためのものである。この工程は後述する■冷
却工程と連続してたとえば窒素等の不活性雰囲気に保た
れた電気炉中にて行うことができる。
(2) Heating process Next, the glass substrate l on which the tin coating layer 3 has been formed is subjected to a heat treatment. In this heating step, the Noricon thin film layer 2 and the tin coating layer 3 are heated, and the silicon-tin binary alloy melt layer 4 is heated.
It is intended to form a This step can be carried out in succession with the cooling step (1) to be described later, for example, in an electric furnace maintained in an inert atmosphere such as nitrogen.

電気炉を用いた場合の加熱−冷却の温度条件の一例を第
6図に示した。昇温はガラス基板lに熱歪が発生しない
ように+10℃/分程度の緩やかなものであって、シリ
コンとスズとの二元合金が融解する温度T以上に加熱す
る。この温度Tは第7図より求めることができる。
An example of heating-cooling temperature conditions when an electric furnace is used is shown in FIG. The temperature is raised slowly at about +10° C./min so as not to cause thermal distortion in the glass substrate 1, and is heated to a temperature T at which the binary alloy of silicon and tin melts. This temperature T can be determined from FIG.

第7図は、シリコン(S i)とスズ(Sn)との二元
合金の状態図である。第7図より明らかなように、スズ
リッチの二元合金融液においては、232℃でシリコン
の固相すなわち結晶が析出するので、この加熱工程にお
ける昇温下限は232℃以上、上限はガラスの軟化点未
満とする。
FIG. 7 is a phase diagram of a binary alloy of silicon (Si) and tin (Sn). As is clear from Figure 7, in the tin-rich binary alloy liquid, the solid phase of silicon, that is, crystals, precipitates at 232°C, so the lower limit of temperature increase in this heating step is 232°C or higher, and the upper limit is the softening of the glass. less than a point.

そしてこの温度T以上の温度でガラス基板1を数分間保
持すると、シリコン薄膜2とその上に形成されたスズ塗
布層3とが溶融して、第4図に示したようにマトリクス
状の融液層4が形成される。
When the glass substrate 1 is held at a temperature higher than this temperature T for several minutes, the silicon thin film 2 and the tin coating layer 3 formed thereon melt, forming a matrix-like melt as shown in FIG. Layer 4 is formed.

なお融液層4は、スズ塗布層3が形成された真];/7
’l  M  O/7)Xi  I+  1’/  2
蔽 *  Q  /7)2.  す7 ニーJ”フ  
プ 徐 ノに 1i3の周辺のシリコン薄膜2を共に溶
融して形成されるものであるので、その面積はスズ塗布
層3のそれもよりも大きくなる。
Note that the melt layer 4 is the layer on which the tin coating layer 3 is formed];/7
'l M O/7) Xi I+ 1'/2
Cover * Q /7)2. 7 Knee J”F
Since it is formed by simultaneously melting the silicon thin film 2 around 1i3, its area is larger than that of the tin coating layer 3.

■冷却工程 ついで融液層4が形成されたガラス基板1を徐冷する。■Cooling process Next, the glass substrate 1 on which the melt layer 4 has been formed is slowly cooled.

降温しまた、昇温時と同様に一1O℃/分程度の緩やか
なものとする。ノリコンースズ合金の熱伝導率はガラス
のそれよりも大きいのて、融液層4の表面からガラス基
板1に向って温度分布が生じ、まず最初に融液層4の表
面からシリコンの結晶が析出する。そして冷却されると
ともに、このシリコンの結晶がガラス基板l側へ向って
成長するので、第5図に示したように、ノリコン薄膜2
中にマトリクス状にポリノリコン薄膜層5か形成される
The temperature is lowered slowly at a rate of about -10° C./min, similar to the temperature increase. Since the thermal conductivity of the Noricon-tin alloy is higher than that of glass, a temperature distribution occurs from the surface of the melt layer 4 toward the glass substrate 1, and silicon crystals first precipitate from the surface of the melt layer 4. . As it is cooled, this silicon crystal grows toward the glass substrate l side, and as shown in FIG.
A polynolycon thin film layer 5 is formed therein in a matrix shape.

このようにして形成されたポリノリコン薄膜層5は、融
液層4の表面に析出した結晶を核として成長させたもの
であるので、結晶粒径がlOμm程度と大きく、かつ結
晶性の良いものとなる。よっとなり、レーザアニール法
によって形成されたポリノリコノ薄膜と同程度もしくは
それ以上のキャリア移動度を有するポリノリコノ薄膜と
することができる。
The polynolycon thin film layer 5 formed in this manner is grown using the crystals precipitated on the surface of the melt layer 4 as nuclei, and therefore has a large crystal grain size of about 10 μm and has good crystallinity. Become. Therefore, it is possible to obtain a polygonal thin film having carrier mobility comparable to or higher than that of a polygonal thin film formed by laser annealing.

この発明の製造方法では、ノリコン−スズ合金の融液層
4からシリコンの結晶を析出させてポリノリコノ薄膜層
5とするが、このシリコンの結晶粒は融液層4の表面側
から成長するので、ポリノリコノ薄膜層5の表面におけ
るスズの混入は数ppm以下でノリコン濃度はほぼ10
0%である。またスズはシリコンと同様にIVb族元素
であるので、シリコン中に混入しても電気的に不活性で
あり、ポリノリコン薄膜層5のガラス基板l側の部分に
スズが混入していても、その半導体特性に全く影響を及
は゛さない。
In the manufacturing method of the present invention, silicon crystals are precipitated from the melt layer 4 of the Noricon-tin alloy to form the polynolycono thin film layer 5, but since the silicon crystal grains grow from the surface side of the melt layer 4, The amount of tin mixed on the surface of the thin film layer 5 is less than a few ppm, and the concentration of tin is approximately 10.
It is 0%. Furthermore, since tin is a group IVb element like silicon, it is electrically inactive even if it is mixed into silicon. It does not affect the semiconductor characteristics at all.

そしてポリシリコン薄膜層5とガラス基板1との界面で
は、スズ濃度が9激に増大し、逆にノリコン濃度は数%
以下となる。よって、このポリノリコン薄膜層5を用い
てたとえばコプラナー型薄膜トランツタを構成すれば、
ポリノリコン薄膜層5の表面がキャリアの走行するチャ
ンネル層となるので、理想的な構造の薄膜トランンタと
することができる。
At the interface between the polysilicon thin film layer 5 and the glass substrate 1, the tin concentration increases dramatically by 9%, while the noricon concentration increases by several percent.
The following is true. Therefore, if a coplanar type thin film transistor is constructed using this polynolylic thin film layer 5, for example,
Since the surface of the polynolycon thin film layer 5 becomes a channel layer through which carriers travel, a thin film transistor with an ideal structure can be obtained.

またこの発明の製造方法にあっては、印刷法によってシ
リコン薄膜層2上にスズ塗布層3を一括して形成するも
のであるので、ガラス基板lが大面積のものであっても
、ガラス基板−枚あたりの印刷に要する時間は数分と短
くすることかでき、スルーブツトを向上させることかで
きる。さらに加熱工程と冷却工程とは、多数枚のガラス
基板lを同時に処理することが可能であるので、スルー
プットすなわち量産性をより一層向上させることができ
る。
Furthermore, in the manufacturing method of the present invention, since the tin coating layer 3 is formed all at once on the silicon thin film layer 2 by the printing method, even if the glass substrate l has a large area, the glass substrate - The time required for printing per sheet can be reduced to just a few minutes, and throughput can be improved. Further, in the heating step and the cooling step, it is possible to simultaneously process a large number of glass substrates l, so that throughput, that is, mass productivity can be further improved.

特にこの発明の請求項2記載の製造方法にあっては、ス
ズ塗布層3をマトリクス状の微細領域に形成するもので
あるので、融液層4からのノリコンの結晶の成長に際し
、各結晶粒間の接触を少なくすることかでき、結晶粒径
をマトリクス状の微細領域とほぼ同し程度の大きさにま
で成長させることか可能となり、スイッチング速度の大
幅な向上を図ることができる。
In particular, in the manufacturing method according to claim 2 of the present invention, since the tin coating layer 3 is formed in a matrix-like fine area, each crystal grain is It is possible to reduce the contact between the crystal grains, and it is possible to grow the crystal grain size to approximately the same size as that of the matrix-like fine regions, and it is possible to significantly improve the switching speed.

[実施例コ ロ00mmX1000mmの矩形のガラス基板を用意し
、洗剤および酸の水溶液で順次洗浄して、その表面を清
浄にした。このガラス基板の片面上にプラズマCVD法
によって第2図に示したように、アモルファスノリコン
薄膜を膜厚l〜2μmで形成した。なおこの際に原料と
してはノラノカスを用い、ガラス基板を250℃に加熱
しに。ついで上記アモルファスノリコン薄膜上に、凹版
印刷法によって、粒径が1μm以下のスズ微粒子をボリ
ヒニルアルコール中に分散させてなるペーストを塗布し
て、スズ塗布層を2〜3μmの膜厚で第3図に示したよ
うに、マトリクス状に形成した。スズ塗布層のパターン
は、10μm×10μ+n17)角tとし、ピッチは水
平方向に150μm、垂直方向に450μmとし、その
数は水平方向に6000個、垂直方向に1000個数、
総数6百万個とした。この印刷には3分間を要した。
[Example] A rectangular glass substrate measuring 00 mm x 1000 mm was prepared and its surface was cleaned by sequentially washing with detergent and acid aqueous solutions. As shown in FIG. 2, an amorphous Noricon thin film was formed on one side of this glass substrate by plasma CVD to a thickness of 1 to 2 μm. At this time, Noranokasu was used as the raw material, and the glass substrate was heated to 250°C. Next, on the amorphous Noricon thin film, a paste made by dispersing fine tin particles with a particle size of 1 μm or less in polyhinyl alcohol is applied by an intaglio printing method to form a tin coating layer with a thickness of 2 to 3 μm. As shown in FIG. 3, it was formed into a matrix shape. The pattern of the tin coating layer is 10 μm x 10 μ + n17) angle t, the pitch is 150 μm in the horizontal direction and 450 μm in the vertical direction, and the number is 6000 in the horizontal direction and 1000 in the vertical direction.
The total number was 6 million. This printing took 3 minutes.

次にスズ塗布層が形成されたガラス基板を窒素雰囲気に
保たれた電気炉中で加熱した。30分かけて300℃に
まで昇温し、300°Cで数分間保持した後、さらに3
0分かけて室温にまで冷却した。この加熱の際に、アモ
ルファスノリコンとスズとが溶融し、マトリクス状に形
成されたスズ塗布層の面積が増大し、そのパターンが2
0μm×20μmと塗布時の約4倍に増大した。なおこ
の加熱処理は、多数枚のバッチ処理が可能であるので、
50枚のガラス基板を一緒に処理してスルーブツトの向
上を図った。
Next, the glass substrate on which the tin coating layer was formed was heated in an electric furnace maintained in a nitrogen atmosphere. The temperature was raised to 300°C over 30 minutes, held at 300°C for several minutes, and then heated for another 3 minutes.
The mixture was cooled to room temperature over 0 minutes. During this heating, the amorphous Noricon and tin melt, the area of the tin coating layer formed in a matrix increases, and the pattern becomes two.
The size was 0 μm×20 μm, approximately 4 times larger than when applied. Note that this heat treatment can be performed in batches on a large number of sheets.
Fifty glass substrates were processed together to improve throughput.

このようにして形成されたポリノリコノ薄膜の結晶構造
を調べるために、ポリノリコン薄膜層の表面を希沸酸系
水溶液でエツチングした後、微分干渉顕微鏡で観察した
。通常LPCVD法によって形成されたポリノリコノ薄
膜の結晶粒は1μm以下と小さいが、この発明の製造方
法で得られたポリノリコノ薄膜の結晶粒は大きく、IO
J1m以上となった。すなわち20μm×20μmのマ
トリクス状のパターン中において結晶粒界の数は数本以
下となってい1こ。またこのポリノリコン薄膜の組成を
厚さ方向に沿ってイオンマイクロアナライザ(IMS)
で調べた。この結果、薄膜表面ではほぼ100%シリコ
ンであり、スズの混入は数pp如以下であった。またガ
ラス基板上の各マトリクス間での結晶粒界数のバラツキ
を調べたところ、約1000mm離れたマトリクス間に
おいても2倍以下となり、大面積基板であっても均一な
薄膜となっていることが確認できた。
In order to investigate the crystal structure of the polynolycon thin film thus formed, the surface of the polynolycon thin film layer was etched with a dilute hydrofluoric acid aqueous solution and then observed using a differential interference microscope. Normally, the crystal grains of the polynolycono thin film formed by the LPCVD method are small, 1 μm or less, but the crystal grains of the polynolycono thin film obtained by the manufacturing method of the present invention are large, and the IO
J1m or more. In other words, the number of grain boundaries in a matrix pattern of 20 μm x 20 μm is one, which is less than a few. In addition, the composition of this polynolycon thin film was measured along the thickness direction using an ion microanalyzer (IMS).
I looked it up. As a result, the surface of the thin film was almost 100% silicon, and the amount of tin mixed was less than a few pp. Furthermore, when we investigated the variation in the number of grain boundaries between matrices on a glass substrate, it was less than double even between matrices separated by about 1000 mm, indicating that even on a large-area substrate, a uniform thin film was obtained. It could be confirmed.

次に、このようにしてマトリクス状に形成された各ポリ
シリコン薄膜上に、第8図に示したようなコブラナー型
の電界効果型薄膜トランシタを作成した。この作成には
通常の薄膜トランシタの製造プロセスを用いた。なお第
851cl中、符号6はソース電極、符号7はドレイン
電極、符号8はゲート電極、符号9はゲート絶縁膜をそ
れぞれ示す。
Next, on each of the polysilicon thin films formed in a matrix in this way, a Cobranar type field effect thin film transistor as shown in FIG. 8 was formed. This was fabricated using a normal thin film transistor manufacturing process. In the 851 cl, reference numeral 6 indicates a source electrode, 7 indicates a drain electrode, 8 indicates a gate electrode, and 9 indicates a gate insulating film.

この薄膜トランシタのチャネル長およびチャネル幅は、
それぞれ5μmおよび10μmとした。薄膜トランシタ
のサイズをポリシリコン薄膜層のマトリクスのパターン
サイズよりもかなり小さくすることにより、ガラス基板
全面にわたって薄膜トランシタをそれぞれのポリシリコ
ン薄膜層上に形成することができた。
The channel length and channel width of this thin film transistor are
The diameters were 5 μm and 10 μm, respectively. By making the size of the thin film transistors much smaller than the pattern size of the matrix of polysilicon thin film layers, it was possible to form thin film transistors on each polysilicon thin film layer over the entire surface of the glass substrate.

このようにして製造された薄膜トランシタの電流電圧特
性からポリシリコン薄膜層のキャリア移動度を求めたと
ころ、約120 cva”/ vsと高い値が得られた
。この値はレーザアニール法による薄膜と同等以上の高
いものである。この結果、第9図に示したような等価回
路において薄膜トランシタ総数6百万個という大表示容
量の高画質液晶デイスプレィを実現することができた。
When the carrier mobility of the polysilicon thin film layer was determined from the current-voltage characteristics of the thin film transistor manufactured in this way, a high value of approximately 120 cva"/vs was obtained. This value is higher than that of the thin film produced by the laser annealing method. As a result, it was possible to realize a high-quality liquid crystal display with a large display capacity and a total of 6 million thin film transistors using the equivalent circuit shown in FIG.

[発明の効果] 以上説明したように、この発明の半導体薄膜の製造方法
によれば、シリコン−スズ合金の融液からシリコン結晶
を成長させるものであるので、結晶粒径が大きく、結晶
性の良好なポリシリコン薄膜を形成することができる。
[Effects of the Invention] As explained above, according to the method for producing a semiconductor thin film of the present invention, silicon crystals are grown from a silicon-tin alloy melt, so the crystal grain size is large and the crystallinity is low. A good polysilicon thin film can be formed.

よって、大面積液晶デイスプレィを駆動するに十分なキ
ャリア移動度を有する半導体薄膜が得られる。
Therefore, a semiconductor thin film having sufficient carrier mobility to drive a large area liquid crystal display can be obtained.

またこの発明の製造方法によれば、印刷法により一括し
て形成するものであるので、短時間にて大面積の基板を
処理することができる。さらに加熱処理は多数枚のガラ
ス基板を同時に処理することができるので、スループッ
トの向上を図ることができ、量産性を高めることもでき
る。
Further, according to the manufacturing method of the present invention, since the substrates are formed all at once by a printing method, a large area of the substrate can be processed in a short time. Furthermore, since a large number of glass substrates can be treated simultaneously in the heat treatment, throughput can be improved and mass productivity can also be improved.

【図面の簡単な説明】[Brief explanation of drawings]

!1図ないし第5図は、いずれもこの発明の製造方法の
各工程におけるガラス基板を示した概略断面図、策6図
はこの発明の製造方法の加熱および冷却工程の温度条件
を示すグラフ、第7図はノリコンースズの二元合金状態
図、第8図はこの発明の実施例における電界効果型薄膜
トランツタの概略断面図、第9図は液晶デイスプレィの
等価回路図である。 l・・・ガラス基板、  2・・・シリコン薄膜、3・
・・スズ塗布層、  4・・・融液層、5・・・ポリシ
リコン薄膜層。
! 1 to 5 are schematic cross-sectional views showing the glass substrate in each step of the manufacturing method of the present invention, and Figure 6 is a graph showing the temperature conditions of the heating and cooling steps of the manufacturing method of the present invention. FIG. 7 is a state diagram of a binary alloy of Noricon tin, FIG. 8 is a schematic cross-sectional view of a field-effect thin film transistor according to an embodiment of the present invention, and FIG. 9 is an equivalent circuit diagram of a liquid crystal display. l...Glass substrate, 2...Silicon thin film, 3.
...Tin coating layer, 4...Melt layer, 5...Polysilicon thin film layer.

Claims (2)

【特許請求の範囲】[Claims] (1)ガラス基板上にシリコン薄膜層を形成し、スズ微
粒子を有機溶媒に分散させてなるペーストを上記シリコ
ン薄膜層上に塗布した後、このガラス基板を232℃以
上に加熱した後、徐冷することを特徴とする半導体薄膜
の製造方法
(1) After forming a silicon thin film layer on a glass substrate and applying a paste made by dispersing tin particles in an organic solvent onto the silicon thin film layer, heating the glass substrate to 232°C or higher, and then slowly cooling it. A method for manufacturing a semiconductor thin film characterized by
(2)スズ微粒子を有機溶媒に分散させてなるペースト
をシリコン薄膜層上にマトリクス状に塗布することを特
徴とする請求項1記載の半導体薄膜の製造方法
(2) The method for manufacturing a semiconductor thin film according to claim 1, characterized in that a paste made by dispersing tin fine particles in an organic solvent is applied in a matrix on the silicon thin film layer.
JP8162590A 1990-03-29 1990-03-29 Method for manufacturing semiconductor thin film Expired - Fee Related JPH0760807B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Publications (2)

Publication Number Publication Date
JPH03280420A true JPH03280420A (en) 1991-12-11
JPH0760807B2 JPH0760807B2 (en) 1995-06-28

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Cited By (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0786608A (en) * 1993-09-07 1995-03-31 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacture thereof
JPH07161635A (en) * 1993-12-02 1995-06-23 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method thereof
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US5879977A (en) * 1993-02-15 1999-03-09 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating a thin film transistor semiconductor device
US5923962A (en) * 1993-10-29 1999-07-13 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
JP2000089250A (en) * 1998-09-10 2000-03-31 Sony Corp Production of electro-optic device and production of drive substrate for exectro-optic device
JP2000111943A (en) * 1998-09-30 2000-04-21 Sony Corp Method of manufacturing electro-optical device and method of manufacturing drive substrate for electro-optical device
US6074901A (en) * 1993-12-03 2000-06-13 Semiconductor Energy Laboratory Co., Ltd. Process for crystallizing an amorphous silicon film and apparatus for fabricating the same
US6090646A (en) * 1993-05-26 2000-07-18 Semiconductor Energy Laboratory Co., Ltd. Method for producing semiconductor device
US6210997B1 (en) 1993-07-27 2001-04-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US6232156B1 (en) 1994-02-03 2001-05-15 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US6285042B1 (en) 1993-10-29 2001-09-04 Semiconductor Energy Laboratory Co., Ltd. Active Matry Display
US6335555B1 (en) 1993-10-01 2002-01-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a manufacturing method for the same
US6337229B1 (en) 1994-12-16 2002-01-08 Semiconductor Energy Laboratory Co., Ltd. Method of making crystal silicon semiconductor and thin film transistor
US6348367B1 (en) 1993-12-02 2002-02-19 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US6413805B1 (en) 1993-03-12 2002-07-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device forming method
US6610142B1 (en) 1993-02-03 2003-08-26 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating semiconductor and process for fabricating semiconductor device
US6624445B2 (en) 1993-12-22 2003-09-23 Semiconductor Energy Laboratory Co., Ltd Semiconductor device and method of manufacturing the same
US6753213B2 (en) 1994-07-28 2004-06-22 Semiconductor Energy Laboratory Co., Ltd. Laser processing method
US6798023B1 (en) 1993-12-02 2004-09-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising first insulating film, second insulating film comprising organic resin on the first insulating film, and pixel electrode over the second insulating film
US6875628B1 (en) 1993-05-26 2005-04-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and fabrication method of the same
US6884698B1 (en) 1994-02-23 2005-04-26 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device with crystallization of amorphous silicon
US6919237B2 (en) 1994-06-02 2005-07-19 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating thin film transistors
US6924506B2 (en) 1993-05-26 2005-08-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having channel formation region comprising silicon and containing a group IV element
US6997985B1 (en) 1993-02-15 2006-02-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor, semiconductor device, and method for fabricating the same
US7037811B1 (en) 1996-01-26 2006-05-02 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating a semiconductor device
US7056381B1 (en) 1996-01-26 2006-06-06 Semiconductor Energy Laboratory Co., Ltd. Fabrication method of semiconductor device
US7078727B2 (en) 1996-01-19 2006-07-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and its manufacturing method
US7135741B1 (en) 1996-03-17 2006-11-14 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
JP2006319361A (en) * 2006-07-19 2006-11-24 Semiconductor Energy Lab Co Ltd Method for manufacturing crystalline silicon film, and semiconductor device
US7173282B2 (en) 1996-01-19 2007-02-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a crystalline semiconductor film
US7186601B2 (en) 1994-08-26 2007-03-06 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a semiconductor device utilizing a catalyst material solution
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US7427780B2 (en) 1996-01-19 2008-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating same
US7456056B2 (en) 1996-01-19 2008-11-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for fabricating the same
US7767559B2 (en) 1994-06-02 2010-08-03 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating semiconductor device
US8835271B2 (en) 2002-04-09 2014-09-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device
US8946717B2 (en) 2002-04-09 2015-02-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and display device using the same
US9366930B2 (en) 2002-05-17 2016-06-14 Semiconductor Energy Laboratory Co., Ltd. Display device with capacitor elements

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60257124A (en) * 1984-06-01 1985-12-18 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
JPS6212655A (en) * 1985-07-08 1987-01-21 川崎炉材株式会社 Carbon-containing refractory brick
JPH01110776A (en) * 1987-10-23 1989-04-27 Mitsubishi Electric Corp Manufacture of semiconductor polycrystalline thin film

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60257124A (en) * 1984-06-01 1985-12-18 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
JPS6212655A (en) * 1985-07-08 1987-01-21 川崎炉材株式会社 Carbon-containing refractory brick
JPH01110776A (en) * 1987-10-23 1989-04-27 Mitsubishi Electric Corp Manufacture of semiconductor polycrystalline thin film

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US6110770A (en) * 1993-02-15 2000-08-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor and process for fabricating the same
US6987283B2 (en) 1993-03-12 2006-01-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device structure
US7391051B2 (en) 1993-03-12 2008-06-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device forming method
US6413805B1 (en) 1993-03-12 2002-07-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device forming method
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US6210997B1 (en) 1993-07-27 2001-04-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
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US7170138B2 (en) 1993-10-01 2007-01-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7301209B2 (en) 1993-10-01 2007-11-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7615786B2 (en) 1993-10-01 2009-11-10 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor incorporating an integrated capacitor and pixel region
US6285042B1 (en) 1993-10-29 2001-09-04 Semiconductor Energy Laboratory Co., Ltd. Active Matry Display
US6335541B1 (en) 1993-10-29 2002-01-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor thin film transistor with crystal orientation
US6998639B2 (en) 1993-10-29 2006-02-14 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US5923962A (en) * 1993-10-29 1999-07-13 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US7998844B2 (en) 1993-10-29 2011-08-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US6348367B1 (en) 1993-12-02 2002-02-19 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US6798023B1 (en) 1993-12-02 2004-09-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising first insulating film, second insulating film comprising organic resin on the first insulating film, and pixel electrode over the second insulating film
US7141461B2 (en) 1993-12-02 2006-11-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
JPH07161635A (en) * 1993-12-02 1995-06-23 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method thereof
US6074901A (en) * 1993-12-03 2000-06-13 Semiconductor Energy Laboratory Co., Ltd. Process for crystallizing an amorphous silicon film and apparatus for fabricating the same
JPH07183536A (en) * 1993-12-22 1995-07-21 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacture thereof
US6624445B2 (en) 1993-12-22 2003-09-23 Semiconductor Energy Laboratory Co., Ltd Semiconductor device and method of manufacturing the same
US7402471B2 (en) 1993-12-22 2008-07-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US6955954B2 (en) 1993-12-22 2005-10-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JPH07183537A (en) * 1993-12-22 1995-07-21 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacture thereof
JP2007158368A (en) * 1993-12-24 2007-06-21 Semiconductor Energy Lab Co Ltd Method of manufacturing semiconductor device
JPH07231100A (en) * 1993-12-24 1995-08-29 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacturing method
US6417031B2 (en) 1994-02-03 2002-07-09 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US6232156B1 (en) 1994-02-03 2001-05-15 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US6884698B1 (en) 1994-02-23 2005-04-26 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device with crystallization of amorphous silicon
US7749819B2 (en) 1994-02-23 2010-07-06 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7235828B2 (en) 1994-02-23 2007-06-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with residual nickel from crystallization of semiconductor film
US7767559B2 (en) 1994-06-02 2010-08-03 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating semiconductor device
US7470575B2 (en) 1994-06-02 2008-12-30 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating semiconductor device
US6919237B2 (en) 1994-06-02 2005-07-19 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating thin film transistors
US6753213B2 (en) 1994-07-28 2004-06-22 Semiconductor Energy Laboratory Co., Ltd. Laser processing method
US7186601B2 (en) 1994-08-26 2007-03-06 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a semiconductor device utilizing a catalyst material solution
US6337229B1 (en) 1994-12-16 2002-01-08 Semiconductor Energy Laboratory Co., Ltd. Method of making crystal silicon semiconductor and thin film transistor
US7173282B2 (en) 1996-01-19 2007-02-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a crystalline semiconductor film
US7456056B2 (en) 1996-01-19 2008-11-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for fabricating the same
US7078727B2 (en) 1996-01-19 2006-07-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and its manufacturing method
US7427780B2 (en) 1996-01-19 2008-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating same
US7056381B1 (en) 1996-01-26 2006-06-06 Semiconductor Energy Laboratory Co., Ltd. Fabrication method of semiconductor device
US7141491B2 (en) 1996-01-26 2006-11-28 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating a semiconductor device
US7422630B2 (en) 1996-01-26 2008-09-09 Semiconductor Energy Laboratory Co., Ltd. Fabrication method of semiconductor device
US7037811B1 (en) 1996-01-26 2006-05-02 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating a semiconductor device
US7135741B1 (en) 1996-03-17 2006-11-14 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
JP2000089250A (en) * 1998-09-10 2000-03-31 Sony Corp Production of electro-optic device and production of drive substrate for exectro-optic device
JP2000111943A (en) * 1998-09-30 2000-04-21 Sony Corp Method of manufacturing electro-optical device and method of manufacturing drive substrate for electro-optical device
US9105727B2 (en) 2002-04-09 2015-08-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and display device using the same
US10700106B2 (en) 2002-04-09 2020-06-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and display device using the same
US8946717B2 (en) 2002-04-09 2015-02-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and display device using the same
US8946718B2 (en) 2002-04-09 2015-02-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and display device using the same
US11101299B2 (en) 2002-04-09 2021-08-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device
US10854642B2 (en) 2002-04-09 2020-12-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and display device using the same
US9406806B2 (en) 2002-04-09 2016-08-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and display device using the same
US9666614B2 (en) 2002-04-09 2017-05-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device
US10050065B2 (en) 2002-04-09 2018-08-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and display device using the same
US10083995B2 (en) 2002-04-09 2018-09-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device
US8835271B2 (en) 2002-04-09 2014-09-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device
US10133139B2 (en) 2002-05-17 2018-11-20 Semiconductor Energy Laboratory Co., Ltd. Display device
US10527903B2 (en) 2002-05-17 2020-01-07 Semiconductor Energy Laboratory Co., Ltd. Display device
US9366930B2 (en) 2002-05-17 2016-06-14 Semiconductor Energy Laboratory Co., Ltd. Display device with capacitor elements
US11422423B2 (en) 2002-05-17 2022-08-23 Semiconductor Energy Laboratory Co., Ltd. Display device
JP2006319361A (en) * 2006-07-19 2006-11-24 Semiconductor Energy Lab Co Ltd Method for manufacturing crystalline silicon film, and semiconductor device

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