JPH03278446A - Automatic wiring for semiconductor device - Google Patents

Abstract

PURPOSE:To perform detail wiring by performing rough wire processing by grit system which becomes the unit of wiring paths decided by detail wiring process, invalidating the part of the paths and using the valid wiring paths. CONSTITUTION:Semiconductor chip 1 is separated into the rough unit wiring areas of 4X4, paths between the unit areas are decided by rough wiring process and paths in each unit area are decided by detail wiring process. At that time, nets are sucessively selected from the nets to be processed excluding the closed nets in the unit area and the selected nets are processed using the same grit system as the one used for the detail wiring process. Segments which pass through the unit area are extracted from the obtained wiring segments, a partial wiring segment which passes through the unit area is created for each selected segment so as to have them as obstructions when wire-processing nets to be selected subsequently and the rough wiring process of the whole nets is performed. The detail wiring process in the unit area is performed using the obtained partial wiring segments as the wired wiring.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a wiring method for semiconductor devices such as a standard cell type or a gate array type, and in particular, to an automatic wiring method for semiconductor devices using CAD. Regarding the method.

(Prior Art) With advances in semiconductor microfabrication technology, the number of circuit elements that can be mounted on a chip is increasing year by year.

For this reason, considering the design time, LSI design takes time and effort that is almost impossible to do manually, and automatic placement and wiring using a computer (CAD) is essential for LSI design.

When the scale of the circuit is small, automatic wiring between circuit cells within a chip is performed by completing the wiring within the chip over the entire surface of the chip at once. However, since wiring the entire surface of a chip requires a significant amount of computer processing time and requires a huge amount of memory, it has traditionally been the practice to divide the wiring process into two stages. It is being said. In other words, the chip is divided into a plurality of partial areas, first a rough wiring process is performed to determine the rough wiring routes between the partial areas on the entire surface of the chip, and then detailed wiring is performed for each area. A method of wiring that reduces the amount of data handled has been used.

FIG. 7 is a diagram showing a conventional wiring method.

In the figure, reference numeral 11 indicates the entire semiconductor chip, and dotted lines indicate a wiring grid in which wiring terminals are present.

The area obtained by dividing the chip into vertical and horizontal lattices shown by solid lines is defined as a general lattice G (p, q). In conventional general wiring, a rough wiring route is once determined on this general grid. In other words, which region G (p,
q) to determine whether to perform the process.

At this time, although there are multiple terminals of different nets inside G (p, q), they are all treated as being located at representative points of this area. This representative point is, for example, the area G (
p, q). Also, when searching for the wiring route of each net, the area G (p, q)
The number of wires that can actually be wired as the capacity of the number of wires on the boundary line (four places on the top, bottom, left and right) of the area G (p, q
) is estimated from the distribution of obstacles, etc. inside the area, and a wiring route is selected so as not to exceed this estimated value in each boundary area.

Next, in each partial area, we take into account the actual terminal positions in the detailed wiring grid system, obtain information about ``from which side on the boundary the wiring will come out'' determined by the rough wiring, and then Perform detailed wiring. By repeating these steps and sequentially wiring each partial area, when all areas have been processed, the wiring result for the entire chip is obtained.

Conventionally, the wiring process is divided into two stages as described above, and in the first rough wiring stage, the placement process is performed on the entire surface of the chip on a coarse grid, and then the wiring on the second detailed grid is performed. By processing each partial area of the chip, the amount of data handled in both stages is reduced and the processing time required for the entire wiring process is reduced. However, such two-step processing causes the following problems.

FIG. 8 is a diagram showing the wiring results obtained by the conventional processing method described above. In Figure 8, ■ indicates the result of the rough wiring,
3 shows the wiring result of detailed wiring, and the cross-hatched area shows the area where wiring is prohibited.

In Fig. 8(a), G
(j, 1), G(j, 2), and G(j, 3) are shown as examples. G(j, 1) and G(j.

3) There are terminals A and B (indicated by O in the figure).

In the rough wiring, the same rough route ((G (j, 1), G (j, 2), G (j, 3)
get l. In detailed wiring, for example, the processing order is G (j, 1) - G (j 2) - G (
j, 3). In region G(j, 1), net A
If the boundary terminals of net B and B are set at the positions marked by X, a redundant wiring result as shown in FIG. 8(a) is obtained. Also, in the case as shown in FIG. 8(b), the wiring result obtained by detailed wiring may become a redundant route with a detour.

The reason for these problems is that in the general route, the position of each terminal is not accurately grasped, while in detailed wiring, the position information of the terminal is locally checked for each partial area, and the boundary position of the area (×
This is because it has been determined.

Furthermore, in the conventional wiring direction, it is necessary to estimate the number of wires that can be wired on the boundary of each partial region at the rough wiring stage, but this also has problems. For example, when there are four terminals in one partial area as shown in Figure 9(a), tracks that are already occupied by terminals or areas where wiring is prohibited are not included in the calculation of the capacity of the number of wiring. If you estimate that,
The wiring capacitance on the boundary of this region is O, and the 4
The estimate is that one truck cannot be used for wiring.

However, as shown in FIG. 9(b), wiring may actually be possible through this area. Thus, the error between the estimated value and the actual routing possibility may result in all routing being impossible.

(Problems to be Solved by the Invention) As described above, in the conventional method of completing the wiring of the entire chip in two stages of general wiring and detailed wiring, some of the wiring results may become redundant. There was also the problem that the wiring of the chip could not be completed completely.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a semiconductor device that can achieve high connection efficiency and non-redundant wiring without increasing the wiring processing time. The purpose of this invention is to provide an automatic wiring method.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a semiconductor chip is divided into a plurality of unit wiring areas, and wiring routes between each unit wiring area are determined by rough wiring processing. In an automatic wiring method for a semiconductor device in which wiring routes for a semiconductor chip are then determined by detailed wiring processing in each unit wiring area, the present invention divides a semiconductor chip into a plurality of unit wiring areas. , sequentially select nets excluding closed nets within the unit wiring area from among multiple nets to be routed, and route the selected nets to the same grid used in detailed routing. Do it in a system,
A wiring segment passing through the unit wiring area is extracted from one or more wiring segments forming the wiring route of the net obtained by this wiring process, and at least a unit wiring area is set for each extracted wiring segment. create one or more partial wiring segments that pass through the
Using the created partial wiring segment as an obstacle in the wiring process of the next selected net, perform rough wiring processing for all the selected nets, and use the partial wiring segment obtained through this rough routing process as already routed. The gist is to perform detailed wiring processing within each unit wiring area.

(Operation) The present invention performs rough wiring processing in a grid system that is a route unit of a wiring route determined by detailed wiring processing, invalidates a part of the wiring route that has been routed, and proceeds with the rough wiring processing. Detailed wiring processing is performed using the effective wiring routes obtained in the general wiring processing.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a flowchart showing the processing procedure of an automatic wiring method for a semiconductor device according to an embodiment of the present invention. The automatic wiring method shown in the figure is a wiring method that performs wiring through a two-step process of general wiring processing and detailed wiring processing. A rough wiring process is performed using the wiring grid system to be used, and some of the wiring results are used as obstacles for the next rough wiring process, and others are invalidated to proceed with the rough wiring process.

In FIG. 1, first, a semiconductor chip on which circuit cells and circuit blocks are arranged is divided into rough wiring regions (partial regions) vertically and horizontally (step Sl).

For example, as shown in FIG.
, and each grid is divided into G (p,
q), p-1 to 4, and q-1 to 4.

In the chip divided in this way, the nets to be routed are divided into two types of sets N (1).

Classify into N(2) (step S2). Here, the set of nets that require connection - N (1) +N (2), N (1) - (the terminals of the net belong to multiple general grids) N (2) - (the terminals of the net are all the same) belongs to the approximate lattice of). In a net classified in this way, N(1
) is a net with a long wiring length that spans a wide area of the chip, and N(2) is a net that is closed in a local area within one lattice.

Next, one net is selected from among the nets belonging to N (1) based on a preset order (step S
3).

Next, wiring processing is performed between the terminals of the selected net (step S4). In this wiring process, wiring is performed not on a general wiring grid but on a detailed grid determined from design rules. That is, wiring processing is performed using the same wiring grid system used in detailed wiring processing.

Furthermore, obstacles to the wiring process at this time include areas where wiring is prohibited, terminals of other nets, etc., and the wiring process is performed with partial overlap of the wiring being allowed. Furthermore, as a wiring algorithm for finding connection paths between terminals, a line segment search method using line segments as units is used, which is suitable for large-scale chips with a large number of wiring grids.

Next, from among the wiring segments forming the wiring route determined by the wiring process, wiring segments that approximately pass between the wiring grids are extracted (step S5).

Next, one wiring segment (SEI) is selected from the extracted wiring segments, and the selected wiring segment (SEI) is selected.
EI ) to one or more partial wiring segments (SE
ll+ S E +2.・・・・・・ SE, fi
) is created (step S6). The method for creating a partial wiring segment will be explained in detail later using a specific example.

Next, the partial wiring segment created in this way is added to obstacles during wiring processing (step S7).
). As a result, wiring processing is performed so that the wiring of the next net to be wired does not overlap with the created partial wiring segment.

This process of creating partial wiring segments is performed for all wiring segments forming the wiring route of one wired net (step S8). moreover,
The processes from step 3 to step S8 described above are repeated for all nets to be routed (step S9). In this way, the general wiring processing for all the general wiring grids of the semiconductor chip is completed. At the time when such general wiring processing is completed, wiring segments that do not pass through the general wiring grid and wiring segments that are not created as partial wiring segments are invalidated in the next detailed wiring processing.

Next, within each general wiring grid, the detailed wiring process of the net belonging to N(2) and the new detailed wiring process of the wiring route that was invalidated in the above-mentioned general wiring process are performed so that the wiring does not overlap. (Step 510). Such detailed wiring processing is executed for all the general wiring grids (step 510), and all wiring processing for the semiconductor chip is executed.

In such a wiring process, the wiring segment SE passing between the grids is entirely converted into a partial wiring segment S.
When set to Ez, this corresponds to the case where the entire chip is wired without allowing overlapping for the net belonging to N(1).

When setting up such a partial wiring segment,
As the wiring process progresses, the degree of congestion of the wiring route increases due to the wiring segments of the nets that have been routed up to that point, and the later the wiring process is performed, the more difficult it becomes to find the wiring route.

However, in the method shown in the embodiment of the present invention, a part of the obtained wiring segment is made into a partial wiring segment, and this partial wiring segment is validated as already wired. Therefore, even if the wiring process has progressed, congestion is alleviated compared to the case described above, and the wiring route can be found relatively easily. Therefore, by introducing a method called partial wiring segments in rough wiring processing, wiring processing is performed with less wiring congestion, so that the entire chip is used for nets belonging to N(1) during detailed wiring processing. Even if wiring processing is performed in a wiring grid system, the wiring processing time is not significantly increased.

In addition, rough wiring processing takes into account the positions of terminals and wiring-prohibited areas accurately, and is performed using the same wiring grid system used during detailed wiring processing, so passing through the rough wiring grid is more effective than before. A wiring route can be obtained. For this reason,
The detailed wiring process that uses this wiring route and the general wiring process are closely related, and the detailed wiring process that uses the general wiring result can obtain wiring results with no redundancy and a high connection rate. .

Next, a wiring procedure including a method for creating a partial wiring segment will be explained using a specific example.

FIG. 2 is a diagram showing the wiring results of the wiring processing from step 81 to step S9 shown in FIG. 1 in the schematic wiring grid shown in FIG. 7. In the figure, the terminals to be connected are indicated by "○", and the terminals with the same symbols are connected. In addition, the area where wiring is prohibited is shown as a liberal arts line area, and the wiring layer is 2
For example, the vertical direction is used as a first layer, and the horizontal direction is used as a second layer.

In such a terminal arrangement, net A to be wired
, B, C, D, and E, net C is a general wiring grid G
Since all the terminals of the net exist in (2, 3), N (1) - (A, B, D, E) N (2) - (C1). Therefore, step S2 of the rough wiring process Then, C is excluded from the wiring processing target.

Once the nets to be subjected to wiring processing are determined, the processing order of these nets is determined in advance, for example, in the order of net A -> net B -> net D -> net E. The general wiring process for each net is executed in this order, but in the first wiring process for net A, wiring with the terminals of other nets B, C, D, and E is prohibited. A wiring route is searched using the area as an obstacle.

Assume that the wiring process for net A has been completed and a wiring route as shown in FIG. 2 has been obtained. Such wiring routes include wiring segments SEA□, 5EA2. 5EA3+
Consists of SE A4. Among such wiring segments, wiring segments 5EAL, 5EA3. which pass through the general wiring grid are wiring segments. SE^
4 is extracted in the process shown in step S5.

Next, a partial wiring segment is created for each extracted wiring segment. Rules for the creation method include, for example: (a) For a wiring segment connected to a terminal, the entire wiring segment is a partial wiring segment.

(b) For wiring segments whose end points are in mutually adjacent general wiring grids, the wiring segment at one grid point in the adjacent portion of both terminals is defined as a partial wiring segment.

(C) For a wiring segment that passes through three or more general wiring grids, the entire wiring segment is a partial wiring segment.

θ) (a), (b), (C) In any case, the right end and top end of the partial wiring segment are included in the partial wiring segment. On the other hand, the left end and bottom end are not included in the partial wiring segment.

Note that rule θ) is not necessarily limited to the above, and may be the reverse of the above, and may include both the left and right, top and bottom ends, or may not include both the left and right, top and bottom ends. good.

Using such rules, partial wiring segments shown in the shaded area in FIG. 3 are sequentially created from the wiring segments constituting the wiring route obtained by the rough wiring processing of each net.

For example, in the wiring process for net A, wiring segment 5
Rule (a) and rule (d) are applied to EA1 to create a partial wiring segment consisting of grid points p, , p2, and p3. Wiring segment 5EA3 has
Rule (b) is applied and grid point P4. A partial wiring segment consisting of P5 is created. Rule (C) is applied to the wiring segment 5EA4 to create a partial wiring segment consisting of grid points P6 to P18.

In this way, for example, when a partial wiring segment in net A is created, this partial wiring segment, that is, grid points P1 to P1B, is registered as an obstacle. On the other hand, the grid point PI7. which constitutes the wiring segment other than this, that is, the wiring segment 5EA2. PI8
The grid point P19, which was not registered as a partial wiring segment of the wiring segment 5EA3, is invalidated and does not become an obstacle to the wiring processing after the net A. Similarly, when the rough wiring process for nets B to E is completed, partial wiring segments for each net are obtained as shown in FIG.

Next, using the obtained partial wiring segments, detailed wiring processing is performed for parts where wiring routes are undetermined and parts where wiring in the same layer overlaps in each general wiring grid so that wiring does not overlap. This is done for each rough wiring grid.

For example, in the general wiring grid G (2, 3), grid points P20 and P20, which form the partial wiring segment of net E,
21, a search for a wiring route between grid points P22 and P21 forming a partial wiring segment of net B, and a search for a wiring route for net C. Furthermore, in the general wiring grid G (4, 2), a wiring route between grid points P3 and 24 forming the partial wiring segment of net A is searched, and a wiring route between the terminal of net D and grid point P2 is searched.
4 is searched for. As a search result, for example, a result as shown in FIG. 4 is obtained.

In FIG. 4, the wiring segment of net B in the schematic wiring grid G (2,3) is located at grid point P 22+
It is composed of P 23 + P 25, and the net C
The wiring segment of is the grid point P 20+ P 2+
+ P 26 + P 27 + P 2g,
The wiring segment of net E is at grid point P20+P
Consists of 21+P29.

Also, the net A in the approximate wiring grid G (4,2)
The wiring segment at grid point p3. p4゜PI7.
The wiring segment of net D is composed of grid points PI7+pie, P241 and P31.

Next, another example of a method for creating a partial wiring segment will be described.

This creation method creates partial wiring segments based on the rule that "a wiring segment passing between approximate wiring grids is created as a partial wiring segment of unit length between both grids."

A specific example of creating partial wiring segments according to such rules is shown in FIG.

Figure 5 shows nets A and B in a 3x3 schematic wiring grid.
, C is a diagram showing the wiring results obtained by performing the general wiring process. In FIG. 5, partial wiring segments are shown by thick solid lines, and partial wiring segments of unit length are created between the general wiring grids passing through the wiring segments of each net. Note that in a multi-terminal net such as net C in which two or more terminals exist within the same grid, one terminal is selected from within the same grid and wiring processing is performed. FIG. 5 shows the results of selecting and wiring one terminal from grid G (1, 3) and one terminal from grid G (2, 3).

In the state shown in FIG. 5, when wiring the net P, the wiring process is performed with only the terminals and partial wiring segments of each net as obstacles and other wiring segments as invalid.

The wiring result is as shown in FIG. 6, for example. In Figure 6, the wiring of net P is connected to net B at grid point Q.
Although this overlaps with the wiring of , this will be resolved in detailed wiring processing for each rough wiring grid. Therefore, even with such a method of creating a partial wiring segment, it is possible to obtain the same effect as when using the above-described method of creating.

In addition, in response to the requirements from the aspect of circuit characteristics, ``For the wiring segments of nets whose wiring routes need to be determined preferentially, all wiring segments obtained through rough wiring processing should be used as partial wiring segments.'' Rules may be set to create partial wiring segments. In such a case, it is possible to implement wiring processing that takes circuit characteristics into consideration.

In this way, various methods can be considered for creating partial wiring segments, and the method is not limited to the above-mentioned method.

[Effects of the Invention] As explained above, according to the present invention, rough wiring processing is performed using the grid system used in detailed wiring processing, and a part of the wiring route that has been routed is invalidated to perform the rough wiring processing. Since the detailed wiring process is performed using the results, it is possible to obtain wiring results with no redundancy and a high connection rate without increasing the wiring processing time in the wiring process of semiconductor devices. You will be able to do this.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing the steps of an automatic wiring method for semiconductor devices according to an embodiment of the present invention, and FIGS. 2 to 4 are diagrams showing the progress of wiring processing by the method shown in FIG. 5 and 6 are diagrams for explaining other examples of the main parts of the method shown in FIG. 1, and FIGS. 7 to 9 are diagrams for explaining the conventional wiring method. 11... Semiconductor chip, A, B, C, D, E, P... Terminal, SEA, , SEA□, S E A3. A S E A4
...Wiring segment, P1 to P31. Q... Grid point, (p. q)... Schematic wiring grid.

Claims (1)

[Claims] After dividing a semiconductor chip into a plurality of unit wiring areas, determining wiring routes between each unit wiring area by rough wiring processing, and then determining wiring routes within each unit wiring area by detailed wiring processing. When determining and automatically performing wiring processing on a semiconductor chip, the semiconductor chip is divided into multiple unit wiring areas, nets to be processed are sequentially selected, and the wiring processing for the selected nets is detailed. Extracting a wiring segment passing through the unit wiring area from among one or more wiring segments forming the wiring route of the net obtained by the wiring process, using the same grid system used in the wiring process, Create one or more partial wiring segments that pass through at least the unit wiring area for each extracted wiring segment, and select the created partial wiring segments as obstacles in the wiring process of the next selected net. Automatic wiring of a semiconductor device, characterized in that a general wiring process is performed for all the nets to be connected, and a detailed wiring process is performed in each unit wiring area, using the partial wiring segments obtained by the general wiring process as already routed. Method.