JPH03278377A - Digital audio tape recorder with queuing/reviewing function - Google Patents

Abstract

PURPOSE:To simplify configuration and to perform queuing/reviewing reproduction by providing a means which sets an error flag at digital data in which coincident number of parity is small and blocks the reproduction of the digital data, and a means which performs the interpolative reproduction of the digital data in which the coincident number of parity is large. CONSTITUTION:Detection circuits 48a-48g which set the error flag on data from either one magnetic head by checking the W1, W2, and P of the data read out by magnetic heads A, B and sending a check result to a CPU are provided. When the coincident number of parity from the magnetic head A exceeds that from the magnetic head B, L is outputted, and when the latter exceeds the former, H is outputted to a control circuit 50, and the magnetic head A when a switching signal shows the L and the magnetic head B when it shows the H can be selected. In such a manner, it is possible to perform the queuing/reviewing reproduction with the simple configuration.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital audio chip recorder with a cue/review function, and particularly to a digital audio chip recorder that performs cue/review playback using parity.

[Conventional technology] Due to the rapid progress of digital technology, digital technology has come to be actively used in audio equipment, which until now was an application field of analog technology.In particular, digital technology that can not only playback but also record Audio chi recorder (
(hereinafter referred to as DAT) is attracting a lot of attention.

This DAT not only eliminates problems inherent to analog technology such as wow and flutter, hiss, and modulation noise, but also
It has the advantage of having a wide dynamic range of dB or more and exhibiting flat characteristics over a wide frequency band. Also, unlike conventional analog cassette tape recorders, a large capacity space is secured to store subcodes that carry various information, separate from the part where music is recorded, making it easy to perform high-speed searches and editing. It has the advantage of being able to

DATs with many advantages include R-DAT, which uses a rotating head, and 5-DAT, which uses a fixed head.
Two formats of AT are known, but the format of R-DAT in particular has been standardized, and research and development is actively being carried out to commercialize it.

In this R-DAT, data is digitized and stored in a track that is strongly tilted 6@ with respect to the direction of travel of the magnetic tape, and the track has a PCM area that stores digitized audio data (PCM). In addition, it is comprised of a SUB area for storing subcodes consisting of information such as the beginning of a recorded song and a song number, and an ATF area for recording an ATF signal for tracking. As shown in FIG. 3, these multiple areas constituting a track contain 8 bits of 5YNC data for data synchronization,
ID code data W for specifying the frame address
1 is 8 bits, block address data W2 for identifying the block is 8 bits, parity P (P is simple parity, P-Wl+W2) is 8 bits, 32 symbols with 8 bits as one symbol, totaling 256 bits of data. It is composed of a plurality of blocks, the SUB area is composed of two 8 blocks, and the PCM area is composed of 128 blocks.

Furthermore, this R-DAT employs an interleave format in which data is distributed and recorded over two tracks in order to minimize the effects of continuous data errors, ie, burst errors. In this interleave format, two tracks with different azimuth angles (hereinafter, +azimuth track and -azimuth track, respectively) are used.
(referred to as the azimuth track), one track records even numbers of the L channel and odd numbers of the R channel, and the other track records even numbers of the R channel and odd numbers of the L channel. By pairing and playing the L channel and R channel, the R
- Even if an error occurs in one of the two magnetic heads of the DAT, it is possible to reproduce the sound without interruption (see FIG. 4).

In this R-DAT, the drum rotation speed during normal playback is 2000 rpm, and the magnetic tape speed is 8.15 mm/
s and the conventional analog cassette tape recorder's 4.76
Since it is extremely slow compared to cm/s, high-speed search is essential.

However, such a high-speed search is often inconvenient when using a magnetic tape in which no start ID, which is subcode data indicating the beginning of a song, is recorded. Therefore, an R-DAT has been developed that has a cue/review function that allows you to cue while listening to the reproduced sound.

[Problems to be Solved by the Invention] However, cue/review playback in the conventional R-DAT requires an envelope circuit to perform amplitude comparison in order to adopt either of the digital data read from the two magnetic heads. There is a problem in that an attached circuit is required, which complicates the system configuration.

FIG. 5 shows the scanning tracks of two magnetic heads A and B (with respective azimuth angles of + and -) in the cue/review function and the reproduction envelope waveforms at that time. The recording track shown in FIG. 5(a) is normally reproduced (x
In the case of I P B), the magnetic heads A and B read the digital data by scanning the +azimuth track and -azimuth track, respectively, as shown in FIG. 5(b), so the reproduction envelope waveform is as shown in FIG. 5(e). ) as shown in A, B
A waveform with almost the same amplitude is obtained. However, in double speed playback (x 2 P B), the magnetic head A scans the +azimuth track as shown in FIG. 5(c),
The magnetic head B also scans the +azimuth track. Therefore, digital data cannot be read by scanning the +azimuth track by magnetic head B, and its envelope waveform is large when reading by magnetic head A, as shown in FIG. Sometimes it gets smaller. Therefore, the envelope circuit must select only the digital data from the magnetic head A to reproduce the audio, leading to the above-mentioned complicated system configuration.

The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide a cue/review circuit that eliminates the need for external circuits such as an envelope circuit, simplifies the system configuration, and enables reliable cue/review playback. DA with review function
The goal is to provide T.

[Means for Solving the Problems] In order to achieve the above object, the DAT with a queue/review function of the present invention extracts parity from digital data alternately read from a magnetic tape by first and second magnetic heads. Parity calculating means for calculating, parity determining means for determining whether the calculated parity matches a pre-given parity, and the digital data read by the first and second magnetic heads respectively match. a counting means for counting the number of matched parities, a comparing means for comparing the size of the matched parity numbers, and a means for preventing the reproduction of digital data by setting an error flag on the digital data for which the matched parity number is small. and means for interpolating and reproducing digital data having a large number of matched parities.

[Function] The DAT with cue/review function of the present invention has such a configuration, and by comparing the envelope waveforms of digital data alternately read from the magnetic tape by the first and second magnetic heads, Rather than employing any one of the digital data, the parity of the read digital data is detected and the digital data with the greater number of matching parities is employed.

That is, the parity determining means determines whether or not the parity P' calculated by the parity calculating means matches the parity P (the sum of each bit of Wl and W2) given in advance at the time of recording. When reading digital data from a magnetic tape using a magnetic head, if no read errors occur, the parities will match, and the digital data read at this time is confirmed to be correct digital data. means. After two tracks of digital data on the magnetic tape are read out, the number of matching parities is compared, and the digital data from the magnetic head with a smaller number of matching parities, that is, with lower data accuracy, is compared. If reproduction of this digital data is prevented by setting an error flag, it is possible to interpolate and reproduce only the digital data with a large number of matched parities, that is, the digital data that has been accurately read, and perform cue/review.

[Embodiment] Hereinafter, a preferred embodiment of a DAT with a queue/review function according to the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of the overall configuration in this embodiment.

A control signal is sent from the CPU10 via the CIO data bus to the mode control circuit 12 that defines the operation of the internal circuit,
Modes such as normal playback, queue/review, or high-speed search are set.

In normal playback mode, the drum rotation speed is 2000.
rpm, and when playing cues, it is 2 to 3 times that,
Furthermore, during high-speed search (F F), 2 during normal playback
The rotation speed will be approximately 00 times. From the synchronization bit in the digital data recorded on the magnetic tape, a P (not shown) is generated.
PCM data read from the track by the two magnetic heads A and B is input to the demodulation circuit 14 in accordance with the synchronized clock generated by the LL circuit. The demodulation circuit 14 has a synchronization detection circuit and a 10-8 converter, and detects the synchronization signal SYNC in the input PCM data block (see FIG. 3), resets the symbol counter 16, and detects the input PCM data block. Transform the data by 10-8. The symbol counter 16 counts the synchronization clock and counts a total of 35 symbols (8 bits per symbol) of ID code data W1, block address data W2, parity P, and PCM data input after the synchronization signal 5YNC of the PCM data block. . The count value of this symbol counter 16 is 2, that is, the block address data W of the data block
2 is detected, the 7 bits indicating the block address in the 8-bit block address data W2 output from the demodulation circuit 14 are input to A5 to A5 of the address counter 18.
It is set to A11. Here, address counter 18
The lower 5 bits A o "" A4 are the counter outputs that count 32 symbols of PCM data, while the upper 2 bits AI2 to A13 are the switching signals of the magnetic heads A and B and their 1/2 frequency divided signal as a. This is a bit that is useful.

Therefore, when the first symbol of PCM data is input, the bit RAM 20 in the storage capacity 128 is accessed by the output of the address counter 18, and the PCM data symbol output from the demodulation circuit 14 is written into the RAM 20.

Then, while the data read from the magnetic head is being written to the bits 64 in the half of the RAM 20, the remaining half 64 bits are being written.
The interleave address control circuit 22 accesses the bit in 4 based on the sampling frequency specified by the mode control circuit 12, and the PCM data stored at the address specified by the interleave address control circuit 22 is output to the output data conversion circuit. Sent to 24th. This output data conversion circuit 24 has an 8-16 converter and an average value interpolation circuit, and after converting the input 8-bit data to 16-bit data, it interpolates intermediate erroneous data from the preceding and following data. Performs value interpolation and outputs to the D/A converter.

Note that during normal playback, a predetermined amount of PCM data is
When stored in AM20, the FCC address control circuit 26
accesses the RAM 20 and sends PCM data to the ECC circuit 28. The ECC circuit 28 checks the C1 code from the input data and writes the corrected data into the RAM 20 again. Also, one track, that is, A,
When all the data read by either magnetic head B is stored in the RAM 20, the ECC address circuit 26
The ECC circuit 28 checks the C2 code and corrects the data.

On the other hand, during cue/review playback, the ECC circuit 28 does not check C1 and C2, the PCM data stored in the RAM 20 is read out by the interleave address control circuit 22, and the output data conversion circuit 24 performs average value interpolation. It is then output to an A/D converter and reproduced.

During recording, a control signal instructing the recording mode and sampling frequency is sent from the CPU 10 to the mode control circuit 12, and the internal circuit is set to the recording mode. Then, the A/D converted data according to the designated sampling frequency is input to the input data conversion circuit 30, which separates the 16-bit data into 8-bit data. The input data converted into 8 bits is interleaved into bits and written into 64 bits of the RAM 20 by the interleave address control circuit 22 as a symbol. Furthermore, a C1 code and a C2 code are created from the written symbols by the ECC circuit 28 and stored in a predetermined area of the RAM 20 again.

Then, CPU10 selects the SU to be recorded together with the audio data.
The B code data is output to the SUB code register 32. This SUB code register 32 creates pack data including parity based on the stored SUB code data, and the created back data is sent to the RA where data supply to the magnetic head has been completed by the back address control circuit 34.
Bit 64 of M20 is written to an area for storing 01 and C2 codes. Then, a C1 code is created by the ECC circuit 28 from the written pack data, and R
It is stored in AM20.

In order to output the data written in this RAM 20 to the magnetic heads A and H, first, the symbol counter 36, block counter 38, and frame counter 4 which count the write clock FCH synchronized with the rotation of the rotating drum are used.
0 specifies the address of the RAM 20.

The data stored at the designated address is input to the modulation circuit 44 via the switching circuit 42, converted into 8-10 data, and then supplied to the magnetic heads A and B.

Note that the switching circuit 42 has Wl created by CPUl0.
, I held in the W2 parity creation data register 46
D code data W1, block address data W2, and parity P are input to the PC and sent from the RAM 20.
M data and the specified block format (
(See Figure 3).

Here, the characteristic feature of this embodiment is that Wl, W2, and P of the data read by the magnetic heads A and H are checked, and the check results are sent to the CPU10 to read the data from either of the magnetic heads. A detection circuit 48 is provided to set an error flag.

This detection circuit 48 will be explained in detail below using FIG. FIG. 1 shows a circuit diagram of the detection circuit 48. Of the PCM data converted into 10-8 by the demodulation circuit 14, 8 bits of ID code data W1, 8 bits of block address W2, and 8 bits of parity P are held in the W register 48a1W2 register 48bSP register 48c, respectively. That is, each register is composed of a D-type flip-flop OFF, and the count-up signal every 8 bits from the binary counter 14a is input to its clock terminal, so that Wl and W2P are sequentially input to the next stage register. , W1 data is held in the final stage W register 48a, W2 data is held in the central W2 register 48b, and P data is held in the first stage P register 48c. on the other hand,
The PCM data is stored at the address of the RAM 20 specified by the address counter 18, as described above.

Then, the W1 data held in the W register 48a and the W2 data held in the W2 register 48b are further sent to the parity calculation circuit 48d, and from these data, the parity calculation circuit 48d calculates r P--W1+W2 (for each bit of Wl and W2). ) is calculated. This parity calculation circuit 48d has eight EX-
It is composed of OR gates, and 1-bit data of W1 and W2 is input to the input terminal of each EX-OR gate. As is well known, the EX-OR gate is a logic gate that outputs 8 O levels when the inputs are equal, and outputs 8 O levels when they are different. The parity P' thus calculated from the W1 data and W2 data is output to the parity determination circuit 48e.

On the other hand, the 8-bit parity P held in the P register 48c is also output to the parity determining circuit 48e, and it is determined whether it matches or does not match the parity P' calculated by the above-mentioned parity calculating circuit 48d. That is, this parity judgment circuit 48e is composed of eight EX-OR gates and an AND gate having inverted outputs, and parity P and P' are input to two input terminals of each EX-OR gate. Therefore, the output from the parity judgment circuit 48e is "1111" when the parities P and Po match.
1111'' is output, and if the parity P and Po are not the same, the output value will be other than that. Therefore, this 8
By outputting bit data through an AND gate, 1 is output only when parity P and P- match, and 0 is output when P1P' does not match.

After the edge is detected, the output from the parity determining circuit 48e, that is, the parity match signal, is input to a parity counter 48f that counts the number of matched parities. This parity counter 48f is composed of an 8-bit binary counter in which eight T-type flip-flops TFF are connected, and the parity counter 48f is composed of an 8-bit binary counter in which eight T-type flip-flops TFF are connected.
magnetic heads A and B from the upper 2 bits AI2 to A13 of
1, that is, the H level input after being reset by both edges (rising and falling) of the switching signal (for example, a 50% duty ratio signal that is L level during the A head read period and H during the B head read period). Count signals. Therefore, the parity counter 48f counts the number of parities determined to match by the parity determination circuit 48e for each of the magnetic heads A and B. Then, the counting result is output to the comparator 48g and the parity register 48h.

Since a latch signal is input to the clock terminal of the parity register 48h at the rising edge of the switching signal of the magnetic heads A and B, that is, when switching from the A head to the B head, the parity register 48h inputs the latch signal to the clock terminal of the magnetic head A and B.
The number of matching parities of the data read from the comparator 48g
It will be output to . Therefore, the matching parity number of the data read from the magnetic head A and the matching parity number of the data read from the magnetic head B are input to the comparator 48g every frame (for two tracks), and a comparison between these is performed. It will be done. And, as a result of this size comparison, A>
B, that is, when the number of coincidence parity from magnetic head A is greater than the number of coincidence parity from magnetic head B, it outputs "L", When it is greater than the matching parity number, "H" is output to the control circuit 50. This control circuit 50 is an EX-OR circuit which inputs the output from the comparator 48g.
The gate 50a1 is composed of an AND gate 50b to which the output from the EX-OR gate 50a is input, and an OR gate 50c to which the output from the AND gate 50b is input. A switching signal for the magnetic heads A and B from the address counter 18 is input to the other input terminal of the EX-OR gate 50a.

As mentioned above, when this switching signal is "L", magnetic head A is selected, and when it is "H", magnetic head B is selected. Therefore, the output from the EX-OR gate 50a is the signal that is selected by the comparator 48g. When the comparison result is A>B and an "L" signal is output, when magnetic head B is selected, "
H", and the comparison result at comparator 48g is BAA.
When the "H" signal is being output, the signal becomes "H" when the magnetic head A is selected. That is, for data from a magnetic head that has a small number of matched parities and is not used as reproduced data, "H" is output with a delay of one frame in response to the switching signal of the magnetic head at that time. Become.

The output from EX-OR gate 50a is input to AND gate 50b. Since the cue/review mode signal from the mode control circuit 12 is input to the other input terminal of the AND gate 50b, the mode is set to cue/review.
It outputs "H" when it is "H" indicating the review mode and the output from the EX-OR gate 50a is "H".

The output from this AND gate 50b is the OR gate 50c.
and output to the output data conversion circuit 24 as an error flag signal.

Now, as mentioned above, the PCM data is stored in one half of the RAM 20 (64 bits), and during this time, the remaining 64 bits are filled with the data of one frame before, which is stored in bits.
The M data is read by the interleave address control circuit 22 and input to the output data conversion circuit 24, but at this time, based on the error flag signal output from the control circuit 50, one of the magnetic heads A and B is determined to be in error. Forcibly flag the data as an error. This output data conversion circuit 24 adopts only the correct data read from the magnetic head for which the error flag is not set, and reproduces this data by performing average value interpolation. At this time,
The data adopted is the data read from either magnetic head A or B, but the PC
Since the M data is recorded in an interleaved format, the original signal can be reproduced.

That is, as shown in FIG. 4, even-numbered L channels and odd-numbered R channels are recorded in the minus track. Therefore, for example, when reproducing the audio of the L channel, the odd-numbered data is recorded on the - track. Even if an error flag is set, the even-numbered data before and after it is correct PCM data, so the data before and after it L 2n' L 2(
, +1) < no, 1.2...) to L - (L+L)/22n+1
2n 2(n+1) enables average value interpolation.

In this way, in this embodiment, the magnetic head for reproduction is selected based on the result of the parity check, and the cue/review function is performed with a simple configuration without the need for an attached circuit such as an envelope circuit. I can do it.

[Effects of the Invention] As explained above, according to the DAT with the cue/review function according to the present invention, it is possible to perform the cue/review function reliably with a simple configuration and further improve the reliability of the DAT. Become.

[Brief explanation of the drawings] Figure 1 shows a DAT with a queue/review function according to the present invention.
A circuit diagram of one embodiment, FIG. 2 is a block diagram of the previous configuration in the same embodiment, FIGS. 3 and 4 are explanatory diagrams showing the recording format in DAT, and FIG. 5 is a diagram of the magnetic head in cue/review mode. FIG. 3 is an explanatory diagram showing a trajectory and a reproduction envelope waveform. 10 ... 12 ... 14 ... 20 ... 24 ... 30 ... 48 ... PU mode control circuit demodulation circuit AM output data conversion circuit input data conversion circuit detection circuit

Claims (1)

[Scope of Claims] Parity calculation means for calculating parity from digital data alternately read from a magnetic tape by first and second magnetic heads, and whether or not the calculated parity matches a pre-given parity. parity determining means for determining whether the digital data is read by the first and second magnetic heads; counting means for counting the number of matched parities for each of the digital data read by the first and second magnetic heads; and comparing means for comparing the numbers of matched parities. , means for preventing reproduction of digital data for which the number of matched parities is small by setting an error flag on the digital data, and means for interpolating and reproducing digital data for which the number of matched parities is large. , a cue/characterized in that it reproduces only digital data from either the first or second magnetic head.
Digital audio tape recorder with review function.