JPH03274753A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular to a semiconductor integrated circuit device having a structure including a solder joint for hermetic sealing and a solder joint for heat dissipation. The present invention relates to techniques that are effective when applied to integrated circuit devices.

[Conventional technology]

As an example of a sealing form that meets the demand for increased packaging density of semiconductor integrated circuit devices, for example, a structure as shown in FIG. 3 can be considered.

That is, a preform material made of solder E is sandwiched between a base C on which a semiconductor integrated circuit element B is mounted via a solder bump A and a cap D, and between a cap D and a semiconductor integrated circuit element B, and the state is Base C is heated to about the melting point of solder E by solder reflow treatment.
The sealing between the semiconductor integrated circuit element B and the cap D, and the formation of a heat dissipation bonding structure between the semiconductor integrated circuit element B and the cap D using the solder E are performed simultaneously.

Then, the base C of the semiconductor integrated circuit device having such a sealed structure is further mounted on a desired mounting board or the like via solder bumps (not shown), etc., and the wiring structure (not shown) formed inside the base C and the solder bumps A are attached. This is used to exchange electrical signals between the semiconductor integrated circuit element B and the outside via the semiconductor integrated circuit element B.

Incidentally, in the case of the sealing structure shown in FIG. The balance of thermal expansion in the horizontal direction is important, and the thickness of the solder E at the sealing part between the base C and cap D is set appropriately according to the diameters of the semiconductor integrated circuit element B and the solder bumps A, which are determined by the product type. Measures such as these will be taken.

On the other hand, if the thickness of the nozzle E in the sealed portion between the K-space C and the cap D is large, the airtightness of the sealed portion may be reduced due to shrinkage holes that occur in the width direction during solidification. As a countermeasure to this problem, it is possible to reduce the thickness of the solder E in the sealing portion to prevent the formation of shrinkage holes.

[Problem to be solved by the invention]

Therefore, as a countermeasure for reducing the airtightness of the sealed part, the thickness of the solder E of the sealed part is simply made smaller. If so, the thermal expansion in the thickness direction would be unbalanced, and the sealing part and the solder of the heat dissipation joint structure would harden at the same time during the cooling process during solder reflow, causing the cap D to become unbalanced.
The semiconductor integrated circuit element B is strongly restrained between the base C and the base C.

For this reason, due to the difference in thermal expansion coefficient between the cap D and the semiconductor integrated circuit element B, for example, as shown in FIG. occurs, and the solder bump A peels off from the semiconductor integrated circuit element B, making the electrical connection between the semiconductor integrated circuit element B and the outside unstable, and reducing the reliability of the operation of the semiconductor integrated circuit device. There is a problem of decreased sexuality.

As a countermeasure against thermal stress in a similar sealing structure, there is a technique disclosed in Japanese Patent Publication No. 60-34813, for example.

In other words, during solder reflow, the surface tension of the solder layer on the back of the chip lifts the chip from the substrate, and controls the melting shape of the connecting bumps that electrically connect the substrate and the chip into a columnar shape, making it more like a normal barrel. This technology aims to reduce the stress concentration at the bonding interface between the connection bump and the substrate that occurs during shaping, and improve the thermal fatigue characteristics of the bond. There is no mention of any measures to prevent airtightness in the area.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device in which thermal stress acting on solder bumps interposed between a base and a semiconductor integrated circuit element is reduced to improve operational reliability.

Another object of the present invention is to improve the airtightness of the sealed portion;
An object of the present invention is to provide a semiconductor integrated circuit device that can reduce thermal stress acting on solder bumps interposed between a base and a semiconductor integrated circuit element.

The above and other objects and novelties of the present invention? ;feature is,
This will be apparent from the description herein and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the semiconductor integrated circuit device of the present invention seals the semiconductor integrated circuit element by sealing the cap via the first solder to the base on which the semiconductor integrated circuit element is mounted via the solder bump, and This is a semiconductor integrated circuit device in which the back surface of a semiconductor integrated circuit element and a cap are connected by a second solder, and the melting point of the second solder is lower than that of the first solder.

[Effect]

According to the above-described semiconductor integrated circuit device of the present invention, for example, during the cooling process during solder reflow during sealing, the
Since the solder solidifies before the second solder, which has a lower melting point and is interposed between the semiconductor integrated circuit element and the cap, the semiconductor integrated circuit element and the solder bumps, etc.
There is no strong restriction between the base and the cap,
When the first solder solidifies, thermal deformation of the cap, semiconductor integrated circuit element, etc. is absorbed by the second solder which is still in a molten or semi-molten state.

Further, since the second solder has a low melting point and is closer to room temperature, the thermal stress generated by solidification of the second solder is also smaller.

Therefore, the thermal stress that acts on the semiconductor integrated circuit element and the solder bump due to the difference in thermal expansion coefficient between the cap and the semiconductor integrated circuit element, etc., is alleviated. The occurrence of peeling and the like is reliably avoided, the electrical connection between the semiconductor integrated circuit element and the outside via the solder bumps is stabilized, and the reliability of the operation of the semiconductor integrated circuit device is improved.

In addition, without worrying about the occurrence of thermal stress in semiconductor integrated circuit elements, solder bumps, etc., for example, the thickness of the first solder interposed in the sealing part between the base and the cap can be reduced to improve the airtightness of the sealing part. This makes it possible to improve the airtightness of the sealed portion and to reduce the thermal stress acting on the solder bumps interposed between the base and the semiconductor integrated circuit element.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a semiconductor integrated circuit device according to an embodiment of the present invention will be described in detail below with reference to the drawings.

FIGS. 1 and 2 show an example of the configuration in the assembly process of the semiconductor integrated circuit device of this embodiment in the order of steps.

First, the configuration of the semiconductor integrated circuit device of this embodiment will be explained.

For example, the base 1 made of ceramics etc. has Pb-3.6% by weight Sn (melting point 310-320°C).
A semiconductor integrated circuit element 3, on which a semiconductor integrated circuit structure having a desired function is formed, is mounted via a plurality of solder bumps 2 having the composition.

Although not particularly shown, a wiring structure is formed inside the base l and on both the front and back surfaces, and operating signals and driving power are transmitted between the semiconductor integrated circuit element 3 and the outside via the wiring structure and the solder bumps 2. It is configured so that giving and receiving can take place.

A cap 5 having a concave cross section is attached to the base 1 on which the semiconductor integrated circuit element 3 is mounted, through a solder layer 4 (first solder) formed by a solder reflow operation as described below.
The semiconductor integrated circuit element 3 is sealed inside the sealed space formed by the base l and the cap 5.

In the case of this embodiment, the solder layer 4 has a composition of, for example, Pb.
-10% by weight Sn (melting point: 275 to 300°C) solder is used.

Further, although not particularly limited, a desired metallized layer may be formed at the sealing site between the base 1 and the cap 5 for the purpose of improving wettability to the solder layer 4 as necessary. .

In this case, between the back surface of the semiconductor integrated circuit element 3 and the inner wall surface of the cap 5, a solder having a composition of In-48% by weight Sn (melting point 117° C.) is formed, for example, and the melting point is lower than that of the solder layer 4. A solder layer 6 (second solder) having a lower temperature and closer to room temperature is formed to fill the solder layer 6 (second solder) as described later, and heat generated during operation of the semiconductor integrated circuit element 3 is transferred to the solder layer 6 and the cap. It has a structure in which it is dissipated to the outside via 5.

An example of solder reflow processing in assembling a semiconductor integrated circuit device having such a structure will be explained as follows.

First, a semiconductor integrated circuit element 3 is mounted on a base 1 via a plurality of solder bumps 2.

Next, as shown in FIG.
A solder layer 4 is placed between the base 1 and the cap 5, which are equipped with
The solder preform material 4a constituting the solder layer 6 is sandwiched therebetween, and the solder preform material 6a constituting the solder layer 6 is sandwiched between the back surface of the semiconductor integrated circuit element 3 and the cap 5 and stacked.

Then, while being compressed with a desired load using a desired jig (not shown), the material is placed into a heating furnace (not shown), and heated to a temperature approximately equal to the melting point of the solder preform material 4a ()\ solder layer 4>. , the solder preform material 4a and the solder preform material 6a having a lower melting point are melted, and thereby the sealing portion between the base 1 and the cap 5 and the back surface of the semiconductor integrated circuit element 3 and the cap 5 are melted. As shown in FIG. 2, the space between the solder layer 4 and the inner wall surface of the solder layer 6 is filled with the melted solder layer 4 and the solder layer 6, as shown in FIG.

Thereafter, it is taken out from the heating furnace and cooled to solidify solder layer 4 and solder layer 6.

During this cooling, in the case of the semiconductor integrated circuit device of this embodiment, the melting point of the solder layer 4 interposed in the sealing portion between the base 1 and the cap 5 is the same as that between the back surface of the semiconductor integrated circuit element 3 and the cap 5. Since the solder layer 6 is higher than the solder layer 6 interposed between the solder layer 6 and the solder layer 6, even when the solder layer 4 of the sealing portion is completely solidified, the solder layer 6 still remains in a molten state or a semi-molten state.

That is, when the solder layer 4 and the solder layer 6 are made of solder having the same composition as in the conventional case and both solidify at the same time during the cooling process, the internal semiconductor integrated circuit element 3 and the solder bump 2 are The base 1 and the cap 5 are strongly restrained, and due to the difference in thermal expansion coefficient between the cap 5 and the semiconductor integrated circuit element 3, for example, tension is generated between the semiconductor integrated circuit element 3 and the solder bump 2. Thermal stress will be applied.

However, in the case of this embodiment, since one of the solder layers 6 is in a molten or semi-molten state, thermal deformation of the cap 5 or the semiconductor integrated circuit element 3 is absorbed by the solder layer 6 that is in a molten or semi-molten state. This prevents harmful thermal stress from acting between the semiconductor integrated circuit element 3 and the plurality of solder bumps 2.

Furthermore, since the melting point of the solder layer 6 is low and close to room temperature, the temperature difference between the solidification of the solder layer 6 and its cooling to room temperature is small, so that the thermal stress caused by this temperature difference is also reduced.

As a result, during the heating/cooling process such as solder reflow, the semiconductor integrated circuit element 3 and the solder plate 2 may peel off due to thermal stress, etc., and the electrical connection between the two may become unstable. The occurrence of problems such as stability is avoided,
The reliability of the operation of the semiconductor integrated circuit device is certainly improved.

In addition, there is no need to worry about the generation of such thermal stress (by making the thickness of the solder layer 4 sufficiently small, it is possible to prevent the deterioration of the airtightness of the sealed portion due to the generation of shrinkage holes, etc.). , it is possible to both reduce thermal stress and improve airtightness in a semiconductor integrated circuit device.

Furthermore, since a substance with a low melting point also has a low rigidity, thermal stress acting between the base 1 and the base 2 (due to thermal cycling during use of the semiconductor integrated circuit device after encapsulation) As a result, the fatigue life of the joint between the solder bump 2 and the base 1 is extended, and as a result, the reliability of the operation of the semiconductor integrated circuit device is improved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, the compositions of the first and second solders are not limited to those exemplified in the above embodiments, but other materials may be used as long as the melting point of the second solder is lower than the melting point of Ml solder. It may be a combination of

Further, the structure of the semiconductor integrated circuit device is not limited to the above embodiment.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

That is, according to the semiconductor integrated circuit device according to the present invention,
By sealing a cap via a first solder to a base on which a semiconductor integrated circuit element is mounted via a solder bump, the semiconductor integrated circuit element is sealed, and a gap between the back surface of the semiconductor integrated circuit element and the cap is sealed. A semiconductor integrated circuit device in which the melting point of the second solder is lower than the melting point of the first solder, so that, for example, the cooling process during solder reflow during sealing is In this case, the first solder, which has a higher melting point and is present in the sealed portion between the base and the cap, solidifies before the second solder, which has a lower melting point, which is present between the semiconductor integrated circuit element and the cap. , semiconductor integrated circuit elements, solder bumps, etc. are not strongly constrained between the base and the cap, and when the first solder solidifies, the second solder, which is still in a molten or semi-molten state, protects the cap and semiconductor integrated circuit elements. Thermal deformation of circuit elements etc. is absorbed.

Furthermore, since the melting point of the second solder is low and closer to room temperature, the thermal stress generated by solidification of the second solder is also smaller.

Therefore, the thermal stress acting on the semiconductor integrated circuit element and the solder bump due to the difference in thermal expansion coefficient f between the cap and the semiconductor integrated circuit element, etc., is alleviated, so that the solder bump and the semiconductor integrated circuit element are The occurrence of peeling from the semiconductor integrated circuit device is reliably avoided, the electrical connection between the semiconductor integrated circuit element and the outside via the solder bumps is stabilized, and the reliability of the operation of the semiconductor integrated circuit device is improved.

In addition, the thickness of the first solder interposed in the sealing part between the base and the cap can be reduced, without worrying about the generation of thermal stress in the semiconductor integrated circuit element and solder bumps, etc., to ensure that the sealing part is airtight. It is possible to improve the airtightness of the sealing part and reduce the thermal stress U that acts on the solder bumps interposed between the base and the semiconductor integrated circuit element.
It becomes possible to achieve both reduction and reduction.

[Brief explanation of drawings]

FIG. 1 is a schematic sectional view showing an example of a semiconductor integrated circuit device in an assembled state before solder reflow, FIG. 2 is a sectional view showing an example of a semiconductor integrated circuit device after solder reflow, and FIG. 3 is a conventional FIG. 3 is a schematic cross-sectional view showing an example of the tank bottom of the semiconductor integrated circuit device of FIG. l...Base, 2...Solder bump, 3...Semiconductor integrated circuit element, 4...Solder layer (first solder),
4a...Solder preform material (first solder), 5
... Cap, 6... Solder layer (second solder),
6a...Solder preform material (second solder). Figure 1 3: Semiconductor integrated circuit element 6: Solder layer (second solder)

Claims (1)

[Claims] 1. A semiconductor integrated circuit element is sealed by sealing a cap via a first solder to a base on which the semiconductor integrated circuit element is mounted via a solder bump;
A second
A semiconductor integrated circuit device connected with solder,
A semiconductor integrated circuit device in which the melting point of the second solder is lower than the melting point of the first solder. 2. First and second solder preform materials made of the first and second solders are sandwiched between the base and the cap and between the semiconductor integrated circuit element and the cap, respectively. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is assembled by heating and cooling to about the melting point of the first solder while the semiconductor integrated circuit device is in a state where the first solder is heated to about the melting point of the first solder and then cooled.