JPH03271721A - Active matrix circuit and production thereof - Google Patents

Abstract

PURPOSE:To obviate the generation of a line defect even if the disconnection between gate lines and source lines and the short circuit between the source lines and the gate lines arises by forming correction gate electrodes facing source electrodes via gate insulating layers and the correction gate electrodes positioned across the adjacent two electrodes. CONSTITUTION:The active matrix of thin film transistors are so formed that respective drain pads D1, D2, etc., can be the bypass passages for the gate line G10 (the same holds true of the other gate lines) in spite of addition of the correction lines 40, 50, etc., and that the correction electrodes 80, 90 etc. along the respective source lines S10, S11 can the constitute the bypasses for the source lines S10, S11. The line defect is prevented by constituting the bypass circuit in this way even if the disconnection of the gate lines G10 to G12 and the source lines S10, S11 or the short circuit, etc., at the intersected points of the gate lines G10 to G12 and the source lines S10, S11 arises.

Description

Detailed Description of the Invention: Industrial Application Field The present invention relates to an active matrix circuit such as a liquid crystal display (LCD) or an electroluminescence (EL) display using thin film transistors, and a manufacturing method thereof.

:Prior art] FIGS. 4(A) and 4(B) show examples of ellipsoidal layout of thin film transistors according to the prior art. The transistor is used in an active matrix circuit as shown in FIG.

FIG. 3 schematically shows the planar structure of an active matrix substrate, with gate lines G1, G2,
G3, . . . run vertically, and source lines S1 + S2, S3 intersect with these gate lines.
+... run and the intersections form a matrix. Drain pads D11, DI2, corresponding to each intersection
...D21, D22, ...D31, D32, ...
is located. These train pads form, for example, drive electrodes of a liquid crystal cell. An insulated gate field effect transistor Tij is arranged between each drain pad and the corresponding source line Si (i=1°2.3...) and gate line Gj (j=1.2.3...). , the voltage of the source line Si is applied to the train pad Dij according to the signal of the gate line Gj.

These insulated gate field effect transistors T11°T1
2,...T21, T22...T31, T32...
is formed of a thin film transistor using amorphous silicon or polysilicon as shown in FIGS. 4(A) and 4(B).

FIG. 4(A) is a plan view showing an enlarged portion of the transistor TI2 in FIG.
A> is a sectional view taken along line IVB-IVB.

A conventional method for manufacturing a thin film transistor will be described with reference to FIG. 4(B).

A conductor@III is formed on the glass substrate 1, and a gate electrode 3 is formed.
is patterned, and then the upper gate voltage tllii4 is further patterned. On top of that, an insulating film 5 such as SiO2, an amorphous 5i (a-3i; H) film 6 doped with hydrogen,
An n-medium type a-3i:H film 7 doped with a large amount of impurities is continuously deposited by plasma CVD and patterned into an island shape. Furthermore, an electrode metal layer is formed and source/drain electrodes 8a and 8b are patterned.

A transparent conductive film is formed and a train pad 2 is patterned. n medium size a-3i on the channel part after A: H1i7
is etched, leaving only the lower a-3t:Hl 116 to form a channel controlled by the gate electrode 3.4.

Problems to be Solved by the Invention Furthermore, when an active matrix is constructed using such thin film transistors, the following problems arise.

When a gate line G1 is disconnected during manufacturing of a thin film transistor, a line defect occurs in which a gate signal is transmitted to the gate line after the disconnection. Further, even if the gate line G1 and the source line S2 are shortened at their intersections, line defects still occur.

Furthermore, when a source line is disconnected, a vertical line defect related to the source line occurs.

An object of the present invention is to provide an active matrix circuit of thin film transistors that does not cause a line defect even if a disconnection of a gate line or a source line or a short circuit between a source line and a gate line occurs, and a method for manufacturing the same.

[Means for Solving the Problems] The present invention will be explained in detail with reference to FIG. FIG. 1 shows a conceptual diagram of an equivalent circuit in a part of the active matrix of the present invention. In FIG. 1, G10 to G12 are gate lines, S10. S11 is a source line, Ti, T2, and T3 are insulated gate field effect transistors, and D1 to D6 are drain pads that are transparent electrodes that drive liquid crystal elements or EL elements, respectively.
40.50 is a correction electrode branching from the gate line GIO, 60.70 is a correction electrode branching from the gate line Gi1 below, 82 is a correction electrode branching from the gate line Gil and arranged along the source line S10, 92 80 is a correction electrode branched from the gate line G11 and arranged along the source line Si1; 80 is a correction electrode branched from the correction electrode 40 and arranged along the source line S10; 90
is a correction electrode branched from the correction electrode 50 and arranged along the source line S11; 81 is a correction electrode branched from the correction electrode 60 and arranged along the source line S10; 91 is a correction electrode branched from the correction electrode 70 and arranged along the source line 511. The correction @, located along the pole. All the correction electrodes are formed at the same time when the gate lines G10, G11, . . . are formed.

A correction electrode 40 branching from the gate line G10 is connected via switches 41 and 42 to adjacent drain pads D1 and D2 driven by the gate line G11. Correction t&50 is also connected to adjacent drain pads D2 and D3 driven by gate line G11 via switches 51 and 52.

A correction pole 60 branching from the gate line G11 is connected to adjacent drain pads D4 and D5 driven by the gate line G12 via switches 61 and 62. The correction pole 70 is also connected via switches 71 and 72 to adjacent drain pads D5 and D6, which are driven by the gate line G12.

That is, as in the equivalent circuit shown in FIG. 1, correction lines are added so that each train pad can serve as a bypass path for gate line G10 (the same applies to other gate lines), and correction lines are added along each source line. An active matrix of thin film transistors is formed so that the electrodes can constitute a bypass for the source line.

: Effect] Here, if the gate line G10 is disconnected at the point (■) during manufacturing, if the switch 62 and the switch 71 are closed, the gate signal will be the correction electrode 60 - switch 62 - drain pad D5 - switch 71 - correction amount [ 70 bypass passages. Therefore, only the drain pad D5 becomes a point defect, but line defects can be prevented.

In an actual thin film transistor, these switches 41.4
2.51.52.61.62.71.72 are all connected to the electrodes connected to the gate line GIO1Gll and the drain pads t'! It is constructed with a structure in which gates fl and gate insulating film are opposed to each other and are in an open state. In order to close these switches 41, 42, 51, 52, etc., a method is used in which the gate insulating film is destroyed by irradiation with a high-density energy beam such as a laser beam, and the opposing electrodes are short-circuited.

On the other hand, an example of the intersection of the gate line and the source line is G.
If the intersection 0 of 11 and S11 was shorted during manufacturing,
If parts 0 and (2) on both sides of the intersection 0 of the gate line G11 are disconnected by irradiation with a laser beam or the like, and then the switches 62 and 71 are closed by destroying the insulating film with a laser beam or the like, the gate signal will be corrected t&60. - Switch 62 - Drain pad D5 - Switch 71 - Correction t Transmitted in the bypass path of pole 70.

Furthermore, if the source line S11 is disconnected at the [F] part, a laser beam or the like is irradiated to the [F] and 0 parts before and after the disconnection part O to destroy the insulating film, and the source line S11
1 and the correction amount [! 92 to create a bypass for the disconnection part O. If left as is, the source and gate will be shorted, so
A laser beam or the like is used to disconnect the gate line G11 on the left and right sides of the intersection 0 with the source line S11, and the switch 62
．． 71 is short-circuited with the drain pad D5 using a laser beam. In this way, D5 becomes a point defect, but a line defect due to a disconnection of the source line can be prevented.

Furthermore, if the intersection (3) between the correction t-electrode 70 and the source line S11 is short-circuited during manufacturing, no defects will occur if the correction is made by cutting the 0 part of the pole 70 with a laser or the like.

Figures 2 (A>, (B), and (C)) of this embodiment show the planar structure of an embodiment of the active matrix of the thin film transistor according to the present invention, the patterns of the gate line and the correction electrode, and the cross sections of the thin film transistor and the correction electrode. The reference numbers indicating the structure are the same as those in the equivalent circuit conceptual diagram of FIG. 1 for the same functions.

FIG. 2(B) shows the pattern of gate lines on the substrate.As shown in the figure, one gate line G11 has a correction electrode 6.
0.70.81.82.91.92... are added and patterned. Similar correction electrodes are branched and formed on all gate lines.

On this gate line pattern, as shown in FIG. 2(C), gate insulation II! 115, depositing a semiconductor film 116 to form a channel region of a transistor, a source/gate intersection region,
As shown in FIG. 2(A), a semiconductor 111101.102.103.1 is formed in an island shape at the intersection of the source and correction electrodes.
Pattern 04. At this time, the gate insulating film is left on the entire surface, and the source lines S10, S11... and the train electrodes are formed.

Drain pads D1, D2, D3, . . . are formed.

The correction @ 'jliii 40 shown in Figure 1 is the 42
and 41, the drain pad D2 is arranged to face DI with the gate insulating film interposed therebetween. Similarly, correction pole 50 is connected to drain pad D at its 52 and 51 portions.
3 and D2 are arranged to face each other with a gate insulating film interposed therebetween. In FIG. 2 (A>), the correction electrode 60 is arranged so that its portions 62 and 61 face the drain pads D5 and D4 with the gate insulating film interposed therebetween. and 71 are arranged to face drain pads D6 and D5 with the gate insulating film interposed therebetween. Therefore, when manufacturing a thin film transistor, the correction electrode 4
0.50.60.70 are drain pads D1, D2, D
3, D4, D5, and D6 are insulated. That is,
Switches 41.42.51.52 in the conceptual circuit diagram of Figure 1
．． This is equivalent to 61, 62, 71, and 72 being open.

Further, from the correction pole 40.50, the correction pole 80° and 90 are formed by branching, respectively, and the gate line G I H:
Ha, correction TF! 82 and 92 are formed on the correction electrodes 60 and 70 by branching off from correction poles 81 and 91, respectively. This also applies to other gate electrodes. This correction voltage [r8
As shown in FIG. 2 (A>), 0.81.82.90.91°92 is formed parallel to the source line with an insulating film interposed therebetween.

Here, if the gate line G10 is disconnected at the point (■) during manufacturing, 62 of the correction electrode 60 and the correction electrode 1ii70 are disconnected.
A laser beam is irradiated to the part 71 of the gate insulating film in that part to destroy the correction electrode 60 and the train pad D5.
and at the same time correct the pole 70 and drain pad D.
5, the drain pad D5 becomes a bypass path, and the gate signal is transmitted through the path of correction t1#160-62-drain pad-D5-71-correction t&70.

Therefore, only the drain pad D5 becomes a point defect, but line defects can be prevented.

On the other hand, the intersection of the gate line and the source line, for example, G
If the intersection 0 of 11 and S11 was shorted during manufacturing,
The portions O10 on both sides of the intersection 0 of the gate line G11 are disconnected by irradiation with a laser beam, etc., and the gate insulating film is destroyed in the same way at the portions 62 of correction t&60 and 71 of correction tN70 with a laser beam, etc. Drain pad D5
If short-circuited, the gate signal is transmitted through the path of correction electrodes 60-62-drain pads D5-71=correction pole 70.

Furthermore, if the source line 311 is disconnected at the O part, a laser beam or the like is irradiated to the [F] and 0 parts before and after the disconnection part O to destroy the insulating film, and the source line S11 and the correction are made as much as possible. 92 to create a bypass for the disconnection part (■). If left as is, the source and gate will be short-circuited.
．． 62.
The portion 71 is irradiated with a laser beam or the like to short-circuit it. In this way, D5 becomes a point defect, but a line defect due to a disconnection of the source line can be prevented.

Further, if the correction electrode 70 is short-circuited at the intersection (2) between the pole 70 and the source line S11 during manufacturing, no defects will occur if the part (2) of the correction electrode 70 is cut with a laser beam or the like.

Next, a method for manufacturing a thin film transistor according to an embodiment of the present invention will be described with reference to FIG. 2(C), which is a cross-sectional view of the JIC-I IC in FIG. 2(A>).

A barrel electrode film is formed on the glass substrate 111, and the correction poles 60 and others and the gate pole 112 (G11) are patterned. On top of that, an insulating Wi 115 such as 5iN-5i02, and an amorphous Si (aSi:H) film 11 doped with hydrogen.
6. N' type a-3i:H film 11 with a large amount of impurity added
7 is successively deposited by a plasma CVD method, and a semiconductor film is patterned in an island shape at the channel portion of the transistor, the source/gate intersection, and the source/correction electrode intersection. Additionally, a t1#1 metal layer is formed and source/drain poles 118a-118b are patterned. Train pads D1, D2, . . . are formed in layers on top of this.

Finally, the n-shaped a-3i:H film 117 on the channel portion is etched, leaving only the underlying a-3t:H film 116 to form a channel controlled by the gate electrode 112.

Although the present invention has been described above in accordance with the examples, the present invention is not limited to these examples. For example, various modifications,
It will be obvious to those skilled in the art that improvements, combinations, etc. are possible.

1 Effects of the Invention] As explained above, according to the present invention, even if a disconnection of the gate line or source line or a short circuit at the intersection of the gate line and the source line occurs during manufacturing, the gate correction electrode and the train pad Line defects can be prevented by configuring a bypass circuit.

[Brief explanation of drawings]

Fig. 1 is a conceptual diagram of an equivalent circuit showing the principle of the present invention, Fig. 2 (A), (B), and (C) are a plan view and a sectional view showing an embodiment of the present invention, and Fig. 3 is a FIGS. 4(A) and 4(B), which conceptually illustrate an active matrix circuit, are a plan view and a sectional view of a conventional active matrix thin film transistor portion. In the figure, T1-T3 Dl-D6 G10, G11,...S10. S11,... 40, 50, 60°90.91.92 1 2 5 6 7 8a Insulated gate field effect transistor drain pad gate line source line gate electrode 70.80.81.82, correction polar substrate gate electrode gate Insulating film Semiconductor film (channel layer) Semiconductor film (contact layer) Source electrode 18b Drain electrode or higher

Claims (2)

[Claims] (1) In an active matrix including a thin film transistor in which a gate electrode layer, a gate insulating film, a channel layer, and a source/drain electrode layer are laminated on a substrate, and an electrode pad driven by the thin film transistor, the gate electrode is connected to the gate An active matrix having a correction gate electrode facing the source electrode with an insulating layer interposed therebetween, and a correction gate electrode formed so as to straddle between two adjacent electrode pads. (2) In a method for manufacturing an active matrix of a thin film transistor by laminating a gate electrode layer, a gate insulating film, a channel layer, a source/drain electrode layer, and an electrode pad on a substrate, when forming the gate electrode on the substrate. A method for manufacturing an active matrix comprising the step of integrally forming with the gate electrode a correction gate electrode that faces the source electrode with the insulating layer interposed therebetween, and a correction gate electrode that straddles between two adjacent electrode pads. .