JPH03267817A - Logic circuit and semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To attain low power consumption of an NTL circuit, an SPL circuit and an ECL circuit or the like by providing a variable impedance means as a collector load of an input transistor(TR). CONSTITUTION:A variable impedance means ZV is adopted for the collector load of an input TR TN. The impedance of the variable impedance means ZV is selected to be a 1st value when the input TR TN is energized and to be a 2nd value lower than the 1st value when the input TR TN is not energized. Thus, the power consumption of the NTL(Non Threshold Logic) circuit, the SPL(Super Push-pull Logic) circuit and the ECL(Emitter Coupled Logic) circuit or the like is reduced without disturbing the fast speed operation.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to logic circuits and semiconductor integrated circuit devices, and relates to logic circuits and semiconductor integrated circuit devices.
Non-Threshold Logic) circuits and SPL (Super Bunschable Logic: S
upper push-put
c>Circuit and ECL (EmitterCoupled L, Ogi
c) The present invention relates to a technology that is particularly effective when applied to circuits and high-speed logic integrated circuit devices having these logic circuits as a basic structure.

[Conventional technology]

There is a non-threshold circuit (hereinafter referred to as an NTL circuit) which receives a relatively small amplitude digital input signal and performs a high-speed logic operation.

There are also high-speed logic integrated circuit devices that have these NTL circuits as their basic configuration, and there are high-speed computers that are constructed from such high-speed logic integrated circuit devices.

As illustrated in FIG. 21, the NTL circuit includes a phase dividing circuit consisting of a bipolar transistor (hereinafter simply referred to as a transistor) Tl that receives an input signal I, its collector resistor R1, and its emitter resistor R2, Furthermore, an output emitter follower circuit is provided for transmitting the inverted output signal of the phase dividing circuit, that is, the collector voltage Vc of the transistor Tl, as the output signal vO of the circuit. This NT
In the L circuit, the input signal Vl and the output signal VO have relatively small signal amplitudes, such as 0.6 square meters.

As a result, the time required to charge and discharge the stray capacitance or load capacitance of each node due to level changes of input and output signals is shortened, and the operation speed of the logic circuit is correspondingly increased.

By the way, in the above NTL circuit, when the input signal Vl is changed to low level and the output signal VO is changed to high level, the output load capacitance CL coupled to the output terminal is as follows.
It is actively charged via the output transistor T2. Therefore, the high level change of the output signal vO is made faster, thereby reducing the propagation delay time for the input signal VlO of the logic circuit to change to the low level. However,
When the input signal VI changes to high level and the output signal VO changes to low level, the output load capacitance Ct is passively discharged via the emitter resistor R4 of the output transistor T2. Therefore, the low level change of the output signal 0 is caused by the capacitance of the output load capacitance CL and the resistance R.
is slowed down according to a time constant determined by the resistance value of 4,
This lengthens the transmission delay time for a high level change of the input signal VI of the logic circuit.

In order to deal with this, prior to the present invention, the inventors of the present application developed a so-called super Buchscheple logic circuit (hereinafter referred to as an SPL circuit) in which the resistor R4 of the NTL circuit was replaced with an active pull-down circuit.
I have completed the patent application.

As illustrated in FIG. 22, the SPL circuit includes an active pull-down circuit centered around a transistor T6 provided as an emitter load of an output transistor T5. A bias voltage immediately before the transistor T6 is turned on is applied to the transistor T6 by a bias circuit including the transistor T4 and the resistor R7. Furthermore, a capacitor C2 and a resistor R are connected to the base of the transistor T6.
The differential signal of the non-inverted output signal of the phase division circuit is transmitted through the differential circuit consisting of 7. As a result, the transistor T6 is temporarily turned on when the input signal Vl is changed to a high level, and the output load capacitance CL is actively discharged via the transistor T6. As a result, the low level change of the output signal VO is accelerated, and the transmission delay time for the high level change of the input signal Vl of the logic circuit is reduced. In addition, the transistor T6, which serves as the emitter load of the output transistor T5, is normally turned off and is temporarily turned on only when the input signal I changes to high level, which reduces the power consumption of the logic circuit. will be significantly reduced.

Regarding NTL circuits, for example, Japanese Patent Application Laid-Open No. 6312461
It is described in Publication No. 5. Furthermore, the SPL circuit is described in, for example, Japanese Patent Application No. 1-199400.

[Problem to be solved by the invention]

The inventors of the present application developed a high-speed logic integrated circuit device using the above-mentioned SPL circuit, and encountered the following problems in the process of promoting higher integration and lower power consumption.

That is, in the SPL circuit described above, an operating current normally flows through the transistor T3 that constitutes the phase division circuit and the transistor T4 that constitutes the bias circuit. Therefore, in order to further reduce the power consumption of the SPL circuit, it is necessary to increase the resistance values of resistors R5, R6, and R7 to reduce the normal current flowing through the transistors. Of these, regarding resistor R7,
Even if the resistance value is increased, the effect on the transmission delay time of the logic circuit is small (Also, as for the resistance R6, the effect can be suppressed by adding a speed amplifier capacitor, for example. However, the effect of the resistance R6 can be suppressed by adding a speed amplifier capacitor. As for When the signal, that is, the collector voltage Vc of the transistor T3 is changed to a high level and the floating capacitance fCC is passively discharged via the resistor R5, the rise of the collector voltage Vc is delayed, and thereby the input signal Vl of the logic circuit is The transmission delay time for a low level change is lengthened.

Here, the capacitance value of the stray capacitance Cc is 10 pF (Picoff 1
Rand). For this reason, for example, the power consumption per gate of an SPL circuit can be reduced to 0.1 mW (milliwand).
If the resistance value of the collector resistor R5 is 20 Ω (kilohm), then the rise time t of the collector voltage Vc is
d reaches about 140 ps (picoseconds). This significantly limits the machine cycles of high-speed combinators, etc., which are constructed from high-speed logic integrated circuit devices, and is one of the factors that hinders higher integration and lower power consumption of high-speed logic integrated circuit devices. Become.

Incidentally, the above-mentioned problems can be solved by the NT shown in FIG.
This phenomenon occurs similarly in the L circuit and the ECL circuit shown in FIG. 23, and also in high-speed logic integrated circuit devices that have these logic circuits as their basic configuration, as well as high-speed computers and the like that are constructed from such high-speed logic integrated circuit devices. , which significantly limits the machine cycle and prevents higher integration and lower power consumption.

The above has been clarified by the inventors of the present application.

The purpose of this invention is to
The purpose of this invention is to reduce the power consumption of L circuits, SPL circuits, ECL circuits, and the like.

Another object of the present invention is to achieve higher integration and lower power consumption of a high-speed logic integrated circuit device whose basic configuration is an NTL circuit, an SPL circuit, an ECL circuit, etc. The goal is to speed up the machine cycles of high-speed computers, etc.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, variable impedance means is employed as the collector load of the input transistor. The impedance of the variable impedance means has a first value when the input transistor is in a conductive state, and a second value lower than the first value when the input transistor is in a non-conductive state. controlled as follows.

More specifically, the variable impedance means includes a switch means whose operation is controlled by an input signal supplied to the input transistor, and a level setting means. The switching means includes, for example, a transistor whose control terminal is adapted to receive the input signal. Further, the level setting means includes, for example, a resistive element and/or a diode element.

According to the above means, the stray capacitance coupled to the collector node of the input transistor is charged to a value of v12 lower than the first value in response to the non-conducting state of the input transistor. This is carried out at high speed by variable impedance means. On the other hand, the stray capacitance is discharged at high speed by the input transistor in a conductive state, and the potential of the collector node becomes an impedance of a first value higher than the second value of the variable impedance means. Therefore, the input transistor is set so that it can operate in a non-saturated state. Therefore, charging and discharging of the collector node of the input transistor is accelerated.

Therefore, by applying the present invention, it is possible to reduce the power consumption of NTL circuits, SPL circuits, ECL circuits, etc. without hindering their high-speed operation. As a result, it is possible to promote higher integration and lower power consumption of high-speed logic integrated circuit devices, etc. whose basic configuration is these logic circuits, and to speed up the machine cycles of high-speed computers, etc., which are constructed using high-speed logic integrated circuit devices. At the same time, its size and power consumption can be reduced.

〔Example〕

3.1. Basic configuration of logic circuit 3.1.1. NTL circuit and SPL circuit FIG. 1 shows a basic conceptual diagram of an embodiment of an NTL circuit and SPL circuit to which the present invention is applied. Further, FIG. 2 shows a basic configuration diagram of an embodiment of the NTL circuit and SPL circuit of FIG. 1. Furthermore, in Figures 3 to 5,
Basic circuit diagrams of the first to third embodiments of the NTL circuit and SPL circuit of FIG. 2 are shown, respectively, and FIG.
FIG. 5 shows an example of a signal waveform diagram of the SPL circuit shown in FIGS. Based on these figures, the NT of this example
The basic configurations and characteristics of the L circuit and SPL circuit will be explained. Note that FIGS. 1 to 5 partially show a common part of the NTL circuit and the SPL circuit, that is, a part related to the phase division circuit.

The logic circuits shown in the following embodiments are installed in high-speed logic integrated circuit devices constituting high-speed computers and the like, although the logic circuits are not particularly limited. Although not particularly limited, these logic circuits and the circuit elements that constitute them, together with other logic circuits installed in high-speed logic integrated circuit devices and the circuit elements that constitute them, can be made of a single semiconductor such as single crystal silicon. Formed on a substrate. In the diagram below,
MOSFETs (metal oxide semiconductor field effect transistors; hereinafter, in this specification, MOSFETs are collectively referred to as insulated gate field effect transistors) whose channel (bank gate) portions are marked with arrows are P-channel type. and the h channel M to which no arrow is added
It is shown separately from OSFET. Furthermore, all illustrated bipolar transistors are NPN transistors unless otherwise specified.

In FIG. 1, the NTL circuit and the SPL circuit of this embodiment both include a phase division circuit based on an NPN type input transistor TN, although this is not particularly limited. A predetermined input signal Vl is supplied to the base of the transistor TN from a pre-stage circuit (not shown) of the high-speed logic integrated circuit device. Here, the input signal (1) is a digital signal having a relatively small signal amplitude, such as 0.6V, although it is not particularly limited.

A predetermined variable impedance means Zv is provided between the power supply voltage VCC on the high potential side (the first power supply terminal to which the first power supply voltage is supplied) and the collector of the input transistor TN. Also, transistor T! A floating capacitance of 1 cc caused by the base capacitance of the output transistor provided in the subsequent stage, related wiring capacitance, etc. is coupled between the collector of the transistor 1 and the ground potential of the circuit. On the other hand, the emitter of the transistor TN and the low potential side tJ+ are connected to the voltage VEE (second voltage f
An emitter resistor RE is provided between the second power supply terminal (to which the M voltage is supplied), and the emitter resistor RE
A predetermined speed amplifier cavantor Cs is provided in parallel with. Here, the resistance value of the emitter resistor RE is N
The value of the operating current of the phase divider circuit of the TL circuit and the SPL circuit during normal operation should be below a predetermined value (sufficiently large).

In this embodiment, the variable impedance means Z■
The impedance of the input signal VlOLm is selectively changed to the logical level of the corresponding input signal VlOLm.

That is, when the input signal v1 is set to a high level, the impedance of the variable impedance means Z2 is made sufficiently large so that the value of the operating current flowing through the transistor TN and the emitter resistor RE is below a predetermined value. At this time, the value of the impedance is required to set the collector voltage Vc of the transistor TN to a predetermined low level, and has no meaning in an open state where the impedance is infinite. Vl
is set to low level, the variable impedance means Z
The impedance of v is made sufficiently small to rapidly charge the stray capacitance Cc and keep the transmission delay time of the NTL circuit and SPL circuit below a predetermined value. At this time, the value of the impedance may be a zero impedance state corresponding to a so-called shortened state, thereby reducing the transmission delay time for changes in the low level and high level of the input signal Vl of the NTL circuit and the SPL circuit. , its power consumption can be reduced.

By the way, the variable impedance means 2V in FIG. 1 is not particularly limited, but as shown in FIG. Means LS
and switch means SW provided in parallel. Among these, the switch means SW has an input signal V at its gate, as illustrated in FIGS.
It can be constructed from a 1 m P-channel MOSFET Qp that receives l. Further, the level setting means LS may be a third level setting means, for example.
FyJ or collector resistance Re as shown in FIG.
or a Zener diode with a predetermined forward voltage [)
Alternatively, as shown in Figure $5, it may be a series circuit of a collector resistor Re and a Zener diode Dc. In these examples, MOSFETQ
Although not particularly limited, p is designed to have a threshold voltage corresponding to approximately the intermediate value between the absolute values of the low level and high level of the input signal Vl.

When the input signal Vl is changed to a high level, the switch means SW, that is, the MOSFET Qp is turned off,
Input transistor TN is substantially turned on. Therefore, the collector voltage Vc of the transistor TN is
As illustrated in the figure, the level setting means LS, that is, the voltage drop of the collector resistor RC or the Zener diode [
) is set to a predetermined low level determined by the forward voltage of c. At this time, the charge charged in the collector stray capacitance Ce of the transistor TN is actively discharged via the transistor TN having a comparatively large conductance. Then, the speed amplifier capacitor Cs provided in parallel with the emitter resistor R[:
This has the effect of accelerating this discharge operation.

On the other hand, when the input signal Vl is changed to low level, the input transistor TN is in a substantially cut-off state,
MOSFETQp is turned on. Therefore, the collector stray capacitance jicc of transistor TN is equal to that of MOSFET
It is actively charged through Qp, thereby causing the collector voltage Vc to rapidly rise to a high level similar to the power supply voltage VCC, as illustrated in FIG.

FIG. 6 shows an NTL circuit and an SP circuit to which this invention is applied.
A partial basic circuit diagram illustrating another embodiment of the L circuit is shown.

In FIG. 6, the phase division circuits of the NTL circuit and the SPL circuit are constructed based on a PNP type input transistor Tp. low potential side power supply voltage VCC<first power supply terminal to which the first power supply voltage is supplied) and the transistor T
Level setting means consisting of a collector resistor Rc is provided between the collector of p and the collector resistor RC.
An N-channel MOSFET QN, which receives an input signal V1 at its gate, is provided in parallel with the MOSFET QN. On the other hand, the power supply voltage VEE (
An emitter resistor RE is provided between the second power supply terminal (a second power supply terminal to which a second power supply voltage is supplied), and a predetermined speed-up capacitor Cs is further provided in parallel with the emitter resistor RE. Needless to say, the collector resistance R
The resistance values of c and emitter resistor RE are made sufficiently large so that the value of the operating current of the phase division circuit of the NTI, circuit, and SPL circuit during normal operation is equal to or less than a predetermined value. Also, M
OS FET Q N is designed to have a threshold voltage corresponding to approximately the intermediate value between the absolute values of the low level and high level of the input signal Vl.

When the input signal ■■ is changed to low level, the MOSF
ETQN is turned off, and the λ transistor Tp is substantially turned on. Therefore, transistor Tp
The collector voltage Vc of is set to a predetermined high level determined by the voltage drop across the collector resistor Rc. At this time, the charge charged in the collector stray capacitance Cc of the transistor Tp is actively discharged via the transistor Tp having a relatively large conductance.
Further, by adding a speed amplifier capacitor Cs, this discharge operation is accelerated. On the other hand, when the input signal Vl is changed to high level, the input transistor Tp is in a substantially cut-off state, and the MOSFET
QN is turned on. Therefore, the collector stray capacitance Cc of the transistor Tp is MOS FET Q
The collector voltage VC is charged to a negative potential through N, thereby rapidly bringing the collector voltage VC to a low level like the power supply voltage VCC. As a result, the NTL circuit and SP of this embodiment
Even in the L circuit, effects similar to those of the NTL circuit and SPL circuit of the embodiments shown in FIGS. 1 to 5 can be obtained.

3.1.2. ECL circuit FIG. 13 shows a basic conceptual diagram of an embodiment of the ECIIJ circuit to which the present invention is applied.

In FIG. 13, the ECL circuit includes a current switch circuit based on, but not limited to, a pair of differential transistors Tel and Tc2. Among these, the input signal Vl is supplied to the base of one transistor TCI (input transistor), and the predetermined reference potential VBB is supplied to the base of the other transistor TC2. here,
The input signal Vl is not particularly limited, but is, for example, 0.8
The reference potential VBB is approximately an intermediate potential between the high level and the low level of the human power V1.

The power supply voltage VCC on the high potential side (the first voltage I:I11 to which the first power supply voltage is supplied) and the transistor Tcl
Although not particularly limited, predetermined variable impedance means ZVl and ZV2 are respectively provided between the collectors of Tc2 and Tc2. In addition, transistors Tel and Tc
A '4L loose capacitance Cc resulting from the base capacitance of the output transistor Tol or Tf+2 provided in the subsequent stage, the related wiring capacitance, etc. is coupled between the collector of 2 and the ground potential of the circuit. On the other hand, a predetermined voltage is connected to the base between the commonly coupled emitters of the transistors T e l and Tc2 and the low potential side power supply voltage VER (second power supply terminal to which a voltage of $2 is supplied). A constant current source consisting of a transistor Ts receiving a constant voltage VS and a resistor Rs is provided. As a result, the constant current source, the transistors Tcl and Tc2, and the pair of variable impedance means ZVI and ZV2 constitute a current switch circuit that uses the reference potential VBB as a logic threshold.

The non-inverted output signal of the current switch circuit, ie, the collector voltage Vc2 of the transistor Tc2, is passed through an output emitter follower circuit consisting of a transistor Tol and a resistor RoI, although not particularly limited, to become the non-inverted output signal VO1 of the ECL circuit.

Further, the inverted output signal of the current switch circuit, that is, the collector voltage Vcl of the transistor Tcl, is
It passes through another output emitter follower circuit consisting of D2 and resistor Rn2 and becomes the inverted output signal VO2 of the ECL circuit.

In this embodiment, the variable impedance means ZV
The impedance of the variable impedance means ZV2 is selectively changed according to the logic level of the corresponding input signal Vl, and the impedance of the variable impedance means ZV2 is changed depending on the inverted output signal of the corresponding current switch circuit, that is, the collector voltage Vcl of the transistor Tel, although it is not particularly limited. Selectively changed according to level. That is, when the input signal Vl is changed to a high level, the impedance of the variable impedance means ZVl is made sufficiently large so that the value of the operating current of the ECL circuit is below a predetermined value and a predetermined low level is obtained at the collector of the transistor Tel. Ru. At this time, the inverted output signal of the current switch circuit, that is, the collector voltage Vcl of the transistor TC1 is set to a low level, so that the impedance of the variable impedance means ZV2 rapidly charges the corresponding stray capacitance Cc, and E
The transmission delay time of the CL circuit is made sufficiently small to be below a predetermined value. On the other hand, when the input signal Vl is changed to low level, the impedance of the variable impedance hand fiZVl quickly charges the corresponding stray capacitance Cc and
The transmission delay time of the L circuit is made sufficiently small to be less than a predetermined value. At this time, the inverted output signal of the current pinch circuit, that is, the collector voltage Vcl of the transistor T c 1 is set to a high level, so that the variable impedance means Z
The impedance of V2 is made sufficiently large so that the value of the operating current of the ECL circuit is below a predetermined value and a predetermined low level is obtained at the collector of the transistor Tc2. These results, as in the several embodiments described above, reduce both the transmission delay time for the low level and high level changes of the input signal Vl of the ECL circuit, resulting in lower power consumption.

3.2. Specific configuration example of logic circuit 3.2.1. NTL circuit FIG. 7 shows a specific circuit diagram of an embodiment of the NTL circuit to which the present invention is applied. NTL for this example
The circuit is based on the basic circuit diagram shown in FIG. In the specific circuit diagram below, the power supply voltage CC on the high potential side is, although not particularly limited, the ground potential of the circuit, and the power supply voltage VEE on the low potential side is, for example, −
It is assumed to be a negative power supply voltage such as 2°OV.

In FIG. 7, although the NTL circuit is not particularly limited,
It includes a phase division circuit based on a transistor TI.

This transistor Tl is the input transistor T in FIG.
A resistor R1 corresponding to the collector resistor Re shown in FIG. 3 is provided between the ground potential of the 0 circuit corresponding to N and the collector of the transistor Tl. A P-channel MOSFET QI corresponding to the channel MOSFET Qp is provided. In these resistor R1 and MOSFET QI, a stray capacitance Cc is further coupled between the ground potential of the zero circuit constituting one variable impedance means and the collector of the transistor Tl. On the other hand, a resistor R2 corresponding to the emitter resistor RE shown in FIG. A corresponding capacitor CI is provided.

In this embodiment, the inverted output signal of the phase divider circuit, ie, the collector voltage Vc of the input transistor T1, is supplied to the base of the output transistor T2, although this is not particularly limited. The collector of this transistor T2 is coupled to the ground potential of the circuit, and an emitter load resistor R4 is provided between its emitter and power supply voltage VER. These transistor T2 and resistor R4 constitute one output emitter follower circuit, and the output signal thereof is supplied as the output signal vO of the NTL circuit to a subsequent stage circuit (not shown) of the high-speed logic integrated circuit device. The output terminal vO of the NTL circuit is further coupled with an output load capacitance Ct corresponding to the input capacitance of the corresponding subsequent circuit and the related wiring capacitance.

Input signal Vl is at high level V1. When changed to M
OSFETQI is in the off state, and the input transistor T
1 becomes a substantial on state. Therefore, a collector current 1c of Ic = (VIH-VBE)/R2 flows through the resistor R1 (here, VIE indicates the base-emitter voltage of the NPN bipolar transistor.
(Similarly below) 9 Therefore, the collector voltage Vc of the transistor TI becomes a predetermined low level of VCL = IcxR1 #(Vls VsE) R1/R2. As a result, the output signal vO of the N TL circuit is V OL −V CL −V B! # (VIHVBE) becomes low level R1/R2VICE. At this time, the electric current charged in the stray capacitance Cc is actively discharged via the transistor T1, which has a relatively large conductance, and this discharge operation is further speeded up by providing a speed-up vacuctor CI. be done. The resistance values of the resistors R1 and R2 are made sufficiently large, thereby reducing the operating current of the NTL circuit.

On the other hand, when the input signal Vl is changed to a low level VIL, the input transistor T1 becomes substantially cut off, and the MOSFET QI is turned on. therefore,
The collector voltage Vc of the transistor T1 is MOSFET
By supplying the ground potential of the circuit through QI, it becomes a high level such as VcHth90. As a result, the output signal 0 of the NTL circuit becomes a high level VOH-VCH-velE b*-VIE. At this time, the collector stray capacitance Cc of the transistor Tl is rapidly charged via the MOSFET Ql, thereby speeding up the rise of the output signal 0.

For these reasons, in this embodiment, the power consumption of the NTL circuit can be reduced without sacrificing its high-speed operation, and the high-speed logic integrated circuit device equipped with these NTL circuits can be highly integrated and have low power consumption. This will result in the promotion of electrification.

3.2.2.3 PL Circuit FIG. 8 shows a specific circuit diagram of the first embodiment of the SPL circuit to which the present invention is applied.

The SPL circuit of this embodiment is based on the basic circuit diagram shown in FIG. 3 above, and explanations of parts that overlap with this will be omitted.

In FIG. 8, although the SPL circuit is not particularly limited,
A phase division circuit based on a transistor T3 is provided.

This transistor T3 is the input transistor T of FIG.
A resistor R5 corresponding to the collector resistor Rc of FIG. 3 is provided between the ground potential of the 0 circuit corresponding to N and the collector of the transistor T3, and a resistor R5 corresponding to the collector resistor Rc of FIG. ! A P-channel MOSFET Q2 corresponding to the P-channel MOSFET Qp of J is provided. These resistor R5 and MOSFET Q2 further have a stray capacitance Cc between the ground potential of the zero circuit constituting one variable impedance means and the collector of the transistor T3.
are combined. On the other hand, a resistor R6 corresponding to the emitter resistor RE in FIG. 3 is provided between the emitter of the input transistor T3 and the liN voltage VEE. Needless to say, the resistance values of the resistor R5 and the resistor R6 are set so as to reduce the steady operating current of the SPL circuit and to reduce the constant operating current of the SPL circuit.
It is made sufficiently large to set the collector voltage Vc of No. 3 to a predetermined low level.

In this embodiment, the inverted output signal of the phase divider circuit, ie, the collector voltage Vc of the input transistor T3, is supplied to the base of the output transistor T5, although this is not particularly limited. The collector of this transistor T5 is coupled to the ground potential of the circuit, and the transistor T6 is provided between its emitter and power supply voltage VEE. transistor T
The commonly coupled emitters and collectors of 5 and T6 are:
This is the output terminal vO of this SPL circuit, and the output load capacitance cL resulting from the input capacitance of the subsequent stage circuit and the related wiring capacitance is coupled thereto. Thereby, the transistor T6 acts as an emitter load for the output transistor T5, and together with the transistor T5 constitutes one output emitter lower circuit, and acts as a pull-down confection for the output load capacitance CL.

A transistor T4 whose base receives a predetermined constant voltage VBI is provided between the ground potential of the circuit and the base of the transistor T6, although this is not particularly limited. Also,
A resistor R7 is provided between the base of the transistor T6 and the power supply voltage VEE. The base of transistor T6 is further coupled via capacitor C2 to the non-inverting output node of the phase divider circuit, ie the emitter of transistor T3. This causes the transistor T4 to connect to the resistor R7.
Together with this, a bias circuit for the transistor T6 is configured, and a bias voltage is applied immediately before this turns on. Further, the capacitor C2 constitutes a differentiating circuit together with the resistor R7, and differentiates the non-inverted output signal of the phase dividing circuit and transmits the differentiated signal to the base of the transistor T6. These transistor T4, resistor R7 and capacitor C2 are
Together with the transistor T6, it constitutes an active pull-down circuit of the SPL circuit.

When the input signal v1 is changed to high level vIH, M
OSFETQ2 is in the off state, and the input transistor T
3 becomes a substantial on state. Therefore, a collector current 1c of I cl-i (V IN -VII/R6) flows through the resistor R5. Therefore, the transistor T
The collector voltage Vc of No. 3 becomes a predetermined low level of VcL-1cxR5 I-1(VIHV8E)R5/R6. At this time, a positive pulse corresponding to a differential signal of the non-inverted output signal of the phase division circuit is transmitted to the base of the transistor T6 via a differentiator circuit consisting of a capacitor C2 and a resistor R7, and this causes the transistor T6 to temporarily turns on.

Therefore, the transistor T6 is the output transistor T
As a result, the output signal 0 of the SPL circuit becomes V OL -V CL VBE ” (VIHVIE) It is changed to a low level of R5/R6-VBE.

When the output signal VO of the SPL circuit is changed to the low level as described above, the charge charged in the collector stray capacitance Cc is rapidly extracted through the input transistor T3, and the charge charged in the output load capacitance MCL is As previously mentioned, it is rapidly drawn off via transistor T6. Therefore, the transmission delay time for a high level change of the input signal Vl of the SPL circuit is significantly reduced. on the other hand,
The resistance values of resistors R5 and R6 that constitute the phase dividing circuit are:
As mentioned above, it is made sufficiently large. Further, the transistor T6 serving as the emitter load of the output transistor T5 is temporarily turned on until the charge load of the output load capacitance CL is removed, and thereafter its conductance is reduced. As a result, the regular operating current of the SPL circuit during low level output is significantly reduced.

On the other hand, when the input signal Vl is changed to the low level vIL, the input transistor T3 becomes substantially cut-off, and the MOSFET Q2 is turned on. therefore,
The collector voltage Vc of the transistor T3 is MO8FET
By supplying the ground potential of the circuit through Q2, it becomes a high level such as 'l/(H(Q). At this time, the transistor T
A negative pulse corresponding to a differential signal of the non-inverted output signal of the phase dividing circuit is transmitted to the base of the phase divider 6 through a differentiating circuit comprising a capacitor C2 and a resistor R7. Therefore, transistor T6 quickly enters the cut-off state and acts as a high resistance load for output transistor T5.

As a result, the output signal VO of the SPL circuit is VOH−Vc
u-VIE "I-veE" is changed to a high level.

When the output signal VO of the SPL circuit is changed to a high level as described above, the collector stray capacitance 1 of the transistor T3
icc is actively and rapidly charged via MOSFET Q2, and the output load capacitor 11ct is actively and rapidly charged via output transistor T5. As a result, the transmission delay time for a low level change of the input signal Vl of the SPL circuit is significantly reduced, even though the resistance value of the collector resistor R5 is increased.

For these reasons, in this embodiment, the power consumption of the SPL circuit can be reduced without sacrificing its high-speed operation, and the high-speed logic integrated circuit device equipped with these SPL circuits can be highly integrated and low-density. This will result in increased power consumption.

FIG. 9 shows a specific circuit diagram of a second embodiment of the SPL circuit to which the present invention is applied.

The SPL circuit of this embodiment basically follows the embodiment shown in FIG. 8, and only the different parts will be explained.

In FIG. 9, the input transistor T7 constituting the phase division circuit of the SPL circuit is of a double emitter type.

On the collector side of the transistor T7, as in the case of the gJ8 diagram above, a collector resistor R5 and a P-channel MOS are connected.
A variable impedance means consisting of FETQ2 is provided, and the inverted output signal of the phase dividing circuit is transmitted through the output transistor T.
5 to the output terminal 0 of the SPL circuit. An active pull-down circuit centered around transistor T6 is provided between the emitter of output transistor T5 and power supply voltage VEE.

The first emitter of the input transistor T7 is coupled to the base of the transistor T6 via a capacitor C2 forming a differentiating circuit, although this is not particularly limited. Also,
The second emitter of the input transistor T7 and the power supply voltage VE
An emitter resistor R6 is provided between the emitter resistor R6 and a speed amplifier capacitor C3 in parallel with the emitter resistor R6. Needless to say, the resistance values of the collector resistor R5 and emitter resistor R6 are made sufficiently large to reduce the steady operating current of the spL circuit and to keep the collector voltage Vc of the transistor T7 at a predetermined low level.

For these reasons, in the SPL circuit of this embodiment, effects similar to those of the embodiment shown in FIG. By separating the emitter to which the resistor R6 is coupled and further adding a speed-up capacitor C3 to the emitter resistor R6, the responsiveness of the phase division circuit is increased and the propagation delay time of the SPL circuit is further reduced. .

Figure 1O shows the third part of the SPL circuit to which this invention is applied.
A specific circuit diagram of the embodiment is shown.

The 5PLl path of this example is the above! This basically follows the embodiment shown in Figure @8, and only the parts that are different from this will be explained.

In FIG. 10, the phase division circuit of the SPL circuit has a basic configuration of three input transistors T8 to TIO arranged in parallel, between the ground potential of the circuit and the commonly coupled collectors of these input transistors. is provided with a collector resistor R5, and in parallel with the collector resistor R5 is a 3f P-channel MOS connected in series.
FETs Q3 to Q5 are provided. These resistor R5 and MOSFETs Q3 to Q5 constitute one variable impedance means.

The inverted output signal of the phase division circuit, that is, the voltage Vc of the commonly coupled collectors of the input transistors T8 to TIO is:
The output terminal V of the SPL circuit via the output transistor T5
transmitted to O. An active pull-down circuit centered around transistor T6 is provided between the emitter of output transistor T5 and power supply voltage VEE. on the other hand,
The base of the input transistor T8 is commonly coupled to the gate of the MOSFET Q3, and is further supplied with an input signal Vll from a pre-stage circuit (not shown) of the high-speed logic integrated circuit device. Similarly, the base of input transistor T9 is MOSF
It is commonly coupled to the gate of ETQ4, and an input signal VI2 is supplied from a pre-stage circuit (not shown). In addition, the base of the input transistor TIO is commonly coupled to the gate of the MOSFET Q5, and the input signal VI
3 is supplied. Here, the input signals Vll to VI3 are
Both are assumed to have relatively small signal amplitudes, such as 0.6V.

Any of the input signals Vll to V13 is at high level vIH
When the corresponding input transistor T8~
One of the TIOs becomes substantially on, and one of the corresponding MOSFETs Q3 to Q5 becomes off.

Therefore, the inverted output signal of the phase dividing circuit, that is, the collector voltage Vc, becomes a predetermined low level of VCL s (VIHVIE) R5/R6, as in the case of the embodiment shown in FIG. 8, and thereby the output signal of the SPL circuit V
O becomes a low level such as VOL s (VIH-V8E> R5/R6VBE. At this time, the collector stray capacitance Cc is rapidly discharged via any of the input transistors T8 to TIO that are turned on. , the output load capacitance CL is rapidly discharged via the transistor T6 which is temporarily turned on.

On the other hand, input signals Vll-VI3 are all at low level vI
When changed to L, input transistors T8 to TIO are both in a substantial cutoff state, and MOSFETQ3
~Q5 are turned on all at once. Therefore, the inverted output signal of the phase division circuit, that is, the collector voltage Vc, becomes a high level such as VcH'qQ, and thereby the output signal VO of the SPL circuit becomes a high level such as VOR'VIE. At this time, the collector stray capacitance Cc is actively and rapidly charged via MOSFETs Q3 to Q5, and the output load capacitance ICt is actively and rapidly charged via the output transistor T5.

From the above, the SPL circuit of this embodiment has the above-mentioned eighth
While obtaining the same effect as the embodiment shown in the figure, VO−Vl 1+V
It functions as a three-person gate circuit corresponding to the logical formula I2+VI3.

FIG. 11 shows the fourth part of the SPL circuit to which this invention is applied.
Fruit h! An example specific circuit diagram is shown.

The SPL circuit of this embodiment basically follows the embodiment shown in FIG. 8, and only the different parts will be explained.

In FIG. 11, input transistor T3 constitutes one phase division circuit together with variable impedance means consisting of collector resistor R5 and P-channel MOSFET Q2, and emitter resistor R6. The inverted output signal of this phase division circuit, ie, the collector voltage Vc of the transistor T3, is transmitted to the output terminal 0 of the SPL circuit via the output transistor T5. An emitter load resistor R8 is provided between the emitter of the output transistor T5 and the power supply voltage VEE, and an N-channel MOSFET Q21 is provided in parallel with the emitter load resistor R8. The gate of MOSFET Q21 is coupled to the emitter of input transistor T3. Here, MOSFETQ
21 is a threshold value corresponding to approximately the intermediate value of the non-inverted output signal of the phase division circuit, that is, the absolute value of the high level and low level of the emitter voltage of the input transistor T3, respectively, minus the absolute value of the voltage VEH. Designed to have voltage.

Input signal v1 is at high level V1. When the input transistor T3 is changed to a substantially on state, the MOS
FETQ2 is turned off. Therefore, the inverted output signal of the phase dividing circuit, that is, the collector voltage Vc of the input transistor T3, is V CL "l (V IN VIE) R5/R6, as in the embodiment shown in FIG. 8 above.
As a result, the output signal VO of the SPL circuit becomes VOL "l (V In VaE) R5/R6-
It becomes a low level like VIH. At this time, the non-inverted output signal of the phase division circuit, that is, the emitter voltage VE of the input transistor T3 becomes a predetermined high level of VE u = VIn VIE, and as a result, the MOSFE
TQ21 is turned on. Therefore, the output is negative? ii
The electric charge charged to J capacitor 1ict is this MOSF
It is actively and rapidly discharged via ETQ21, thereby reducing the propagation delay time for a high level change of the input signal V1 of the SPL circuit.

On the other hand, when the input signal V■ is changed to the low level VIL, the λ transistor T3 becomes substantially cut-off, and the MOSFET Q2 is turned on. Therefore, the collector voltage Vc of the input transistor T3 becomes a high level of VcH 0, and thereby the output signal vO of the SPL circuit becomes a high level of voHI-I-vBe. At this time, the non-inverted output signal of the phase divider circuit, that is, the emitter voltage ■E of the input transistor T3 becomes a low level such as VE L -V I t, VBE, thereby turning the MOSFET Q21 off. The output load capacitance CL is actively and rapidly charged via the output transistor T5, which has a relatively large conductance. As a result, while increasing the speed of the SPL circuit, the operating current of the output limiter follower circuit is reduced, resulting in lower power consumption.

3.2.3. ECL circuit FIG. 14 shows a specific circuit diagram of an embodiment of an ECL circuit to which the present invention is applied. EC of this example
The L circuit is based on the basic circuit diagram shown in FIG. 13 above, and explanations of parts that overlap with this will be omitted.

! In the $14 diagram, the ECL circuit includes, but is not particularly limited to, a current switch circuit based on a pair of differential transistors Tll and T12. These transistors Tll and TI2 are the differential transistor Te of FIG.
1 and T c 2, respectively. transistor T
A predetermined input signal Vl is supplied to the base of ll from a pre-stage circuit (not shown) of the high-speed logic integrated circuit device. Furthermore, a predetermined reference potential VBB is supplied to the base of the transistor T12 from a constant voltage generation circuit (not shown) of the high-speed logic integrated circuit device. Here, the input signal Vl is a digital signal having a relatively small signal amplitude, such as 0.8V. Further, the reference potential VBB is approximately an intermediate value between the high level and the low level of the input signal Vl.

A collector resistor R8 is provided between the ground potential of the circuit and the collector of the transistor Tll.
A P-channel MOSFET Q6 is provided in parallel with 8. The gate of MOSFETQ6 is connected to the transistor T.
The input signal Vl is commonly coupled to the base of the input signal Vl, and is further supplied with an input signal Vl from a pre-stage circuit (not shown) of the high-speed logic integrated circuit device.

Furthermore, MOSFET Q6 is designed to have a threshold voltage that corresponds to approximately an intermediate value between the absolute values of the high level and low level of the input signal I. This results in resistance R8
and MOSFET Q6 act as variable impedance means ZVI in FIG. Similarly, a collector resistor R9 is provided between the ground potential of the circuit and the collector of the transistor T12, although it is not limited to M, and a P-channel MOSFET Q7 is connected in parallel with the resistor R9.
is provided. The gate of MOSFETQ7 receives the inverted output signal of the switching circuit, that is, the transistor Tll.
collector voltage Vcl is supplied. Also, MOSFE
TQ7 is designed to have a threshold voltage corresponding to approximately an intermediate value between the absolute values of the high level and low level of the collector voltage V c l. Thereby, resistor R9 and MOSFET Q7 act as variable impedance means ZV2 in FIG. 13. A stray capacitance CC is coupled to the collector nodes of the differential transistors T11 and T12, respectively.

On the other hand, a transistor T13 and a resistor RIO corresponding to the transistor T3 and resistor Rs in FIG. 13 are provided between the commonly coupled emitters of the differential transistors Tll and T12 and the power supply voltage VEE.
A predetermined constant voltage VS is supplied to the base from a constant voltage generating circuit (not shown) of the high-speed logic integrated circuit device. As a result, the transistor T13 and the resistor RIO
Operating current 1: s = (VS-VBE) /Rl O
It acts as a constant current source that supplies s to the current switch circuit. In the ECL circuit of this embodiment, the resistor RI
The resistance value of O is made sufficiently large, and the operating current 1s of the current switch circuit is made sufficiently small.

The non-inverted output signal of the current switch circuit, that is, the collector voltage Vc2 of the transistor T12, is the collector voltage Vc2 of the transistor T12.
The signal is transmitted to the non-inverting output terminal VOI of the ECL circuit via an output emitter follower circuit consisting of a resistor R11 and a resistor R11. Needless to say, these transistor T14 and resistor R11 are similar to transistor TDl and resistor R1 in FIG.
o l respectively. Similarly, the inverted output signal of the current switch circuit, that is, the collector voltage Vcl of the transistor Tll, is transmitted to E through another output limiter follower circuit consisting of the transistor T15 and the resistor R12.
It is transmitted to the inverting output terminal VO2 of the CL circuit. Needless to say, the transistor TI4 and the resistor R11 correspond to the transistor TD1 and the resistor Ral in Figure $13, respectively. The non-inverting output terminal VOI and the inverting output terminal VO2 of the ECL circuit are further provided with an output load capacitance c corresponding to the input capacitance of the corresponding subsequent circuit and the related wiring capacitance.
L are respectively combined.

When the input signal Vl is changed to a high level higher than the reference potential VBB, the transistor Tll is turned on,
The paired transistor T12 is in a cutoff state.

Furthermore, by setting the input signal Vl to a high level, MO
SFETQ6 is turned off. As a result, the operating current is given by the constant current source consisting of the transistor T13 and the resistor RIO is directly applied to the transistor T.
11 collector current 1c. Therefore, the inverted output signal of the current switch circuit, that is, the collector voltage Vcl of the transistor Tll, becomes a predetermined low level of Vc 1L - IC VO2 becomes a low level such as VO2L = VCit, VBE # (VS-VBE) R8/RI 0-VBE. Furthermore, since the transistor TI2 is in the cutoff state, the non-inverted output signal of the current switch circuit, that is, the collector voltage VC of the transistor T12
2 becomes a high level such as VC2H#0, and thereby the non-inverted output signal VOI of the ECL circuit becomes a high level such as VOIH-Vc2HVat:'vsi:.

By the way, when the collector voltage Vcl is set to the above-mentioned low level and the collector voltage VC2 is set to the above-mentioned high level, the MOSFET Q7 constituting the variable impedance means ZV2 is turned on. Therefore, the stray capacitance Cc coupled to the collector node of the transistor Tll is actively discharged via the transistor Tll, and the stray capacitance Cc coupled to the collector node of the transistor T12 is actively charged via the MOSFET Q7. be done. As a result, although the operating current of the ECL circuit including the current switch circuit is made sufficiently small, the propagation delay time for a high level change of the input signal Vl of the ECL circuit is significantly reduced.

On the other hand, when the input signal Vl is changed to a low level lower than the reference potential VBB, the transistor Tll becomes a cant-off state, and the paired transistor T12 becomes an on-state instead. Further, when the input signal VI is set to a low level, MO8FETQ6 is turned on. As a result, the operating current I3 provided by the constant current source composed of the transistor T13 and the resistor RIO becomes the collector current 1c of the transistor T12 as it is. Therefore, the inverted output signal of the current switch circuit, that is, the transistor T
The collector voltage Vcl of 11 becomes a high level such as VC1u#0, and thereby the inverted output 1゛δ VO2 of the ECL circuit becomes a high level such as VO2H-VcINVBE'VBE. Further, the non-inverted output signal of the current switch circuit, that is, the collector voltage Vc2 of the transistor T12 becomes a predetermined low level of V c 2L = j c The non-inverted output signal VOI becomes a low level such as VOIL-VC2L VBE # (VS-VBE) R9/'RI 0-VBE.

By the way, when the collector voltage Vcl is set to the high level as described above and the collector voltage VC2 is set to the low level as described above, the MOSFET Q6 constituting the variable impedance means ZVI is turned on as described above. Therefore, the floating capacitance 1iCc coupled to the collector node of the transistor Tll is actively charged via the MOSFET Q6, and the floating capacitance 1icc coupled to the collector node of the transistor T12 is charged via the MOSFET Q6.
It is actively discharged via 12.

As a result, although the operating current of the ECL circuit including the current switch circuit is made sufficiently small, the transmission delay time for a change in the low level of the input signal VI of the ECL circuit is significantly reduced.

For these reasons, in this embodiment, the power consumption of the ECL circuit can be reduced without sacrificing its high-speed operation, and the high-speed logic integrated circuit device equipped with these ECL circuits can be highly integrated and have low power consumption. This will result in the promotion of electrification.

3.3. Evaluation of Logic Circuits FIG. 15 shows an example of a characteristic diagram showing the relationship between power consumption per gate and transmission delay time of various logic circuits. Further, FIG. 16 shows an example of a characteristic diagram showing the relationship between the capacitance value of the output load capacitance of various logic circuits and the transmission delay time.

Based on these figures, the transfer characteristics of the logic circuit to which this invention is applied will be evaluated. In addition, FIGS. 15 and 816 are
This was obtained as a result of computer simulation. In FIG. 15, the power consumption pw per gate is shown in mW (milliwatt) in the X-axis direction, and the transmission delay time tpd is shown in ps in the Y-axis direction.
(picoseconds). In addition, in FIG. 16, the capacitance value of the output load capacitance CL is pF (
It is expressed in units of picofarands, and the propagation delay time t
pd is shown in ps in the Y-axis direction. 15th
In the figure and FIG. 16, the SPL circuit to which the present invention is applied is shown as 5PLB, and the conventional SPL circuit and EC
The L circuits are designated as 5PLN and ECL, respectively.

In FIG. 15, a conventional SPL circuit (SPL) is shown.

N), for example, the resistors R1 and R2 shown in Figure @21
The transmission delay time tpd is reduced by decreasing the resistance value of the gate and increasing the power consumption PW per gate. However, if you try to reduce the power consumption PW per gate to about 0.1 mW by increasing the resistance values of the resistors R1 and R2, the rise delay of the collector voltage Vc due to the collector stray capacitance iCC increases, and the transmission delay time increases. tpd increases about 4 times. Therefore, it is difficult to reduce power consumption while maintaining high-speed operation of a high-speed logic integrated circuit device. This also applies to the ECL circuit, and the power consumption pw per gate required to realize the desired transmission delay time tpd is larger than that of the conventional SPL circuit.

However, the SPL circuit (SPLB) in which this invention was applied
), even if the resistance values of the collector resistor R5 and resistor R6 shown in FIG. 8 are increased and the power consumption per gate is reduced to Q, about 1 mW, the transmission delay time tpd of the SPL circuit hardly increases. .

Next, focusing on the relationship between the capacitance value of the output load capacitance Ct and the transmission delay time tpd, as illustrated in FIG.
If the size is increased as in the conventional SPL circuit (SP
There is no big difference between the transmission delay time tpti of the SPL circuit (LN) and the transmission delay time tpd of the SPL circuit (S P LB) to which this invention is applied, but the power consumption per gate p
When w is made small, for example, 0.1 mW, the propagation delay time tpd of the conventional SPL circuit is more than four times the propagation delay time tpd of the SPL circuit to which this invention is applied, and the difference is It increases as the capacitance value of the load capacity fCL increases.

From the above, the SPL circuit to which this invention is applied is as follows:
It is possible to reduce the operating current without hindering the high-speed operation, and correspondingly high integration of the circuit elements can be achieved. As a result, it is possible to achieve higher integration and lower power consumption of high-speed logic integrated circuit devices whose basic configuration is SPL circuits, and to speed up the machine cycles of high-speed computers and other devices made of high-speed logic integrated circuit devices while reducing their size. This makes it possible to reduce power consumption and reduce power consumption.

3.4. Example of a circuit using a logic circuit $17FIJ shows a circuit diagram of an embodiment of a series circuit made of a logic circuit to which this invention is applied, and FIG. 18 shows its signal waveform diagram. .

Further, FIG. 25 shows an example of a circuit diagram of a series circuit consisting of a conventional logic circuit, and FIG. 26 shows its signal waveform diagram. Based on these figures, the configuration and characteristics of a circuit example using a logic circuit to which the present invention is applied will be explained. Note that the series circuit of this embodiment is included as part of a high-speed logic integrated circuit device constituting a high-speed computer or the like, although it is not particularly limited. Furthermore, the signal waveform diagrams shown in FIGS. 18 and 26 are obtained as a result of computer simulation, and the output load capacitance CL and power consumption per gate PW of each NOR gate circuit are 1pF and 0.1mW
is set to

In FIG. 17, the series circuit of this embodiment includes five NOR gate circuits N in series, although not particularly limited.
It is composed of OI to NO5.

An input signal Vl is supplied to the input terminal of the NOR gate circuit NOI from a pre-stage circuit (not shown) of the high-speed logic integrated circuit device. This Noah gate circuit N.

The output signal v1 of I is sent to the next stage NOR gate circuit N.

2 input terminals. Thereafter, similarly, the output signal 2 of the NOR gate circuit NO2 is supplied to the input terminal of the NOR gate circuit NO3, and the output signal V3 thereof is supplied to the input terminal of the NOR gate circuit NO4. Further, the output signal V4 of the NOR gate circuit NO4 is the output signal V4 of the NOR gate circuit NO4 at the final stage.
5, and its output signal is supplied to a subsequent stage circuit (not shown) of the high-speed logic integrated circuit device as an output signal VO of the series circuit.

In this embodiment, the NOR gate circuits NOI to NO5 are basically the NTL circuit shown in FIG. 7, the SPL circuit shown in FIGS. 8 to 1F, or the ECL circuit shown in FIG. The circuit configuration is said to be the same. Therefore, the propagation delay time of each NOR gate circuit is significantly reduced even though its operating current is significantly reduced by ~1 and power consumption is reduced. For this reason, in a series circuit made up of conventional logic circuits, as illustrated in FIG. Although there is a propagation delay of nearly 10 ns, in a series circuit consisting of logic circuits to which this invention is applied, the delay due to each NOR gate circuit is about one-fifth, as illustrated in Figure 18. It is eventually reduced to about 1 to 2 ns.

Similar effects can be obtained in other combinational circuits and logic operation circuits, and as a result, the machine cycles of high-speed computers, etc. made of high-speed logic integrated circuit devices are accelerated, and their miniaturization is promoted. Become something.

3.5. A high-speed logic integrated circuit device consisting of a plurality of types of logic circuits and its evaluation FIG. 19 shows a board layout diagram of an embodiment of a high-speed logic integrated circuit device to which the present invention is applied. Further, FIG. 20 shows a characteristic diagram showing the relationship between switching frequency and power consumption per gate (-) of various logic circuits included in the high-speed logic integrated circuit device of FIG. 19. Here, the switching frequency Fs, in other words, the frequency of the digital signal transmitted through each logic circuit, is expressed in units of Hz (Hertz) in the X-axis direction,
Power consumption PW per gate is shown in mW (milliwatt) in the Y-axis direction. Further, the SPL circuit to which this invention is applied is shown as 5PLB, and is similar to the conventional CM
An O5 (complementary MO3) circuit is shown as CMOS. The characteristic diagram shown in Figure @20 was obtained as a result of computer simulation, and the output load capacitance CL of each NOR gate circuit is set to 19F, and the amplitude Vs of the transmitted digital signal is 0M03. The voltage is set to 5V in the circuit and 0°5V in the SPL circuit.

In FIG. 19, the high-speed logic integrated circuit device of this embodiment includes, but is not particularly limited to, a logic HLCH consisting of an SPL circuit (first logic circuit) and a logic section LCL consisting of a CMO5 circuit (second logic circuit). Equipped with. Of these, the logic section LCH is one that transmits a relatively high frequency signal, such as a Cronk system circuit in a high-speed computer, etc., and is not particularly limited to the above-mentioned new It is composed of an SPL circuit (SPL B). On the other hand, the logic unit LCL is supposed to transmit a relatively low frequency signal, and is a P-channel MOSFET.
It is constructed by a conventional 0M08 circuit consisting of an ET and an N-channel MOS FET combined in series-parallel configuration.

By the way, j1i! 1 erase per gate required for logic circuit! The power pw is expressed as follows: -When the output load capacity is CL, the signal amplitude and switching frequency of the transmitted digital signal are Vs and F3, respectively, and the power consumption of each logic circuit at rest is PWs, - For boat fishing, PW -CL Vs2Fs 10PWs It is calculated by the calculation formula. Therefore, 0M03
As illustrated in Fig. 20, the power consumption PW per gate required for the circuit (CMO5) is 0.1 m when the switching frequency Fs is about 10 MHz or less (1 MHz is lO to the 6th power). W or less will do, but
When the switching frequency Fs exceeds 10 MHz, it increases rapidly. However, as is well known, the 0M03 circuit is constructed only of MOSFETs that can be relatively miniaturized, so the required layout area per gate is small. On the other hand, in the case of an SPL circuit (SPLB),
Power consumption P W s when signal amplitude Vs is small and stationary
Since there are extremely few
The frequency dependence of the R power pw becomes very small, and only about 0.1 mW is sufficient until the switching frequency FS exceeds 1 gigahertz (1 gigahertz is lO to the 9th power). However, when the switching frequency Fs becomes less than about 10 megaH2, the power consumption PW per gate becomes larger than that of the CMO5 circuit.Also, as mentioned in the previous section, the SPL circuit is a composite circuit with bipolar transistors. Therefore, it requires a larger layout area compared to the 0M03 circuit.

In the high-speed logic integrated circuit device of this embodiment, as described above, the logic section LCH that transmits a relatively high frequency digital signal close to 1 gigabyte (z) is configured by a new SPL circuit, and is configured with a new SPL circuit, for example, 1 gigabyte (1 gigabyte) (close to z). The logic section LCL that transmits a digital signal of a relatively low frequency is configured by a conventional 0M03 circuit.As a result, the logic fiLcH achieves a low power consumption ratio while ensuring a relatively high switching frequency. At the same time, the logic unit LCL achieves low power consumption while ensuring the desired switching speed and achieving high integration.As a result, the overall transfer characteristics of the high-speed logic integrated circuit device are improved. It is possible to promote higher integration and lower consumption gravity while increasing the number of devices.

As shown in the above embodiment, this invention can be applied to N T
By being applicable to logic circuits such as L circuits, SPL circuits, and ECL circuits, as well as semiconductor integrated circuit devices such as high-speed logic integrated circuit devices that are constructed based on such logic circuits, the following effects can be obtained. It will be done. That is, (1) A predetermined level setting means and an input signal provided in parallel with the level setting means as a collector load of a human-powered transistor constituting a phase division circuit or a current switch circuit such as an NTL circuit, an SPL circuit, an ECL circuit, etc. By providing variable impedance means, the impedance of which is selectively turned on according to the input signal level, the 1$ idle capacitance coupled to the collector node of the transistor is reduced. The effect of speeding up charging and discharging operations can be obtained.

(2) In the above item (1), the level setting means is
Consisting of a collector resistor with a relatively large resistance value, a diode with a predetermined forward voltage, or a series circuit consisting of such a collector resistor and a diode,
By configuring the switch means using a P-Nayan MOSFET having a threshold voltage corresponding to approximately the midpoint of the peak value of the logic amplitude of the input signal, the variable impedance means can be easily constructed while suppressing the required layout area. The effect is that it can be realized.

(3) In items (1) and (2) above, the resistance value of the emitter load that sets the operating current of the transistor is made sufficiently large, and a speed-up capantor is loaded in parallel with it. It is possible to reduce the operating current of the phase division circuit and the current scanner circuit without increasing the propagation delay time.

(4) Items (1) to (3) above allow NTL circuits, SPL circuits, and E
The effect of significantly reducing the operating current of the CL, etc. can be obtained.

(5) According to the above (1) to (4), the NTL circuit, SPL circuit, or ECL circuit can be used while maintaining its high-speed operation.
This has the effect of promoting higher integration and lower power consumption of high-speed logic integrated circuit devices and the like that are configured based on circuits.

(6) The effect of items (1) to (5) above is that it is possible to reduce the size and power consumption of high-speed computers, etc. made of high-speed logic integrated circuit devices, while increasing the speed of the machine cycle. is obtained.

(7) In a semiconductor integrated circuit device such as a high-speed logic integrated circuit device, a logic section to which a relatively high frequency digital signal is transmitted is configured with an NTL circuit, an SPL circuit, or an ECL circuit, and a relatively low frequency digital signal is transmitted. By configuring the logic section to be transmitted using a CMOS circuit, it is possible to reduce the transmission delay time and reduce the power consumption of each logic section.

(8) In the above item (7), the impedance of the input transistor is selectively changed according to the level of the input signal as a collector load of the input transistor constituting the phase division circuit or current switch circuit of the NTL circuit, SPL circuit, and ECL circuit. By providing the variable impedance means, it is possible to speed up the charging and discharging operations of the collector floating capacitor of the transistor, thereby achieving the effect of further speeding up the operation and promoting lower power consumption of each logic section. .

(9) The effect of items (7) and (8) above is that it is possible to achieve higher integration and lower power consumption of high-speed logic integrated circuits, etc., while increasing the speed of their overall operation. is obtained.

(10) The effect of items (7) to (9) above is that it is possible to reduce the size and reduce the power consumption of high-speed computers, etc. made of high-speed logic integrated circuit devices, while increasing the speed of the machine cycle. is obtained.

As above, the invention made by the present inventor has been specifically explained based on Examples, but this invention is not limited to the above-mentioned Examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say, for example, in FIGS. 1 to 6 and FIG. 13, the signal amplitudes and absolute values of the input signal Vl and the output signal 0, VOl, VO2 and their absolute values are arbitrary, and the variable impedance means Z
Various specific configurations of V, ZVI, ZV2, level setting means LS, and switching means SW may be considered, and the diode Dc shown in FIG. 14 and FIG. 5 is not particularly required to be a Zener diode.

In FIGS. 7 to 11 and FIG. This embodiment can be adopted. That is, for example, in the seventh step, the input transistor T
'l can be replaced by multiple input transistors in parallel, deaf, similar to the $lO diagram. In this case, it is necessary to provide a plurality of P-channel inter-O3FETs arranged in series in place of the P-channel MOS FET Q1. In addition, in FIGS. 8 to 10, the SPL circuit may include a circuit for clamping the base potential of the transistor T6.
1 can be replaced with a plurality of transistors depending on the logic configuration of the ECL circuit, or may output only a non-inverted or inverted output signal. In FIG. 17, the series circuit can take various logic forms and can be constructed from various logic gate circuits other than NOR gate circuits. In FIG. 19, the high speed logic integrated circuit device may be divided into three or more logic sections. Furthermore, the logic section LCH of the high-speed logic integrated circuit device may include an NTL circuit and an ECL circuit.

In the above explanation, the invention made by the present inventor will be mainly described in the NTL circuit and S
Although we have described the case where the PL circuit, ECL circuit, and these logic circuits are used as the basic configuration and are applicable to a high-speed logic integrated circuit device constituting a high-speed combinator, the present invention is not limited to this (for example, if the above logic circuit is It can also be used for various types of logic circuits that basically follow the same logic circuits, gate array integrated circuits that have such logic circuits as their basic configuration, and various digital processing devices that are constructed from the above-mentioned high-speed logic integrated circuit devices or gate array integrated circuits. .

The present invention is widely applicable to logic circuits that include at least a phase division circuit or a current switch circuit, and to semiconductor integrated circuit devices that include such logic circuits.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, NTL circuits, SPL circuits, and ECL circuits.
As a collector load of an input transistor constituting a phase division circuit or a current switch circuit of a circuit, for example, a collector resistor having a relatively large resistance value, and a collector resistor provided in parallel with this and receiving an input signal at its gate and receiving the input signal. By providing a variable impedance means consisting of a P-channel MOSFET having a threshold voltage corresponding to the intermediate value of the absolute value of the logic amplitude, the charging and discharging operations of the collector stray capacitance of the input transistor can be speeded up. without hindering its high-speed operation.
The power consumption of NTL circuits, SPL circuits, ECL circuits, etc. can be reduced. As a result, it is possible to promote higher integration and lower power consumption of high-speed logic integrated circuit devices, etc. whose basic configuration is these logic circuits, and to speed up the machine cycles of high-speed computers, etc., which consist of high-speed logic integrated circuit devices. can.

[Brief explanation of drawings]

Figure 1 shows an NTL circuit and an SPL circuit to which this invention is applied.
Figure 2 is a partial basic conceptual diagram showing the first example of the circuit; Figure 2 is a partial basic configuration diagram showing an example of the NTL circuit and SPL circuit in Figure 1; Figure NT
A partial basic circuit diagram showing the first embodiment of the L circuit and the SPL circuit, @4 is a partial basic circuit diagram showing the second embodiment of the NTL circuit and SPL circuit of FIG. 2, @ 5 is a partial basic circuit diagram showing a third embodiment of the NTL circuit and SPL circuit of FIG. 2, and FIG. 6 is a partial basic circuit diagram showing another embodiment of the NTL circuit and SPL circuit to which the present invention is applied. 7 is a specific circuit diagram showing an example of an NTL circuit based on the basic circuit diagram in FIG. 3, and FIG. 8 is a partial basic circuit diagram based on the basic circuit diagram in FIG. 3. A specific circuit diagram showing the first embodiment of the SPL circuit, FIG. 9, is an SPL circuit based on the basic circuit diagram of FIG.
A specific circuit diagram showing the second embodiment of the PL circuit, FIG. 1θ, is a specific circuit diagram showing the third embodiment of the SPL circuit based on the basic circuit diagram of FIG. 3, and FIG. A specific circuit diagram showing an example of @4 of the SPL circuit based on the basic circuit diagram of FIG. 3, and FIG. 12 is the NTL circuit diagram of FIG.
A signal waveform diagram showing an example of the circuit and an SPL circuit, FIG. 13 is a basic conceptual diagram showing an example of an ECL circuit to which the present invention is applied, and FIG. A specific circuit diagram showing an example of the ECL circuit in Fig. 13, Fig. 15 is a characteristic diagram showing the relationship between power consumption per gate and transmission delay time of various logic circuits, and Fig. 16 shows each f logic circuit. FIG. 17 is a characteristic diagram showing the relationship between the capacitance value of the output load capacitance of the circuit and the transmission delay time, and FIG. 17 is a signal waveform diagram showing an example of the series circuit shown in FIG. 17, FIG. Figure 21 is a characteristic diagram showing the relationship between switching frequency and power consumption per gate of various logic circuits included in the high-speed logic integrated circuit device; Figure 21 is a circuit diagram showing an example of a conventional NTL circuit; Figure 23 is a circuit diagram showing an example of a conventional ECL circuit. The $24 factor is a circuit diagram showing an example of a conventional ECL circuit. FIG. 25 is a circuit diagram showing an example of a series circuit consisting of a conventional logic circuit. FIG. 26 is a signal waveform diagram showing an example of the series circuit of FIG. 25. TN ・・・NPN type bipolar transistor, Z■・
...Variable impedance means, Cc...Collector stray capacitance, RE...Eminter resistance, C3...Speed amplifier capacitor. LS...level) L setting means, SW...-switch means. Qp--P channel MOSFET, Rc--collector resistance. DC...Zener diode. 1p...PNP type bipolar transistor, Qs
...N-channel MOSFET. Tl-T15...NPN type bipolar transistor,
Ql-Q7...P channel MOSFET, Q21.
...N-channel MOSFET. R1-R12...Resistor, 01-C3...Capacitor, CL...Output load capacitance. Tcl~Tc 2. Ts, To1~To2...NPN
type bipolar transistor, ZVI-ZV2... variable impedance means, R3, RD 1 to Rn 2...
resistance. PW...power consumption per gate, tpd/transmission delay time, ECL...ECL circuit, 5PLN...conventional S
PL circuit, 5PLB...SPL circuit according to the present invention. N0I-NOIO...Nor gate circuit. LSI...High-speed logic integrated circuit device, LCL...C
Logic unit consisting of MOS, LCH...SP according to the present invention
A logic section consisting of an L circuit. Fs...Switching frequency. Figure 1

Claims (1)

[Claims] 1. A bipolar transistor whose base receives a predetermined input signal; and a bipolar transistor coupled to the collector-emitter path of the bipolar transistor, the impedance of which is selectively changed according to the potential level of the input signal. A logic circuit comprising variable impedance means. 2. The variable impedance means includes a level setting means provided between a first power supply terminal to which a first power supply voltage is supplied and the collector of the bipolar transistor, and a level setting means provided in parallel with the level setting means. 2. The logic circuit according to claim 1, further comprising switch means that is selectively turned on according to the level of an input signal. 3. The logic circuit according to claim 2, wherein the level setting means includes resistance means. 4. The logic circuit according to claim 2, wherein the level setting means includes a diode. 5. The logic circuit according to claim 2, wherein the level setting means includes a diode and a resistance means provided in series with the diode. 6. The logic circuit according to claim 2, wherein the bipolar transistor includes an NPN transistor, and the switch means includes a P-channel MOSFET that receives the input signal at its gate. 7. Claim 6, characterized in that the P-channel MOSFET is designed to have a threshold voltage approximately corresponding to an intermediate value of the absolute value of the logic amplitude of the input signal. The logic circuit described. 8. The logic circuit is an NTL circuit, and further includes a speed-up capacitor provided in parallel with the emitter load means of the bipolar transistor. Logic circuit according to item 2, 6 or 7. 9. The logic circuit is an SPL circuit, and further includes a speed-up capacitor provided in parallel with the emitter load means of the bipolar transistor. Logic circuit according to item 2, 6 or 7. 10. The logic circuit according to claim 1, 2, 6 or 7, wherein the logic circuit is an ECL circuit. 11. The logic circuit according to claim 1 or 2, wherein the logic circuit is included in a high-speed logic integrated circuit device. 12. Claims 1 and 2, wherein the high-speed logic integrated circuit device includes the logic circuit and CMOS circuit that are selectively used depending on the frequency of the transmitted signal. Or the logic circuit according to item 11. 13. The logic circuit according to claim 1, 2, 11, or 12, wherein the high-speed logic integrated circuit device constitutes a high-speed computer. 14. A semiconductor integrated circuit device comprising first and second logic circuits that are selectively used depending on the frequency of a transmitted signal. 15. The first logic circuit is an NTL circuit, an SPL circuit, or an ECL circuit, and the second logic circuit is a C
Claim 1 characterized in that it is a MOS circuit.
4. The semiconductor integrated circuit device according to item 4. 16. The NTL circuit, SPL circuit, and ECL circuit are characterized in that they are provided with variable impedance means that is provided as a collector load of the input bipolar transistor and whose impedance is selectively changed according to the level of the input signal. Claim 1
The semiconductor integrated circuit device according to item 4 or item 15. 17. The variable impedance means includes a resistance means provided between the first power supply voltage and the collector of the input bipolar transistor, and a P channel M which is provided in parallel with the resistance means and receives the input signal at its gate.
17. The semiconductor integrated circuit device according to claim 14, 15, or 16, characterized in that it is constituted by an OSFET. 18. An input terminal to which an input signal is to be supplied, an output terminal to which an output signal is to be supplied, and first and second power supply terminals to which first and second power supply voltages are to be supplied, respectively;
a bipolar transistor having a base coupled to the input terminal and a collector coupled to the output terminal; and a bipolar transistor coupled between the first power supply terminal and the collector of the bipolar transistor, the bipolar transistor being in a conductive state. variable impedance means controlled such that its impedance has a first value when the bipolar transistor is to be rendered non-conducting; and its impedance has a second value lower than the first value when the bipolar transistor is to be rendered non-conducting; and emitter load means coupled between the emitter of the bipolar transistor and the second power supply terminal.