JPH03266453A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03266453A JPH03266453A JP2066418A JP6641890A JPH03266453A JP H03266453 A JPH03266453 A JP H03266453A JP 2066418 A JP2066418 A JP 2066418A JP 6641890 A JP6641890 A JP 6641890A JP H03266453 A JPH03266453 A JP H03266453A
- Authority
- JP
- Japan
- Prior art keywords
- main body
- case main
- cap
- pellet
- sealing material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000008188 pellet Substances 0.000 claims abstract description 14
- 239000003566 sealing material Substances 0.000 claims abstract description 10
- 238000007789 sealing Methods 0.000 claims abstract description 7
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract 1
- 239000000565 sealant Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は気密封止型半導体装置、特に半導体ペレットを
搭載する容器本体とキャップがシール材で接着して気密
封止された半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hermetically sealed semiconductor device, and more particularly to a semiconductor device in which a container body in which semiconductor pellets are mounted and a cap are hermetically sealed by bonding with a sealing material.
従来、この種の半導体装置は、第3図の断面図に示す様
に、半導体ペレット2を搭載する容器本体1は、上下平
行な平坦な面の板体で形成され、その上面中央の半導体
ペレット搭載部に半導体ペレット2が搭載され、容器本
体周辺のシール部とキャップ5との間はシール材6を介
して気密に封着されていた。Conventionally, in this type of semiconductor device, as shown in the cross-sectional view of FIG. A semiconductor pellet 2 was mounted on the mounting portion, and the seal portion around the container body and the cap 5 were airtightly sealed via a sealing material 6.
上述した従来の半導体装置は、容器本体のシール部の内
側が平坦であったため、特に小型な半導体装置では、容
器本体とキャップを接着する際に、シール材が容器内に
流れ込むことがあり、最悪の場合は、半導体ペレットの
電極との間を接続するポンディングワイヤの接続されて
いる導電パターンのところまで流れこみ、ポンディング
ワイヤ4を切断したり、さらにはペレット部まで流れて
ペレット2の破壊を生じるという欠点がある。In the conventional semiconductor devices mentioned above, the inside of the seal part of the container body was flat, so especially in small semiconductor devices, when bonding the container body and the cap, the sealing material may flow into the container, causing a worst-case scenario. In this case, it may flow to the conductive pattern connected to the bonding wire that connects the electrode of the semiconductor pellet, cutting the bonding wire 4, or even flowing to the pellet part and destroying the pellet 2. It has the disadvantage of causing
上記課題に対し本発明の半導体装置は、容器本体周辺の
シール部の内側に溝を設け、この溝により容器本体の中
央部へ流れ込むシール材を阻止している。In order to solve the above problem, the semiconductor device of the present invention provides a groove inside the sealing portion around the container body, and this groove prevents the sealant from flowing into the center of the container body.
つぎに本発明を実施例により説明する。 Next, the present invention will be explained by examples.
第1図は本発明の一実施例の断面図である。第1図にお
いて、板状の容器本体1の上面中央に半導体ペレット2
が搭載され、ペレット2の搭載部の周囲に設けである導
電パターン3とペレットの電極との間はポンディングワ
イヤ4で接続されている。導電パターン3は容器本体を
貫通する導電路により底面に導かれ、容器本体1の底面
から横方向に引圧されている外部リード7につながって
いる。また、容器本体1の上面周辺には、周壁を有する
キャップ5の周壁下面がシール材6で気密封着されてい
るが、容器本体1の、キャップ5とが接着されたシール
部と、導電パターン3との間には、断面U字状の溝8が
シール部に沿うように設けられている。この溝8により
、容器本体の中央部までも流れ込もうとするシール材6
は阻止される。FIG. 1 is a sectional view of an embodiment of the present invention. In FIG. 1, a semiconductor pellet 2 is placed in the center of the top surface of a plate-shaped container body 1.
is mounted, and a conductive pattern 3 provided around the mounting portion of the pellet 2 and the electrode of the pellet are connected by a bonding wire 4. The conductive pattern 3 is guided to the bottom surface by a conductive path penetrating the container body, and is connected to an external lead 7 that is laterally pulled from the bottom surface of the container body 1. Further, around the upper surface of the container body 1, the lower surface of the peripheral wall of a cap 5 having a peripheral wall is hermetically sealed with a sealing material 6. 3, a groove 8 having a U-shaped cross section is provided along the seal portion. This groove 8 allows the sealing material 6 to flow into the center of the container body.
is prevented.
第2図は本発明の他の実施例の断面図である。FIG. 2 is a sectional view of another embodiment of the invention.
第1図では、容器本体のシール部の内側に断面U字状の
溝を形成したが、第2図では、前記シール材流入阻止用
の溝9は、V字状断面としている。In FIG. 1, a groove with a U-shaped cross section is formed inside the sealing portion of the container body, but in FIG. 2, the groove 9 for preventing the sealant from flowing in has a V-shaped cross section.
以上説明したように本発明は、容器本体とキャップがシ
ール材で接着される気密封止型半導体装置の容器本体側
のシール部の内側に、該シール部に沿った溝を設けるこ
とにより、容器本体とキャップの接着部から、内部半導
体ペレット側へ、シール材が流れ込むことを防止する効
果がある。As explained above, the present invention provides a hermetically sealed semiconductor device, in which the container body and the cap are bonded together with a sealing material, by providing a groove along the seal portion on the side of the container body. This has the effect of preventing the sealant from flowing into the internal semiconductor pellet from the bonded portion between the main body and the cap.
第1図および第2図はそれぞれ本発明の一実施例および
他の実施例の断面図、第3図は従来の半導体装置の断面
図である。
1・・・・・・容器本体、2・・・・・・半導体ペレッ
ト、3・・・・・・導1[パターン、4・・・・・・ポ
ンディングワイヤ、5・・・・・・キャップ、6・・・
・・・シール材、7・・・・・・外部リード、8,9・
・・・・・シール材流入阻止用溝。1 and 2 are sectional views of one embodiment and another embodiment of the present invention, respectively, and FIG. 3 is a sectional view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Container body, 2... Semiconductor pellet, 3... Conductor 1 [pattern, 4... Bonding wire, 5... Cap, 6...
... Seal material, 7 ... External lead, 8, 9.
...Groove for preventing seal material inflow.
Claims (1)
ップをかぶせて気密封着した半導体装置において、前記
容器本体とキャップを接着するシール材が容器本体の中
央部へ流れ込むのを阻止するための溝が容器本体のシー
ル部の内側に、このシール部に沿って設けられているこ
とを特徴とする半導体装置。In a semiconductor device in which a semiconductor pellet is mounted on the center of the upper surface of a container body and a cap is placed on the semiconductor device for airtight sealing, a groove is provided to prevent a sealing material that adheres the container body and the cap from flowing into the center of the container body. A semiconductor device characterized in that the semiconductor device is provided inside a seal portion of a container body and along the seal portion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2066418A JPH03266453A (en) | 1990-03-15 | 1990-03-15 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2066418A JPH03266453A (en) | 1990-03-15 | 1990-03-15 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03266453A true JPH03266453A (en) | 1991-11-27 |
Family
ID=13315229
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2066418A Pending JPH03266453A (en) | 1990-03-15 | 1990-03-15 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03266453A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5543663A (en) * | 1993-12-27 | 1996-08-06 | Kabushiki Kaisha Toshiba | Semiconductor device and BGA package |
JP2013051560A (en) * | 2011-08-31 | 2013-03-14 | Nippon Dempa Kogyo Co Ltd | Piezoelectric device |
-
1990
- 1990-03-15 JP JP2066418A patent/JPH03266453A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5543663A (en) * | 1993-12-27 | 1996-08-06 | Kabushiki Kaisha Toshiba | Semiconductor device and BGA package |
JP2013051560A (en) * | 2011-08-31 | 2013-03-14 | Nippon Dempa Kogyo Co Ltd | Piezoelectric device |
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