JPH03266297A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To attain a high-speed action and to suppress a momentary current owing to the sense action by making a first sense amplifier system and a second sense amplifier system active independently. CONSTITUTION:Word lines 2 and a pair of bit lines 3 are installed to a memory cell array 1 arranged in a matrix shape, the sense amplifier of first system 4 is connected to the pair of bit lines 3 and a sense amplifier driving signal A5 is inputted. Moreover, the sense amplifier of the second system 11 to make only the selected pair of bit lines active is provide and is driven by a column decoder 13 to be active corresponding to the sense amplifier driving signal B 12 of the second system and the selected pair of bit lines. Then, for the first sense amplifier system 4, action time action speed is made to delay to the second sense amplifier system 11. Thus, signal delay owing to the wiring resistance of the sense amplifier driving signal is reduced, a high-speed sense action is realized and simultaneously a momentary current value can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device equipped with a sense amplifier.

Conventional technology Semiconductor storage devices have made remarkable progress and are increasing in capacity.

Speeding up is underway. However, increasing the capacity leads to an increase in the chip area, and signal delay due to increased wiring resistance is a cause of impediments to higher speeds. In particular, since the sense amplifier drive signal for amplifying memory data has a large current drive amount, the signal delay due to the increase in wiring resistance is significant.

On the other hand, due to the increase in the number of memory cells due to larger capacity and faster speeds, and the short operation time, instantaneous current increases, causing power fluctuations and electromagnetic induction, which become noise sources and cause malfunctions of semiconductor storage devices or systems equipped with such semiconductor storage devices. cause. As described above, in order to increase the capacity and speed of semiconductor memory devices, important issues are reducing signal delay by reducing wiring resistance and reducing instantaneous current.

A conventional semiconductor memory device will be explained below.

FIG. 3 shows the configuration of a conventional semiconductor memory device, in which a memory cell array 21 arranged in a matrix is equipped with word lines 22 and bit line pairs 23.
A sense amplifier 24 is connected to 3, and is driven by a sense amplifier drive signal 25. Further, a row decoder 26 is connected to the word line 22 and a row address 27 is input thereto. Furthermore, a column decoder 2 is connected to the bit line pair 23.
8 is connected and column address 29 is input. Note that 30 is a data line pair.

Regarding the semiconductor memory device configured as described above, the related operations of its constituent elements will be explained below.

Input the row address 27 to the row decoder 26, and
One word line is selected from the word lines 22 of the book. The memory cell data selected by the word line 22 is read out onto the bit line pair 23 to generate a potential difference in the bit line pair 23.

Next, the sense amplifier drive signal 25 is activated, and the potential difference between the bit line pair 23 is sufficiently expanded by the sense amplifier 24.

Input column address 29 to column decoder 28, m
Select one bit line pair from the bit line pair 23,
After the potential difference between the bit line pairs is sufficiently expanded by the sense amplifier operation, the selected bit line pair and the data line pair 30 are connected, and the memory cell data read to the bit line pair is transferred to the data line pair 30. .

Problem to be Solved by the Invention However, in the conventional configuration described above, all the sense amplifiers 24 are driven simultaneously regardless of whether the bit line pair 23 is selected or not, so the charges related to all the sense amplifiers 24 are charged and discharged at the same time. Therefore, the signal delay of the sense amplifier drive signal 25 due to the wiring resistance of the sense amplifier drive signal line increases, making high-speed operation difficult.

Furthermore, if the wiring resistance is reduced and the signal delay is suppressed to speed up the sensing operation, the instantaneous current due to charging and discharging of the charge during the sensing operation increases, which becomes a noise source and becomes more likely to cause malfunctions. It had

The present invention takes the above-mentioned problems into consideration and provides a semiconductor memory device equipped with a sense amplifier circuit that simultaneously realizes high-speed sensing operation and low instantaneous current.

Means for Solving the Problems In order to achieve the above object of the present invention, a memory cell array in which a plurality of memory cells are arranged in a matrix, one column of memory cells from this memory cell array, and data of this memory cell are selected. a first sense amplifier system that simultaneously amplifies the potential difference between all bit line pairs of the memory cell array; and a first sense amplifier system that amplifies the potential difference of only the bit line pair that reads data from the selected memory cell. Equipped with a second sense amplifier system,
The first sense amplifier system and the second sense amplifier system are provided with means for independently performing the operations at different times.

Operation The semiconductor memory device of the present invention having the above-mentioned configuration performs a sense amplifier drive by independently performing a sensing operation using the second sense amplifier system for a bit line pair selected for reading data by a column decoder or the like. By reducing the charging and discharging charges that become a signal load and reducing the current, signal delay can be reduced and high-speed sensing operations can be performed.

Regarding unselected bit line pairs, since there is no need to perform a high-speed sense operation, the first sense amplifier system is used to perform the sense operation at a lower speed than the second sense amplifier system. This makes it possible to reduce the instantaneous current caused by the sensing operation by staggering the times at which the sensing operations occur so that the currents do not flow at the same time.

As described above, according to the present invention, high-speed sensing operation and instantaneous current reduction during sensing operation can be simultaneously realized.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a semiconductor memory device in one embodiment of the present invention.

As shown in FIG. 1, a memory cell array 1 arranged in a matrix is equipped with word lines 2 and bit line pairs 3. A first system sense amplifier 4 is connected to the bit line pair 3, and a first system sense amplifier drive signal A5 is input thereto. Further, a row decoder 6 is connected to the word line 2, and a row address 7 is input thereto. Further, a column decoder 8 is connected to the bit line pair 3, and a column address 9 is input thereto. Note that 10 is a data line pair, which has the same structure as the conventional example.

The present invention further provides a second bit line pair in which only the selected bit line pair operates.
A system sense amplifier 11 is provided, and corresponding to the second system sense amplifier drive signal B12 and the selected bit line pair,
It is driven by the column decoder 13 which becomes active.

The operation of the semiconductor memory device of this embodiment configured as described above will be described below.

FIG. 2 is a timing diagram showing the operation timing of the embodiment of the present invention shown in FIG. 1, and the operation will be explained based on FIG.

At time t=tl, the selected word line becomes active, and the data of the memory cell selected from memory cell array 1 is read onto bit line pair 3.

At time t=t2, the sense amplifier drive signal B12 becomes active, and the output 13 that becomes active corresponding to the selected bit line pair is output from the column decoder 8, and the NA
The sense amplifier 11 of the selected bit line pair is driven via the ND circuit to amplify the potential difference between the selected bit line pair 3.

Since the sense amplifier 11 to be driven is limited to the sense amplifier related to the selected bit line pair, the amount of charge to be driven is small, the current is reduced, and signal transmission due to wiring resistance can be made sufficiently small.

After sufficiently amplifying the potential difference between the selected bit line pair 3, the data on the selected bit line pair 3 is read out to the data line pair 10.

At time t=t3, the sense amplifier drive signal A5 becomes active, and the sense amplifier 4 operates to amplify the potential difference between the unselected bit line pair 3. Since the sense operation of the unselected bit line pair 3 does not affect the access time of the semiconductor memory device, the speed of the sense operation can be slowed down so that the instantaneous current caused by the operation of the sense amplifier 4 is sufficiently small. becomes.

As described above, according to this embodiment, there are two sense amplifier systems: a first sense amplifier system that operates simultaneously for all bit line pairs, and a second sense amplifier system that operates only for bit line pairs selected by the column decoder. The first sense amplifier system is provided with a sense amplifier system, and the operating speed of the first sense amplifier system is delayed relative to the second sense amplifier system, thereby reducing signal delay due to wiring resistance of the sense amplifier drive signal. , it is possible to realize high-speed sensing operation, reduce the instantaneous current value due to sense amplifier operation, and prevent malfunctions caused by power supply fluctuations due to instantaneous current.

In this embodiment, the timing is shown in FIG. 2 for the circuit configuration of Vcc (power supply voltage) bit line precharge, but it is clear that this has nothing to do with the essence of the present invention. .

In addition, in this example, the speed of the sense operation and the reduction of the temporary current due to the sense operation are simultaneously achieved, but by setting the circuit constants, it is possible to speed up the sense operation or reduce the instantaneous current value due to the sense operation. It is clear that there are cases in which only one effect is achieved.

Furthermore, in this embodiment, the timing t=t3 at which the unselected bit line drive signal A5 becomes active is delayed compared to the timing t=t2 at which the selected bit line signal drive signal 2 becomes active, but t2=t3 or It is clear that even if t2 is slightly delayed compared to t3, the same effect as in this embodiment can be obtained.

Effects of the Invention As is clear from the above description, the present invention includes a first sense amplifier system that operates on all bit line pairs and a second sense amplifier system that operates on selected bit line pairs. By operating the sense amplifier system and the above-mentioned second sense amplifier system independently, it is possible to suppress the signal delay due to wiring resistance of the sense amplifier drive signal and enable high-speed sensing operation, and also to suppress the instantaneous current caused by the sensing operation to realize instantaneous This provides an excellent semiconductor memory device that can prevent malfunctions caused by current.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation timing of the semiconductor memory device according to the same embodiment, and FIG. 3 is a diagram of a conventional semiconductor memory device. FIG. 2 is a block diagram showing the configuration. 1...Memory cell array, 3...Bit line pair, 4...First system sense amplifier, 5
...First system sense amplifier drive signal A, 6.
... Row decoder, 7 ... Row address, 8 ... Column decoder, 9 ... Column address, 11 ... Second system sense Amplifier, 12...Second system sense amplifier drive signal B
, 13...Column decoder output that becomes active corresponding to the selected bit line pair.

Claims (2)

[Claims] (1) A memory cell array in which a plurality of memory cells are arranged in a matrix, means for selecting one column of memory cells from the memory cell array, a bit line pair for reading data from the selected memory cell, and a memory cell array for reading data from the selected memory cell. a first sense amplifier system that simultaneously amplifies the potential differences of all the bit line pairs; and a second sense amplifier system that amplifies the potential difference of only the bit line pair that reads data from the selected memory cell among the bit line pairs of the memory cell array. A semiconductor memory device comprising an amplifier system, and means for independently performing operations of the first sense amplifier system and the second sense amplifier system with temporal shifts. (2) Compared to the operation of the first sense amplifier system, the second sense amplifier system
2. The semiconductor memory device according to claim 1, wherein the sense amplifier system operates at low speed.