JPH03258083A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To improve the transfer efficiency between horizontal charge transfer sections by setting tentatively a gate voltage of a transfer gate voltage to an intermediate voltage on the way of the gate voltage to be transited at the end of charge transfer between the horizontal charge transfer sections. CONSTITUTION:A gate 9 is provided between a storage section 3 and a 1st horizontal register 4, the gate 9 is controlled by a signal PHIVH and the gate 9 is conductive when the signal PHIVH is at an H level and the gate 9 is interrupted when the signal PHIVH is at an L level. That is, a gate voltage of a transfer gate 10 controlling the transfer between horizontal charge transfer sections at the end of the charge transfer between the horizontal charge transfer sections is transited via an intermediate voltage or transited slowly to bring the transfer gate 10 into the interrupting state after the charge of a channel region 14 under the gate electrode is sufficiently transferred to the horizontal charge transfer section being the transfer destination. Thus, an ill effect of the charge applied to the transfer gate 10 reversely transferred to the horizontal charge transfer sections being the transfer destination is prevented and the transmission efficiency is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state image sensor having a plurality of horizontal charge transfer sections.

[Summary of the invention]

In the present invention, signal charges from light receiving sections arranged in a matrix are transferred to a plurality of vertical charge transfer sections.

In a CCD solid-state image sensor that reads out data via a horizontal charge transfer section, the transfer efficiency is improved by making the transition of the gate voltage of the transfer gate between the horizontal charge transfer sections stepwise or for a longer period of time. be.

[Conventional technology]

In a solid-state image sensor having a large number of pixels, the horizontal transfer frequency becomes high, making the transfer difficult. Therefore, in order to lower the horizontal transfer frequency, two or more horizontal charge transfer units (horizontal registers) are provided, and signal charges are distributed and transferred to these units.

For example, in a solid-state image sensor that has two horizontal charge transfer sections provided in parallel, each horizontal charge transfer section performs high-speed transfer using two-phase transfer signals ΦH1 and ΦH2.
The transfer electrodes of the two horizontal charge transfer sections are common across the transfer gate, and are provided with common transfer signals ΦH1 and ΦH2. A channel region is provided below the transfer gate and sandwiched between channel stop regions, and transfer between the horizontal charge transfer sections is performed via the channel region. The channel region is sandwiched between a region to which the transfer signal ΦH2 of one horizontal charge transfer section is applied and a region M\i to which the transfer signal ΦH1 of the other horizontal charge transfer section is applied,
The region to which the transfer signal ΦH1 of one horizontal charge transfer section is applied is adjacent to the channel stop region below the transfer gate.

FIGS. 5(a) to 5(d) are diagrams for explaining charge transfer between horizontal charge transfer sections from the viewpoint of the potential thereof. To explain the case where charges are transferred from the area of the transfer signal ΦH2 of the horizontal charge transfer unit to the area of the transfer signal ΦH1 of the horizontal charge transfer unit via the transfer gate controlled by the signal ΦHHG, first, FIG. As shown in (a), the level of the signal ΦHHG is raised to make the transfer gate conductive, and the transfer signals ΦH1 and ΦH2 are set to a low level. Then, the 0th order where charges are accumulated in the channel region at the bottom of the transfer gate,
As shown in FIG. 5(c), the transfer signal ΦH which is the transfer destination
Change only 1 to a high level. Then, the charges accumulated in the channel region below the transfer gate are transferred to filJdi applied to the transfer signal ΦH1 of the other horizontal charge transfer section. Next, in order to cut off the transfer gate, the level of the signal ΦHHG is changed from a high level to a low level, as shown in FIG. 5(C). And Figure 5 (
As shown in d), when the level of the signal ΦHHG becomes completely low, the two horizontal charge transfer sections are electrically separated, and the distribution is completed.

[Problem to be solved by the invention]

However, the charge transfer between the horizontal charge transfer sections described above has the following problems.

In other words, at the end of the charge transfer between the horizontal charge transfer sections, it is necessary to put the transfer gate between the two horizontal charge transfer sections into the cutoff state, but at the time of the level transition to put the transfer gate into the cutoff state, the transfer gate A portion of the charge existing in the channel region below the horizontal charge transfer section is also returned to the original horizontal charge transfer section, degrading the transfer efficiency.

SUMMARY OF THE INVENTION In view of the above-mentioned technical problems, the present invention aims to provide a solid-state image sensor that improves the transfer efficiency between horizontal charge transfer sections.

[Means to solve the problem]

A solid-state image sensor of the present invention that achieves the above-mentioned object includes a plurality of light receiving sections arranged in a matrix, and a plurality of light receiving sections provided for each vertical column of the light receiving sections to transfer charges from the light receiving sections in the vertical direction. It has a vertical charge transfer section and a plurality of horizontal charge transfer sections that transfer charges from the vertical charge transfer sections in the horizontal direction.

An accumulation section including a second vertical charge transfer section may be provided between the vertical charge transfer section adjacent to the light receiving section and the horizontal charge transfer section.

Further, in the solid-state image sensor of the present invention, the gate voltage of the transfer gate that controls the transfer between the plurality of horizontal charge transfer sections is set at a point in the middle of the transition of the gate voltage when the charge transfer between the horizontal charge transfer sections is completed. It is characterized by being temporarily set to an intermediate voltage or by making a transition slower than the normal transition of the gate voltage.

Here, the temporary setting to the intermediate voltage is, for example, 2
This can be realized by increasing the intermediate level of a value pulse to make it a three-value pulse, and the slow transition can be realized by changing the time constant of charging the gate electrode, for example, by increasing the gate capacitance.

[Effect]

At the end of the charge transfer between the horizontal charge transfer sections, the gate voltage of the transfer gate that controls the transfer between the horizontal charge transfer sections is made to transition through an intermediate voltage or more slowly than usual, so that the gate voltage of the gate electrode can be changed. After the charges in the lower channel region are sufficiently transferred to the horizontal charge transfer section as a transfer destination, the transfer gate can be turned off. Therefore, the disadvantage that the charge applied to the transfer gate is reversely transferred to the horizontal charge transfer section of the transfer source is prevented, and the transfer efficiency is improved.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

This embodiment is an example of a FIT (frame interline transfer) type CCD image sensor, which has two horizontal charge transfer sections to reduce the horizontal charge transfer frequency.

FIG. 1 is a schematic plan view thereof. As shown in FIG. 1, the CCD image sensor 1 of this embodiment includes an imaging section 2 that generates signal charges by photoelectric conversion, an accumulation section 3 that temporarily accumulates the signal charges, and a horizontal charge transfer section. The main components are a first horizontal register 4, which is a horizontal charge transfer section, and a second horizontal register 5, which is also a horizontal charge transfer section, and these are formed on a silicon substrate using semiconductor manufacturing technology.

The imaging section 2 has light receiving sections 6 arranged in a matrix, and each of these light receiving sections 6 performs photoelectric conversion of incident light. These light receiving sections 6 are made up of, for example, an n-type silicon substrate, an n-type impurity diffusion region formed in a p-well, and an n-type hole accumulation layer on the surface, and have a pnpn structure in order from the surface. Ru. Along each vertical column of each light receiving section 6, a first vertical register 7 is provided for each vertical column. These first vertical registers 7 transfer charges from the light receiving section 6 in the vertical direction. In each of these first vertical registers 7, a buried channel layer for transferring charges is formed on a silicon substrate, and a plurality of transfer electrodes are formed on the buried channel layer with an insulating film interposed therebetween.

The transfer electrode of this first vertical register 7 has a transfer signal Φ
IMI to ΦIM4 are supplied.

A plurality of second vertical registers 8 are formed in the storage section 3 so as to be electrically continuous with the first vertical register 7, and the number of the first vertical registers 7 and the second vertical registers 8 is One-on-one correspondence. Smear is reduced by transferring signal charges from the first vertical register 7 to the second vertical register 8 at high speed during the vertical blanking period. These second vertical registers 8 have transfer signals ΦSTI to ΦST4.
is supplied.

A gate 9 is provided between the storage section 3 and the first horizontal register 4, and this gate 9 is controlled by a signal ΦVH. When the signal ΦVH is at a high level, the gate 9 is in a conductive state, and when the signal ΦVH is low and in a healthy state, the gate 9 is in a cut-off state.

The first horizontal register 4 and the second horizontal register 5 are provided in parallel with each other at the vertical end of the storage section 3 via a gate 9. Transfer electrodes are formed in the first horizontal register 4 and the second horizontal register 5, and transfer signals ΦH1 and ΦH2 having phases opposite to each other during high-speed transfer are supplied to these transfer electrodes. Ru. A transfer gate 10 is provided between the first horizontal register 4 and the second horizontal register 5, and controls transfer between these two horizontal registers. A signal ΦHHG is supplied to the transfer gate 10, and the level of this signal ΦHHG controls the transfer between the two horizontal registers.

At the end of each horizontal register 4.5, a floating diffusigon area 21, 22 is provided, respectively. Each floating diffusitane eMM21.2
2 are connected to each amplifier 23 and 24, and the signal charges are converted into voltages, and the output signals Vout+ and Vout+,
Vout- is output. In addition, each floating differential region 21° 22 has a reset gate 1-25.
．． 25 to a reset drain region 26.26 to which voltages VRDI and VRD2 are applied.

Therefore, reset gate 25, 25! The floating differential regions 21 and 22 are reset (precharged) by the applied signal ΦRG.

Further, a smear gate electrode 27 to which a signal ΦSG is applied is provided on the side of the horizontal register 5, and a smear drain region 28 to which a voltage VSD is applied is formed along the smear gate electrode 27. Ru. By these smear gate electrode 27 and smear drain region 28,
The square charge is swept away.

FIG. 2 is a plan view of a portion of two horizontal registers 4.5. These two horizontal registers 4.5 are connected to transfer gate 1
In particular, the first horizontal register 4 is provided sandwiched between a gate 9 made of a first layer of polysilicon layer and a transfer gate 10, which are indicated by dashed lines in the figure. The second horizontal register 5 has its transfer gate 10
Similarly, it is provided between smear gate electrodes 27 made of the first polysilicon layer. Each horizontal register 4, 5 has a second polysilicon layer and a third polysilicon layer, respectively.
A plurality of transfer electrodes 11 and 12 each made of a polysilicon layer are arranged. The transfer electrode 11 is formed by patterning the second polysilicon layer as shown by the solid line in the figure, and the direction (■) in the figure is the longitudinal direction. It is bent by about the line width in the -H direction on the transfer gate 10 so that it does not become distorted, and has a substantially rectangular shape on each horizontal register 4.5. The plurality of transfer electrodes 11 are spaced apart from each other at regular intervals in the H direction, and are arranged in a third pattern so as to cover the spaced areas and have their ends overlapped with the transfer electrodes 11, as shown by broken lines in the figure. A transfer electrode 12 made of a second polysilicon layer is formed. Like the transfer electrodes 11, these transfer electrodes 12 also have a longitudinal direction in the V direction in the figure, but a line is placed in the -H direction on the transfer gate 10 so that the electrodes spanning the two horizontal registers 4.5 are not on a straight line. It is bent about the width, and has a substantially rectangular shape on each horizontal register 4.5, with both side portions in the H and −H directions overlapping the transfer electrode ll. Transfer signals ΦH1 and ΦH2 are alternately supplied to these transfer electrodes 11 and 12 for each transfer electrode. Therefore, one of the transfer electrodes 12 adjacent to any transfer electrode 11 is always given a transfer signal of the same phase.
In this embodiment, an in-phase transfer signal ΦH1 or ΦH2 is applied to the transfer electrode 12 adjacent to the -H side of the transfer electrode 11. Furthermore, when the same voltage is applied, the potential well of the lower channel layer of the transfer electrode 11 is made deeper than that of the lower channel layer of the transfer electrode 12.
The side serves as a storage section, and the transfer electrode 12 side functions as a transfer section.

A second layer is formed on the surface of the silicon substrate below the transfer gate 10.
In the figure, channel stop flJi area 1 indicated by the shaded area
3 are provided, and the area sandwiched between these channel stop areas 13 is defined as a channel area 14. This channel region 14 is located under the transfer gate 10 in the H direction and the
Both patterns are provided diagonally with respect to the direction, and are arranged to cross the direction in which the transfer electrodes 11 and 12 are bent. This channel region 14 is the first
Area 1 controlled by transfer signal ΦH2 of horizontal register 4 of
5 and a region 16 controlled by the transfer signal ΦH1 of the horizontal register 5 are provided so as to face each other at both ends thereof.

Since the channel region 14 is provided continuously to the region 15 controlled by the transfer signal ΦH2 of the first horizontal register 4, the region controlled by the transfer signal ΦH2 of the first horizontal register 4 is continuous to the channel stop region 13. do. Therefore, even if the gate voltage of the transfer gate 10 becomes high, charges will not be transferred from the region of the first horizontal register 4 controlled by the transfer signal ΦH1 to the next horizontal register 5. Note that a channel stop region 17 is also provided below the gate 9 of the first horizontal register 4 on the side of the storage section 3, as indicated by a hatched region in the figure.

In the CCD imager of this embodiment having such a first horizontal register 4 and a second horizontal register 5, data is transferred between the horizontal registers in order to reduce the horizontal transfer frequency. In FIG. 2, the circles represent the charges transferred by the first horizontal register 4, which are transferred from the storage section 3 to the area controlled by the transfer signal ΦH1 of the first horizontal register 4. Therefore, it remains in its first horizontal register 4. On the other hand, the charges indicated by black circles in the figure represent the charges transferred to the second horizontal register 5 via the first horizontal register 4.
In order to be transferred from the storage section 3 to the area 15 controlled by the transfer signal ΦH1, the signal is transferred to the area 16 of the second horizontal register 5 via the channel area 14.

Next, with reference to FIG. 3 and FIGS. 4(a) to 4(d), the transfer between the horizontal registers corresponding to the black circles in FIG. 2 will be explained.

First, the signal ΦHHG supplied to the transfer gate lO
becomes a high level, the transfer gate 10 becomes conductive, and then the transfer signals ΦH1 and ΦH2 supplied to the transfer electrodes 11 and 12 both become low level, so that the first horizontal register 4' 4M15 charges are transferred at least to the channel region 14. At this time, the potential state is such that only the potential in the region applied to the signal ΦHHG is depressed, as shown in FIG. 4(a).

Subsequently, at time t1 in FIG. 3, the level of the signal ΦH1 that controls the area 16 of the second horizontal register 5, which is the transfer destination, changes from a low level to a high level.

Then, as shown in FIG. 4(b), the potential of the region 16 applied to the signal ΦH1 becomes deeper, and the charge is transferred to the region 16.
will be forwarded to.

Next, at time t2 in FIG. 3, the signal ΦHHG applied to the transfer game 10 is not caused to transition from a high level to a low level, but from a high level to an intermediate level. Then, as shown in FIG. 4(C), the potential in the region 16 of the second horizontal register 5 becomes deeper than the potential in the channel region 14, and as a result,
The signal charge is sufficiently transferred to the area 16 of the second horizontal register 5.

Then, at time t in FIG. 3, the level of the signal ΦHHG applied to the transfer game 10 is transitioned from the intermediate level to the low level, and the transfer game 10 is placed in a cutoff state. At this time,
Since the charge has already been sufficiently transferred to the second horizontal register 5 side when the signal ΦHHG is set to the intermediate level, a problem such as the charge in the channel region 14 being transferred in the opposite direction does not occur.

The above is an example in which the transition from the high level to the low level of the signal ΦHHG is made from the high level to the intermediate level once at the end of the transfer, and then from the intermediate level to the low level. This is used to transition the level of the signal ΦHHG. Although it is possible to improve the transfer efficiency by such means, the same effect can also be obtained by making the gate voltage transition slower than the normal transition of the gate voltage, as shown by the broken line in the signal ΦHHG in FIG. can be obtained. For example, such a slow transition may be achieved by changing the driving capability of the driver that drives the transfer gate 10, or by adding a capacitance or resistance only when making a slow transition to increase the time constant.

Although the above embodiment is an example of a frame interline transfer type CCD solid-state image sensor, the solid-state image sensor of the present invention may be an interline transfer type CCD solid-state image sensor. Further, the number of horizontal registers is not limited to two, and the solid-state image sensor of the present invention may have a larger number. Further, the transfer signal that drives the horizontal register is not limited to a two-phase signal.

〔Effect of the invention〕

In the solid-state image sensor of the present invention, the transition at the end of the transfer of the transfer gate that controls the transfer between the horizontal charge transfer sections is performed via an intermediate voltage or slowly in time; This eliminates the problem of data being transferred from the channel region at the bottom to the source horizontal charge transfer unit. Therefore, the transfer efficiency between the horizontal charge transfer units is improved, and various image signals of high quality can be transferred. video equipment.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view showing the overall structure of an example of the solid-state image sensor of the present invention, FIG. 2 is a plan view of essential parts of the example,
Figure 3 is a timing chart at the end of transfer between horizontal registers in one example, and Figures 4 (a) to (d) show potential states near the channel area at the end of transfer between horizontal registers in that example. The potential diagrams shown in FIGS. 5(a) to 5(d) are potential diagrams showing the potential state near the channel region at the end of transfer between horizontal registers in the conventional example. l... CCD image middle 2... imaging section 3... storage section 4... first horizontal register 5... second horizontal register 6... light receiving section 7... first Vertical register 8...Second vertical register 10...Transfer gate 11.12...Transfer electrode 13...Channel stop region 14...Channel region 15.16...Area

Claims (2)

[Claims] (1) A plurality of light receiving sections arranged in a matrix, a plurality of vertical charge transfer sections provided for each vertical column of the light receiving sections and vertically transferring charges from the light receiving sections, and the vertical charge transfer. The solid-state imaging device has a plurality of horizontal charge transfer sections that horizontally transfer charges from the horizontal charge transfer sections, and the gate voltage of the transfer gate that controls the transfer between the plurality of horizontal charge transfer sections is determined by the horizontal charge transfer section. 1. A solid-state image sensor, wherein the gate voltage is temporarily set to an intermediate voltage during transition when charge transfer between the two ends. (2) A plurality of light receiving sections arranged in a matrix, a plurality of vertical charge transfer sections provided for each vertical column of the light receiving sections and vertically transferring charges from the light receiving sections, and the vertical charge transfer. The solid-state imaging device has a plurality of horizontal charge transfer sections that horizontally transfer charges from the horizontal charge transfer sections, and the gate voltage of the transfer gate that controls the transfer between the plurality of horizontal charge transfer sections is determined by the horizontal charge transfer section. A solid-state imaging device characterized in that the gate voltage transitions later than the normal transition of the gate voltage at the end of charge transfer between the two.