JPH0325791A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To accurately perform data transfer and to realize a fast access by increasing the resistance of a power source or a ground wire when performing the data transfer, and decreasing the driving capacity of a latch circuit. CONSTITUTION:The data in a storage element 1 on a row selected with a row selection line 2 is amplified with a sense amplifier 4, and appears on column lines 3a and 3b. The data is transmitted to the latch circuits 8-11 with a data transfer signal 7 and data transfer gates 6a and 6b. At this time, a gate voltage is supplied to MOS transistors TR 18 and 19 when a difference between the driving capacity of the amplifier 4 and that of the circuits 8-11 exists, which decreases the conductivity of the TRs 18 and 19. Then, the resistance of the power source 16 and the ground wire 17 are increased, and the driving capacity of the circuits 8-11 are decreased. Thereby, the data transfer can be performed accurately without inverting the amplifier 4, and the fast access can be easily obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to improving the operating margin thereof. [Prior Art] Figure 2 shows an example of a conventional semiconductor memory device. In the figure, 1 is a storage element, 2 is a row selection line, 3a, 3b is a pair of column lines, 4 is a sense amplifier, 5a . 5b is a sense drive signal. This example shows the case of a dynamic memory, which is the main embodiment of the present invention. Components such as the storage element 1 and the sense amplifier 4 are not directly related to the present invention, so their explanation will be omitted. 6a, 6b are data transfer gates, 7 is a data transfer control signal, 8, 9, 10.1
1 are CMOS inverters, which are cross-coupled to form a latch circuit, 12a. 12
b are output contacts of inverters 8, 9, 10.11, 13a. 13b is a column selection gate, 14 is a column selection line, 1
5a. 15b is a pair of input and/or output signal lines. 16 is the power supply wiring of the above latch circuit array, 17 is the same <G
This is ND wiring. Next, we will explain the operation when outputting data. Row selection line 2
The data in the memory element 1 in the row selected by is amplified by the sense amplifier 4 and the sense drive signal 5 and sent to the column lines 3a,
Appears in 3b. This data is the data transfer control signal 7,
Data transfer game}6a. 6b connects the output contact 12a,
12b, and is held in latch circuits 8 to 1l even after transfer gates 6a and 6b are closed. The data held in this way is transferred to the column selection gate 413a by the column selection line 14.
, 13b are activated, the input/output signal line 15a
, 15b. [Problems to be Solved by the Invention] Since the conventional semiconductor memory device is configured as described above, if the transistor size of the latch circuits 8 to 11 is too large compared to the size of the sense amplifier 4, the drive of the latch circuit becomes difficult. There were problems in that if the drive capacity was larger than the drive capacity of the sense amplifier, the sense amplifier would be inverted during data transfer, and if it was too small, the data output speed to the output signal line pair would be slow. The present invention was made to solve the above-mentioned problems, and it is possible to perform data transfer accurately, widen the data transfer margin, and without slowing down the data output speed to the output signal line pair. The purpose is to provide a semiconductor memory device that enables high-speed access. [Means for Solving the Problems] A semiconductor memory device according to the present invention includes a plurality of storage elements, row selection lines, column line pairs. and a memory array connected to the sense amplifier, a latch circuit array consisting of two inverters attached to each column line pair, and a switching circuit provided between the column line pair and the latch circuit. and means for varying the resistance of the power supply or GND line connected to the latch circuit array. [Function] In the semiconductor memory device of the present invention, during data transfer, the resistance of the power supply or GND line connected to the latch circuit array is increased to lower the drive capability of the latch circuit, thereby eliminating the risk of sense amplifier inversion. When outputting data to a pair of signal lines, high-speed data output and, in turn, high-speed access can be achieved by restoring the drive capability of the latch circuit. [Example] An example of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention, and in the figure, the same reference numerals as in FIG. 2 indicate the same parts. 18.19 is a MOS as a means for varying the resistance of the power supply or GND line connected to the latch circuit array
A transistor whose conductivity changes depending on the voltage applied to its gate. Next, we will explain the operation. The data in the storage element 1 in the row selected by the row selection line 2 is amplified by the sense amplifier 4 and sent to the column line 3a. Appears in 3b.

This data is the data transfer signal 7, data transfer gate 6a
, 6b to the latch circuits 8-11. At this time, even if the drive ability of the sense amplifier 4 is small due to defects in the manufacturing process and there is a difference between the drive ability of the latch circuits 8 to 11, the MO
So that the conductivity of the S transistors 18 and 19 is low,
When a moderate gate voltage is applied to the MOS} transistors 18 and 19, the resistance of the power supply or GND'a connected to the latch circuits 8 to 11 increases, thereby reducing the drive ability of the latch circuit. 8～
11 no longer inverts the sense amplifier 4, and data can be easily transferred. The above MOS} transistor 18 is used except when transferring the above data.
By adjusting the gate voltages of the latch circuits 8 to 19 to increase their conductivity and making them in the same state as the conventional circuit, the latch circuits 8 to 11 can be used even when outputting data to the output signal line pair.
stability of There is no longer any risk of access speed being affected.
You can easily get high-speed access.

〔Effect of the invention〕

As described above, according to the present invention, means is provided for varying the resistance of the power supply or GND line connected to the latch circuit array,
During data transfer, the resistance of the 'gl source or GND line is increased to reduce the drive ability of the latch circuit, so there is no fear that the sense amplifier will be inverted during data transfer, and the data transfer margin can be expanded. I can do it,
In addition, there is an effect that high-speed access can be easily obtained without slowing down the data output speed to the output signal line pair except during data transfer.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional semiconductor memory device. In the figure, l is a storage element, 2 is a row selection line, 3a. 3b is a column line pair, 4 is a sense amplifier, 5a and 5b are sense drive signals,
6a and 6b are data transfer gates, 7 is a data transfer control signal, and 8, 9.10.11 is a CMO that constitutes a latch circuit.
S inverter, 12a and 12b are inverter output contacts, 13a and 13b are column selection gates, 14 is a column selection line, 1
5a51 5b C Output signal line pair, 16411km wiring, 17 is GND wiring, 1B, i9 are MOS transistors (resistance variable means).

Claims (1)

[Claims] (1) A memory array consisting of a plurality of storage elements, row selection lines, column line pairs, and sense amplifiers, and a latch circuit array consisting of two inverters attached to each column line pair; A semiconductor memory device comprising: switching means provided between a column line pair and the latch circuit array; and means for varying the resistance of a power supply or ground line connected to the latch circuit array. .