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JPH03257843A - Evaluation of semiconductor substrate - Google Patents

Evaluation of semiconductor substrate

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Publication number
JPH03257843A
JPH03257843A JP5596890A JP5596890A JPH03257843A JP H03257843 A JPH03257843 A JP H03257843A JP 5596890 A JP5596890 A JP 5596890A JP 5596890 A JP5596890 A JP 5596890A JP H03257843 A JPH03257843 A JP H03257843A
Authority
JP
Japan
Prior art keywords
attenuation coefficient
ellipsometry
wafer
semiconductor substrate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5596890A
Other languages
Japanese (ja)
Inventor
Yasuhito Nakagawa
中川 泰仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP5596890A priority Critical patent/JPH03257843A/en
Publication of JPH03257843A publication Critical patent/JPH03257843A/en
Pending legal-status Critical Current

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  • Investigating Or Analysing Materials By Optical Means (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To simultaneously evaluate a natural oxide film, etc., which cannot be evaluated by a PBS method with machining damage evaluation by measuring the attenuation coefficient of a semiconductor substrate using ellipsometry. CONSTITUTION:In ellipsometry, He-Ne gas laser having a wavelength of 6328Angstrom is used and the intrinsic attenuation coefficient k0 of a complete GaAs crystal becomes the lowest of 0.211. When the surface of the crystal substrate becomes incomplete by machining damage, etc., as superfluous levels are created in the forbidden band, the symmetric property of Bloch function is destroyed and the attenuation coefficient increases according to the destruction. Therefore, the increase of (k-k0), which shows the attenuation coefficient increase, becomes the barometer of the substrate surface crystal incompleteness and the increase of the machining damage. In ellipsometry, a wafer 1 has a large attenuation coefficient (k) by a natural oxide film formed on the surface. Therefore, a wafer having a small value of (k) has a less natural oxide film, surface defects, machining damage, etc.

Description

【発明の詳細な説明】 く産業上の利用分野〉 本発明は、偏光解析法とも言われるエリプソメトリによ
シ半導体基板の表面における特性を評価する方法に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for evaluating characteristics on the surface of a semiconductor substrate by ellipsometry, also called ellipsometry.

〈従来の技術〉 特性のよい半導体デバイスの高集積化、高歩留の確立に
は、特性のよい均一な半導体基板を用いる必要である。
<Prior Art> In order to achieve high integration and high yield of semiconductor devices with good characteristics, it is necessary to use a uniform semiconductor substrate with good characteristics.

例えばGaAsのデジタ1vICに於て高速化、高集積
化及び高歩留を実現するには、その構成素子であるGa
As  MESFETのしきい値電圧(vth )を設
計値の中心値とし、しかも使用した基板に於て均一にす
る必要がある。以上のGaAs  MESFETの作製
に於て、vthO値を決める能動層の形成に、制御性の
良いイオン注入法が広く用いられている。このイオン注
入法で製造しても、そのGaAs  MESFETのv
thが不均一になる原因として、ゲート長Lgや絶縁膜
の膜厚分布のバラツキなど製造プロセスによるものもあ
るが、ここでは半導体基板における転位、深い準位EL
2、加工による損傷などに起因するバラツキに関する評
価方法について説明する。この半導体基板におけるバラ
ツキは前記の例のMESFETでは能動層のバラツキと
なる。この能動層のバラツキに対して転位やEL2によ
る影響は従来から多くの研究がなされ、種々の説がださ
れている。又、近年になって注目されているのは、研磨
時の加工損傷の分布に関連する影響である。
For example, in order to achieve high speed, high integration, and high yield in a GaAs digital 1vIC, it is necessary to
It is necessary to set the threshold voltage (vth) of the As MESFET to a central design value and to make it uniform across the substrates used. In manufacturing the above GaAs MESFET, the ion implantation method with good controllability is widely used to form the active layer that determines the vthO value. Even if manufactured using this ion implantation method, the v
The non-uniformity of th can be caused by the manufacturing process, such as variations in the gate length Lg or the thickness distribution of the insulating film, but here we will discuss dislocations in the semiconductor substrate, deep levels EL
2. An evaluation method regarding variations caused by damage caused by processing, etc. will be explained. This variation in the semiconductor substrate results in variation in the active layer in the MESFET of the above example. Many studies have been conducted on the influence of dislocations and EL2 on this variation in the active layer, and various theories have been proposed. Also, in recent years, attention has been paid to the effects related to the distribution of machining damage during polishing.

一般に、半導体基板は引き上げで単結晶に成長させたイ
ンゴットをスライスしてウェハにし、機械研磨によシ平
滑化した上、その研磨による加工損傷を化学エツチング
によって除去してbるが、前記の半導体基板の加工損傷
は、この加工損傷がエツチングにより除去しきれないで
基板の表面に残留しているものである。
In general, semiconductor substrates are produced by slicing an ingot grown into a single crystal by pulling it into wafers, smoothing it by mechanical polishing, and removing processing damage caused by the polishing by chemical etching. Processing damage to the substrate is that processing damage that cannot be completely removed by etching and remains on the surface of the substrate.

以上の加工損傷の残留によフ転位などの格子欠陥の発生
や格子定数に歪などを生じるので、作製したMESFE
Tのvthが不均一になった。従来この加工損傷はPB
S法(Photon Back  Scatterin
g )によシ検知して、評価していた。(このPBS法
による評価は、例えばR、C、C1arket aL、
  ”5urface damage  in sem
i−insulatingGaAs 5tibStra
teS” 、 GaAs ICSyml)−、p、 4
1.1987 ナトVC説明すレ”Cイル。)以上のP
BS法は、半導体基板表面をレーザビームで走査し、加
工損傷の残留に起因する欠陥(表面のでこぼこ、異物の
など含めて)による散乱度を検知して評価する方法であ
る。
The remaining machining damage causes lattice defects such as F dislocations and distortions in the lattice constants, so the fabricated MESFE
The vth of T became uneven. Conventionally, this machining damage is PB
S method (Photon Back Scatterin)
g) was detected and evaluated. (Evaluation by this PBS method, for example, R, C, C1arket aL,
”5 surface damage in SEM
i-insulatingGaAs 5tibStra
teS”, GaAs ICSyml)-, p, 4
1. 1987 Nato VC explanation Les “Cile.) Above P
The BS method is a method in which the surface of a semiconductor substrate is scanned with a laser beam, and the degree of scattering due to defects (including surface irregularities, foreign matter, etc.) caused by residual processing damage is detected and evaluated.

〈発明が解決しようとする課題〉 以上で説明したPBS法は、加工損傷の残留による欠陥
の評価方法として広く用いられている。
<Problems to be Solved by the Invention> The PBS method described above is widely used as a method for evaluating defects due to residual machining damage.

しかし、こ(2)PBS法は、半導体基板表面の粗さや
欠陥は感度よく検出できるが、他の例えば半導体基板の
表面に均一な自然酸化膜(native−oxide:
半導体基板を大気中に放置したときなどに、その表面に
自然に形成される酸化層)が覆っている場合は、その評
価ができないという問題がある。
However, although this (2) PBS method can detect roughness and defects on the surface of a semiconductor substrate with high sensitivity, it can detect other defects such as a uniform native oxide film (native-oxide) on the surface of a semiconductor substrate.
There is a problem in that if a semiconductor substrate is covered with an oxide layer (which naturally forms on the surface when it is left in the atmosphere), it cannot be evaluated.

本発明は、従来の加工損傷の評価方法として用に評価で
きる半導体基板の評価方法を提供することを目的として
いる。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor substrate evaluation method that can be used as a conventional processing damage evaluation method.

〈課題を解決するだめの手段〉 本発明は、エリプソメトリを用いた半導体基板の減衰係
数の測定から、PBS法によるのと同じエリプソメトリ
による半導体基板の評価は一般にエツチングダメージや
イオン注入ダメージの評価に用いられている。(例えば
、K、 Watanabeet  al、、  “El
lipsometric  5tudy  ofsil
icon  1nplanted  with  Bo
ron  Ionsin  low  doses?、
Appl+Phys+Lett+、84゜p518.1
979など)。
<Means for solving the problem> The present invention is based on the measurement of the attenuation coefficient of a semiconductor substrate using ellipsometry, and the evaluation of a semiconductor substrate by ellipsometry, which is the same as the PBS method, is generally used to evaluate etching damage and ion implantation damage. It is used in (For example, K. Watanabee et al., “El
lipometric 5tudy ofsil
icon 1nplanted with Bo
Ron Ionsin low doses? ,
Appl+Phys+Lett+, 84°p518.1
979 etc.).

エリプソメトリによる評価に於て、半導体基板する評価
も行なうことができる。
In the evaluation by ellipsometry, it is also possible to evaluate semiconductor substrates.

ここで、エリプソメトリによシ評価する半導体基板の度
射率をR1吸収係数をα、透過率をTとすると、次の関
係がある。
Here, if the emissivity of the semiconductor substrate to be evaluated by ellipsometry is R1, the absorption coefficient is α, and the transmittance is T, then the following relationship exists.

R=[(n−1)2+に2]/[(n+1)2+に2]
・・・(1)α=4πに/λ ・・・(2) T=(1−R2)exp(−αyD、4l−R2exp
(−2αX)]  −−−(3)こ−で、λは入射レー
ザ光の波長、nは半導体の屈折率、kは減衰係数、Xは
侵入深さである。
R = [2 to (n-1)2+]/[2 to (n+1)2+]
...(1) α=4π/λ ...(2) T=(1-R2)exp(-αyD, 4l-R2exp
(-2αX)] - (3) where λ is the wavelength of the incident laser beam, n is the refractive index of the semiconductor, k is the attenuation coefficient, and X is the penetration depth.

上記の(2)式から吸収係数σは、減衰係数と一次相関
であり、エリプソメトリではnとkが求められるのでk
で評価する方が作業が簡単になる。従って、以下の説明
ではkを用いる。(勿論、換算は容易であるからnを用
いてもよい。) 一般に、エリプソメトリに於ては波長が6328AのH
e−Neガヌレーザが用いられ、本発明のは0.211
の最低になり、加工損傷などで結晶基板の表面が乱れる
とその禁止帯のなかに余分な準位ができることでブロッ
ホ関係の対象性が崩れ、その乱れの程度によって減衰係
数が大きくなる。
From the above equation (2), the absorption coefficient σ is a linear correlation with the attenuation coefficient, and since n and k are found in ellipsometry, k
It is easier to evaluate using Therefore, k will be used in the following explanation. (Of course, conversion is easy, so n may be used.) Generally, in ellipsometry, H with a wavelength of 6328A is used.
An e-Ne Gannulas laser is used, and the inventive one is 0.211
When the surface of the crystal substrate is disturbed due to processing damage, etc., extra levels are created in the forbidden band, destroying the symmetry of the Bloch relation, and the attenuation coefficient increases depending on the degree of the disturbance.

(例えば、M、H,Brodsky  et  al、
(For example, M.H., Brodsky et al.
.

5tructura1. optical and e
lectricalproperties  of  
amorphous  siliconfi1ms’、
、Phys、Rev、B、t p2682.1970)
従って、減衰係数の増大を示す(k−ko)の増大は基
板表面の結晶の不完全性や加工損傷が増大していること
の指標になる。
5tructura1. optical and e
electrical properties of
amorphous siliconfi1ms',
, Phys, Rev, B, t p2682.1970)
Therefore, an increase in (k-ko), which indicates an increase in the attenuation coefficient, is an indicator of an increase in crystal imperfections or processing damage on the substrate surface.

以上で説明したエリプソメトリでも、PBS法と同じよ
うに基板表面の加工損傷などの評価ができることを確認
するため■、■及び■の3種のGaAsウェハについて
、エリプソメトリによフち 基板上を5m間隔で測定bIX減衰係数にの分布を示し
たのが第1図である。この第1図で示した数字は、測定
したkO値から基板上でのkの平均値1caveを引い
て1000倍した値である。つまシ1000 X (k
  kave )を示している。
In order to confirm that the ellipsometry described above can also evaluate processing damage on the substrate surface in the same way as the PBS method, three types of GaAs wafers (■, ■, and ■) were examined using ellipsometry. Figure 1 shows the distribution of bIX attenuation coefficients measured at 5 m intervals. The numbers shown in FIG. 1 are the values obtained by subtracting the average value of k on the substrate 1cave from the measured kO value and multiplying the result by 1000. Tsumashi 1000 X (k
kave).

以上のkの分布図に於て、実線は減衰係数kがウェハ上
で平均値になる。つまシ0になる点を結んだものであり
、−点鎖線は図の数字が10以上になる境界を、又、点
線は図の数字が一10以下になる境界を示している。
In the distribution diagram of k above, the solid line indicates the average value of the attenuation coefficient k over the wafer. It connects the points where the thumbnail is 0, and the - dotted chain line indicates the boundary where the number in the figure becomes 10 or more, and the dotted line indicates the boundary where the number in the figure becomes 110 or less.

以上の第1図に於ける8種の線の示す範囲を見ることで
、そのウェハの加工損傷等の分布の均一性を容品に知る
ことができる。
By looking at the ranges indicated by the eight types of lines in FIG. 1, the uniformity of the distribution of machining damage, etc. on the wafer can be clearly understood.

第1図でウェハIと■の間にkの分布で特に目立った違
いはないが、その平均値は■の方が0.025低い、こ
れはウェハの保存パッケージ方法の差によるものと評価
される。
In Figure 1, there is no noticeable difference in the distribution of k between wafer I and Ru.

次の第2図に示したのは、ウェハ1.■及び■の中心ヲ
通り、各ウェハのオリエンテーションフラットネスに水
平方向にラインスキャンした1の線、及びその垂直方向
にラインスキャンした点線で示したそれぞれのPBS散
乱強度分布と、エリプソメトリの減衰係数分布とを比較
するためのグラフである。この第2図で、加工損傷の大
きいウェハ■においては、上記の2つの評価手段による
評価値の傾向が極めてよく一致している。これは、マク
ロ的に見たとき、レーザビームを散乱させるウェハ表面
の欠陥は同時に減衰率kを増加させる原因にもなってい
る考えられる。ウェハIと■について2つの評価手数に
よる測定曲線の間で微細変化での対応性を見いだすこと
l”m難しい。この原因としては、本測定に用いたエリ
プソメトリの装置がPBS法の装置のように測定点の密
度を高くできなかったので(マニュアル移動のため)P
BS法で測定したウェハ表面の微細変化に対応できなか
ったためと考えられる。
The following figure 2 shows wafer 1. The respective PBS scattering intensity distributions and ellipsometry attenuation coefficients are shown by the line 1 line scanned horizontally to the orientation flatness of each wafer and the dotted line line scanned vertically through the center of ■ and ■. This is a graph for comparing the distribution. In FIG. 2, for wafer (3) with large processing damage, the trends of the evaluation values by the two evaluation means described above are in very good agreement. This is considered to be because, from a macroscopic perspective, defects on the wafer surface that scatter the laser beam also cause an increase in the attenuation rate k. It is difficult to find correspondence in minute changes between the measurement curves of the two evaluation procedures for wafers I and ■.The reason for this is that the ellipsometry equipment used for this measurement is similar to the PBS method equipment. Because it was not possible to increase the density of measurement points (due to manual movement),
This is thought to be due to the inability to respond to minute changes on the wafer surface measured by the BS method.

次の第1表に第1図と第2図で示した各ウェハの水平及
び垂直方向走査によるそれぞれの減衰係数に値及びPB
S散乱信号値の平均値と各ウェハの仕様をまとめて示し
ている。
The following Table 1 shows the values and PB of the respective attenuation coefficients obtained by horizontal and vertical scanning of each wafer shown in Figures 1 and 2.
The average value of the S scattering signal value and the specifications of each wafer are shown together.

第 表 第1表に於て、ウェハ■・は標準的ラップ・プロセス(
機械的及び化学的研磨工程)後普通の空気雰囲気でパッ
ケージして保管したもので、ウェハ■は標準ラップ・プ
ロセスと、乾燥N2雰囲気でノ保管、ウェハmは機械的
研磨のみア、ウエノ刈と同じ保管によるウェハである。
In Table 1, wafers are processed using the standard lapping process (
After mechanical and chemical polishing processes), the wafers were packaged and stored in a normal air atmosphere, wafers were subjected to a standard lapping process and stored in a dry N2 atmosphere, and wafers were subjected to only mechanical polishing and wafer cutting. The wafers are from the same storage.

以上の第1表から、エリプソメトリではウェハIがその
表面に形成された自然酸化膜によってウェハ■よシ大き
い減衰係数kをもつと見ることができるが、PBS法に
よる測定値の間には明確な差がない。この原因は、基板
表面に形成された自とによると考えられる。
From Table 1 above, it can be seen that in ellipsometry, wafer I has a larger attenuation coefficient k than wafer II due to the natural oxide film formed on its surface, but there is a clear difference between the measured values using the PBS method. There is no difference. The cause of this is thought to be the particles formed on the substrate surface.

〈作 用〉 本発明のエリプソメトリによる非破壊の半導基板評方法
は、その基板の減衰係数を測定して、PBS法によって
評価した加工損傷の評価と共にできるので、実用的で効
率のよい半導体基板の評価方法になるものである。
<Function> The non-destructive semiconductor substrate evaluation method using ellipsometry of the present invention can be performed in conjunction with the evaluation of processing damage by measuring the attenuation coefficient of the substrate and the PBS method, so it is a practical and efficient semiconductor evaluation method. This is a method for evaluating the board.

〈実施例〉 以下、本発明の実施例を図面を参照しながら説明する。<Example> Embodiments of the present invention will be described below with reference to the drawings.

本実施例に用いた半導体基板は径が2インチの高抵抗G
aAsウェハであシ、これらのウェハを入手経路側と、
半導体結晶の成長方法や不純物量などウェハの種類で分
類してウニへ分類の番号をつけて表にしたのが第2表で
ある。
The semiconductor substrate used in this example has a diameter of 2 inches and has a high resistance G
aAs wafers, and the source of these wafers,
Table 2 categorizes the wafers by type of wafer, such as semiconductor crystal growth method and amount of impurities, and assigns classification numbers to each type.

第 表 以上の各種のウェハについて、第1図での説明と同じ方
法により、エリプソメトリによるウェハの減衰係数にの
分布を示したのが第8図であシ、エバ分類の番号との対
応は、この第3図の(a)。
Figure 8 shows the distribution of wafer attenuation coefficients measured by ellipsometry using the same method as explained in Figure 1 for the various wafers listed above, and the correspondence with the EVA classification numbers is shown in Figure 8. , (a) of this Figure 3.

・・・(g)で対応させている。更に、この図における
t(1)、 ID、・・・は同じ分類のウェハ数枚につ
いて定し、それぞれの結果を示している。各図に付記し
たave、とdevi、は測定した各ウェハについての
減衰係数にの平均値とその分散を示している。第2表の
に値平均値は、その分類の番号のウェハの全測定値の平
均値である。
...(g) corresponds to this. Furthermore, t(1), ID, . . . in this figure are determined for several wafers of the same classification, and the respective results are shown. Ave and devi added to each figure indicate the average value and variance of the measured attenuation coefficient for each wafer. The average value in Table 2 is the average value of all measured values for wafers with that classification number.

以上のエリプソメトリによる半導体基板上のに値及びそ
のkの分布を示す第8図からそれぞれの入手経路ごとに
特徴をもっておシ、特にkの分布に於て、平均値を示す
実線を注目して見ると特徴のあるパターンが形成されて
いることが分る。このようなパターンの差違は、前記の
第1図での説明で述べたように自然酸化膜の分布に起因
するとも考えられるが、これだけでは入手経路で異なる
エバメーカ毎に特徴をもったパターンが形成さパターン
の関係を調べるためHCI 処理を行った結果を示した
のが第4図である。この第4図(a)はHCIによる自
然酸化膜除去前のウェハのkとその分布を示しておシ同
図の(b)、 (C)及び(d)は、それぞれHCI処
理後、自然放置で24時間、48時間及び72時経過し
たときのkとその分布を示している。この第4図の経過
を見るとMCI処理パターンは、HCI 処理亘後は多
少変化しても、その後の経過時間とともにMCI処理前
のパターンに近すいている。以上からたとえ本発明のエ
リプソメトリによるkの評価が主として半導体表面に形
成された自然酸化膜を対象にしていても、その膜の成長
も下地になってbるGaAs基板やその加工損傷などが
ウェハメーカ毎に異なっていることが、入手経路毎にに
分布パターンを類似させている要因であると考えられる
From Figure 8, which shows the above ellipsometry values and the distribution of k on a semiconductor substrate, we have shown the characteristics of each acquisition route, and in particular, in the distribution of k, pay attention to the solid line showing the average value. When you look at it, you can see that a distinctive pattern is formed. These differences in patterns may be due to the distribution of the natural oxide film, as mentioned in the explanation for Figure 1 above, but this alone does not mean that patterns with characteristics are formed for each evaporator manufacturer, which differs depending on the route of acquisition. FIG. 4 shows the results of HCI processing to examine the relationship between the patterns. Figure 4 (a) shows the k and its distribution of the wafer before the natural oxide film is removed by HCI, and (b), (C) and (d) of the same figure show the k of the wafer before removing the native oxide film by HCI, and Figure 4 (b), (C) and (d) show the k of the wafer after HCI treatment. shows k and its distribution after 24 hours, 48 hours, and 72 hours. Looking at the progress in FIG. 4, even though the MCI processing pattern changes somewhat after the HCI processing, it approaches the pattern before the MCI processing as time elapses. From the above, even if the evaluation of k by ellipsometry of the present invention mainly targets the natural oxide film formed on the semiconductor surface, the growth of that film may also cause damage to the underlying GaAs substrate or its processing damage, etc. It is thought that the fact that they are different from each other is a factor that makes the distribution patterns similar depending on the acquisition route.

従って、ウェハの入手経路毎にエリプソメトリによる評
価の特徴をまとめるのも意味があると考え、次のように
まとめた。
Therefore, we thought it would be meaningful to summarize the characteristics of evaluation by ellipsometry for each wafer acquisition route, and summarized them as follows.

1)A−1 平均のkがやや高い。しかし、その平均値線はウェハの
周辺にあシ中央部は均一であシ、最も良好な分布と言え
る。
1) A-1 Average k is slightly high. However, the average value line is uniform at the periphery of the wafer and at the center of the reed, which can be said to be the best distribution.

これらflA−1とほぼ同じkの分布で、ドーパントの
違いでkの分布パターンFi夏らない。
The distribution of k is almost the same as flA-1, but the distribution pattern of k is different due to the difference in dopants.

しかもその平均[は低くなっている。Moreover, the average [is] getting lower.

8)B−1 にの平均値は最も低い。平均値線がウェハの中央部にか
け帯状になっているが均一性はよい。
8) The average value for B-1 is the lowest. Although the average value line is band-like toward the center of the wafer, the uniformity is good.

4)C−1 kC)分布は複雑で(4回対象パターンン、平均値が高
く、良いウェハと言えない。
4) C-1 kC) The distribution is complicated (four target patterns, the average value is high, so it cannot be said that it is a good wafer.

前記Aとほぼ同じkの分布パターンであ)、A−1に近
いkの平均値になっている。この低度素濃度はC〜2.
4 X 1014cx  、  高炭素濃度はC〜2.
4 X 1015os”程度である。
The distribution pattern of k is almost the same as that of A), and the average value of k is close to A-1. This low elementary concentration is C~2.
4 X 1014cx, high carbon concentration is C~2.
It is about 4×1015os”.

6)D−1 前記+2)BとCの平均という特徴で、特に定まった傾
向はなくkC)分布のバラツキはかなシ大きい。しかし
、その平均値は低い方である。
6) D-1 Above +2) It is characterized by the average of B and C, and there is no particular tendency, and the variation in kC) distribution is quite large. However, the average value is on the low side.

以上を総合してしてみると、kの分布が均一なのは、A
とC−2,8であり、その平均値の低いのはBである、
と言える。
Taking all the above into account, we can see that the distribution of k is uniform because A
and C-2,8, and the one with the lowest average value is B.
I can say that.

続いて、以上で本発明のエリプソメトリにより評価した
基板によりFETを作製し、そのFETの特性分布との
比較を行った。FETを作製したのは、第2表に示した
各種ウェハから選択したウェハによるものである。
Subsequently, an FET was manufactured using the substrate evaluated by the ellipsometry of the present invention as described above, and a comparison was made with the characteristic distribution of the FET. The FET was fabricated using wafers selected from the various wafers shown in Table 2.

作製したFETの形状は断面図が第5図のようになって
おフ、このFET作製プロセスと、主要部の寸法は第3
表に示したようになっている。
The cross-sectional view of the manufactured FET is as shown in Figure 5.The FET manufacturing process and dimensions of the main parts are shown in Figure 3.
It is as shown in the table.

8g 8 表 即ち、半絶縁性のGaAs基板に低濃度にn形不純物を
イオン注入した上、急速アニール(RTA)して不純物
の活性化し、ゲートとソース及びドレインの金属電極を
リフト・オフ工程によって作製している。
8g 8 Table In other words, n-type impurities are ion-implanted at a low concentration into a semi-insulating GaAs substrate, the impurities are activated by rapid annealing (RTA), and the gate, source, and drain metal electrodes are removed by a lift-off process. It is being produced.

作製したFETについて、各種ウェハにM応させた、基
板ノシート抵抗、F ETclVth 、 K (=μ
ξ/2aLg)、I dss  についての平均値とそ
の分散をまとめたのが第4表である。更に、各種ウェハ
に対応するショットキ特性を表すn値、バリアントφb
とその分散を示したのが第5表である。
Regarding the fabricated FET, the substrate sheet resistance, FETclVth, K (=μ
Table 4 summarizes the average values and variances of ξ/2aLg) and I dss . Furthermore, the n value and variant φb representing Schottky characteristics corresponding to various wafers are
Table 5 shows this and its variance.

第5表 各種基板ショ ットキ特性比較 更に、第6図に減衰係数とFETのVth O分散との
相関を示したが、かなシよい相間々係を示している。
Table 5: Comparison of Schottky characteristics of various substrates Further, FIG. 6 shows the correlation between the attenuation coefficient and the Vth O dispersion of the FET, and it shows a very good correlation.

次の第7図(a)にショットキー特性Onとに値の関連
、同図(b)にnの分散(σn)とに値の関連を示して
いる。しかしこの第f図に於ては7明確な相関は見出せ
ない。第8図(a)にバリアハイドφb、!:に値の比
較をしているが明確な相関は見出せない。
The following FIG. 7(a) shows the relationship between the Schottky characteristic On and the value, and FIG. 7(b) shows the relationship between the value and the dispersion of n (σn). However, in this figure f, no clear correlation can be found. In FIG. 8(a), barrier hide φb,! : I am comparing the values, but I can't find a clear correlation.

し≠1し、同図(b)のφbの分散とに値の間にはかな
り明白な一次の相関があることが分る。
≠1, and it can be seen that there is a fairly clear first-order correlation between the value and the variance of φb in FIG.

以上の各図で示したことから、k値はσvth及びσφ
bとよい相関があることが分る。これらの値には次のよ
うな関係で関連していることにもよると考えられる。
From what is shown in each of the above figures, the k value is σvth and σφ
It can be seen that there is a good correlation with b. This may be due to the fact that these values are related in the following relationship.

Vth=φb −Vp ” (6Vth)” = At Co $b)2+A2
(’Vp)2(AlとA2は相関係数) 以上、測定したに値と、そのウェハで作製したデバイス
の特性の間の相関を調べたもので、相関関係のとシ方に
よっては更に有用な関連を見出すことができる。つまフ
、デバイス作製工程前の搬入したウェハのに値が小さい
ときは、バリアハイドφbのばらつきが小さくなフ、又
、スレッシュホルド電圧の分散σvthも小さくなり、
また、良好なショットキ特性が得られやすい。以上の相
関関係の理由は明確ではないかに値の小さいウェハでは
自然酸化膜、表面欠陥及び加工損傷等が少ないことを示
し、これがφb(Dばらつきを小さくするなどの原因に
なっていると考えられる。
Vth=φb −Vp ” (6Vth)” = At Co $b)2+A2
('Vp)2 (Al and A2 are correlation coefficients) The above is a study of the correlation between the measured value of 2 and the characteristics of devices fabricated using the wafer, and depending on the correlation, it may be even more useful. relationships can be found. When the value of the wafer carried in before the device fabrication process is small, the variation in the barrier hide φb is small, and the variance σvth of the threshold voltage is also small.
In addition, good Schottky characteristics are easily obtained. The reason for the above correlation is not clear, but wafers with smaller values indicate fewer natural oxide films, surface defects, processing damage, etc., and this is thought to be the cause of reducing the variation in φb (D). .

以上の本発明によるエリプソメトリの減衰係数kを測定
する半導体基板の評価の実施例ではGaAsの基板で説
明したが、本発明の半導体基板の評価方法の対象はGa
As基板に限定されるものでなく、SiやInP等の半
導体についても同様に評価することができ、それぞれの
基板について非破壊の評価を行ない、所定の選別を行な
うことができ、選別したウェハを用いることで半導体デ
バイスの生産効率を上ることができる。
In the above embodiment of the evaluation of a semiconductor substrate for measuring the attenuation coefficient k of ellipsometry according to the present invention, a GaAs substrate was explained.
It is not limited to As substrates, but semiconductors such as Si and InP can also be evaluated in the same way, and each substrate can be evaluated non-destructively, and predetermined selection can be performed, and the selected wafers can be By using it, it is possible to increase the production efficiency of semiconductor devices.

〈発明の効果〉 本発明によるエリプソメトリによる半導体基板の評価法
によシ、m工前のウェハを非破壊で検査して、その半導
体基板の加工損傷や自然酸化膜等のウニ八表面に関する
情報を減衰係数にとして得ることができ、こ(Z)kか
ら、ウェハでデバイスを作製したときの特性値のばらつ
きを推定することが可能になった。従って、工程前に作
製するデバイスに適したウェハを選別することが可能に
なフ。
<Effects of the Invention> According to the evaluation method of semiconductor substrates using ellipsometry according to the present invention, wafers before processing can be non-destructively inspected, and information regarding processing damage and surface defects such as natural oxide films on the semiconductor substrates can be obtained. can be obtained as an attenuation coefficient, and from this (Z)k, it has become possible to estimate variations in characteristic values when devices are manufactured using wafers. Therefore, it is possible to select a wafer suitable for the device to be manufactured before the process.

半導体デバイス作製の生産性を向上させることができる
Productivity in manufacturing semiconductor devices can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、各種の表面加工ウェハに対する本発明のに分
布を示す図、第2図は本発明とPBS法の測定値の比較
図、第3図は実施例の各種ウニ/1で(Dk(0分布を
示す図、第4図は塩酸処理後のに値の経時変化を示す図
、第5図は実施例0FETの構成図、第6図はkとσV
thの関係を示す図、第7図kに対するnとσnの関連
を示す図、第8図はkとφb及びσφbの関連を示す図
である。
FIG. 1 is a diagram showing the distribution of Dk of the present invention for various surface-treated wafers, FIG. 2 is a diagram comparing the measured values of the present invention and the PBS method, and FIG. (Figure 4 shows the time-dependent change in value after hydrochloric acid treatment, Figure 5 shows the configuration of Example 0 FET, Figure 6 shows k and σV
FIG. 7 is a diagram showing the relationship between n and σn with respect to k, and FIG. 8 is a diagram showing the relationship between k, φb, and σφb.

Claims (1)

【特許請求の範囲】[Claims] 1.エリプソメトリによる半導体基板表面での減衰係数
、又は、減衰係数の分布状況の測定から、前記半導体基
板表面に於ける加工損傷や酸化等の状態を推定して、選
別することを特徴とする半導体基板の評価方法。
1. A semiconductor substrate characterized in that the state of processing damage, oxidation, etc. on the semiconductor substrate surface is estimated and selected from the measurement of the attenuation coefficient or the distribution of the attenuation coefficient on the semiconductor substrate surface by ellipsometry. evaluation method.
JP5596890A 1990-03-07 1990-03-07 Evaluation of semiconductor substrate Pending JPH03257843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5596890A JPH03257843A (en) 1990-03-07 1990-03-07 Evaluation of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5596890A JPH03257843A (en) 1990-03-07 1990-03-07 Evaluation of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPH03257843A true JPH03257843A (en) 1991-11-18

Family

ID=13013871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5596890A Pending JPH03257843A (en) 1990-03-07 1990-03-07 Evaluation of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPH03257843A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010249833A (en) * 1998-04-30 2010-11-04 Kla-Tencor Corp System and method for inspecting semiconductor wafers

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01158735A (en) * 1987-12-16 1989-06-21 Nec Corp Processing of semiconductor crystal surface

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01158735A (en) * 1987-12-16 1989-06-21 Nec Corp Processing of semiconductor crystal surface

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010249833A (en) * 1998-04-30 2010-11-04 Kla-Tencor Corp System and method for inspecting semiconductor wafers

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