JPH03248256A - Inter-system data transfer method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] This invention aims to speed up data transfer with respect to an inter-system data transfer method used when transferring data between two systems using a handshake method using lookout. , a data register means and a status register, and in inter-system data transfer for transferring data from one system to a second system, the data to be transferred is coded data set in advance, and the status is data holding means for holding data written in the data register means using data that is not coded data and also using a data read signal from the second system; and a selection control signal to be inputted. a selection means for selecting either the data holding means or the status register according to the state; and a selection means for selecting either the data holding means or the status register at all times; and a selection control means for sending a selection control signal for selecting the data holding means when a read signal is input from the second system, and the second system selects the data holding means using the data read signal. The held data or the status stored in the status register is read out, but of the read data, only the encoded data is taken in and the data is transferred from the first system to the second system. Configure.

[Industrial application field]

The present invention uses a handshake method using lookout.
This relates to a data transfer method used when transferring data between two systems.

In general, with asynchronous timing, system A and system B
When transferring data between the two, handshaking is performed using interrupts and lookout (monitoring whether the data to be transferred has been written to the data register). However, if the scale of the system is large and the number of interrupt levels is insufficient, the latter method is used to perform handshaking.

Note that the state of the data register can be determined by looking at the state of the status bits stored in the status register.

Now, the reason for monitoring the status of the status bits mentioned above is to prevent overrun or underrun errors of transferred data, but it is also possible to monitor the status of the status bits without using interrupts. To do this, read the status data every time one data is read from the data register
The state of the bit must be read repeatedly.

For this reason, the above-mentioned status monitoring of the status bit becomes an extra process when continuous data is written from the sending side. It becomes difficult to increase the speed.

Therefore, it is necessary to increase the speed of data transfer.

[Conventional technology]

FIG. 5 is a block diagram of a conventional example, and FIG. 6 is an explanatory diagram of the number of steps in the external memory access process of FIG.

The operation of FIG. 5 will be described below with reference to FIG. 6 assuming that data is transferred using a handshake method using lookout. Note that the status register 15 stores a bit indicating whether data to be transferred has been written in the data register 13.23.

(1) Data transfer from system 8 to system B First, computer (hereinafter abbreviated as CPU) 11 read the status of the bits in the status register and found that there was no write data in data register 13. Therefore, the data in the memory 12 is written to the data register 13. As a result, the bit in the data register 13 is set to the state of "1 with write data."

Furthermore, if the state of the bit is “write data available”,
CPt111 performs another process (see Figure 6-○~■)
.

Next, when the CPU 21 reads the state of the bit in the status register I5 in the same way as the CPU 11, it shows "write data available", so the gate 24 is turned on and the data is written to the data register 13. The written data is written to the memory 22, thereby changing the state of the bit in the status register 13 to 1 "No write data."

Thereafter, data is transferred from system A to system B by repeating this process.

(2) Data transfer from system B to system^ is performed using the same procedure as in (1) above, but at this time the data
Register 23. Data in memory 22 is transferred to memory 12 using buffer 14 .

[Problem to be solved by the invention]

As mentioned above, before writing data to or reading data from the data register, the CPU 11.21 always reads the state of the bit in the status register and writes data to the data register. , or it is necessary to recognize whether reading is possible or not.

For this reason, at least three steps are required before data is written into the memory 12 or 22. This includes three steps: reading the status bit from the status register in FIG. 6, reading the data written from the data register, and writing the read data to the memory.

Note that one machine cycle when the CPU accesses the external memory is one step.

Here, if there is a difference of one step, the slower the CPU accesses the memory, the larger the amount of data to be transferred, the more
There is a problem in that it becomes difficult to increase the speed of data transfer.

An object of the present invention is to speed up data transfer.

[Means to solve problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 3 is a data register means into which data to be transferred is written and read, and 6 is a status register in which a status indicating whether or not data to be transferred has been written to the data register means is stored. It is.

Further, 4 is a data holding means for holding data written in the data register means using a data read signal from the second system, and 5 is a data holding means for holding data written in the data register means using a data read signal from the second system. Data retention means and status
This is selection means for selecting one of the registers.

Further, 7 selects the status register at all times, but selects the data holding means when the status of the status register is write and a read signal is input from the second system. It is a selection control means that sends out a control signal.

Further, preset coded data is used as the data to be transferred, and data other than the coded data is used in the state.

Then, the second system uses the data read signal to read the data held in the data holding means or the status stored in the status register, but captures only the coded data from the read data. Data is transferred from the first system to the second system.

[Effect]

The present invention uses preset coded data as the data to be transferred, uses non-coded data as the status, and provides data holding means, selection means, and selection control means.

First, when transferring data from the first system to the second system, when the first system writes the data to be transferred to the data register means using the data write signal, the written data is stored in the data holding state. and is maintained using the data read signal from the second system.

Note that information indicating that data to be transferred has been written from this data register means is stored in the status register.

Further, the selection control means sends a selection control signal to the selection means to normally select the status register. However, the state of the bit in the status register (hereinafter,
When the status (referred to as status) is "Write data available" and a data read signal from the second system is input, the data holding means is selected.

On the other hand, the second system uses the data read signal to retrieve the data held in the data holding means or the status of the status register without monitoring the status of the status register, but the retrieved data Of these, data is transferred from the first system to the second system by capturing only the coded data.

That is, since the selection means automatically selects the data holding means and the status register in response to the selection control signal from the selection control means, from the perspective of the second system, data can be read from one register. It looks like there is.

This replaces the conventional status register and data register.
Two processing steps for register reading can be reduced to one processing step, and data transfer speed can be increased.

〔Example〕

2 is a block diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of the operation of FIG. 2, and FIG. 4 is an explanatory diagram of the number of steps in the external memory access process of FIG. 2.

Note that the symbols on the left side of FIG. 3 indicate the waveforms of the portions with the same symbols in FIG.

Here, data register 31, state generation circuit 32, A
ND gate 33 is a component of data register means 3;
The latch circuit 41 is a component of the data holding means 4, and the selection circuit 51. The gate circuit 52 is a component of the selection means 5, and the selection control section 71 is a component of the selection control means 7. Also,
System^ and System B correspond to the first system and second system in the claims.

In the following, data will be transferred from system A to system B using data stipulated in the JIS code and status not stipulated in the JIS code, with reference to Figs. 3 and 4. The operation shown in FIG. 2 will be explained.

Incidentally, in FIG. 2, parts other than those necessary for explaining the above-mentioned operation are omitted.

First, the CPU 11 applies a data write signal to the data register 31 and the status generation circuit 32, writes the data to be transferred to the data register 31, and confirms that the data has been stored in the data register from the status generation circuit 32. The status register 6 is caused to send out information indicating the status. Therefore, the status of the status register 6 becomes "write data available". (See Figure 3 - ■, ■ left side).

Note that the data written in the data register 31 passes through the latch circuit 41 and appears at the input side of the selection circuit 51, but if it is not latched and another data is input to the latch circuit, this other data will be updated.

However, when a data read signal from system B is input to this latch circuit 41 via the selection control section 71, the data in the latch circuit is latched and fixed at the falling point of this signal (Fig. (Refer to the latch part in ■).

In addition, the selection circuit 5I performs a selection operation in response to the state of the selection control signal from the selection control section 71, but normally selects the status register side and leaves the data written in the data register 3. In addition, the latch circuit side is selected only during the period in which the data read signal from system B is valid (L level period) (see FIG. 3--) and (-).

Now, since the gate circuit 52 is in an on state while the data read signal from system B is valid, the data to be transferred from system A is transferred to system B while the selection circuit selects the latch circuit side. The data are taken out onto the data bus (see the portions D+ and Dz in Figure 3-2).

At this time, the AND gate 33 receives a selection control signal from the selection control section 71 (selection control signal for selecting the latch circuit side).
and the data read signal from system B are input,
A reset signal is sent to the state generation circuit 32 from this gate.

Therefore, information indicating that the data register is empty is sent from the status generating circuit to the status register 6.
The status of the status register becomes “no data written”. Further, the selection control section 71 sends out a selection control signal to cause the selection circuit 51 to select the status register side.

Next, when a data read signal from system B is input while data is not being written to the data register 31 (see part a of Figure 3-■), the selection circuit 51 selects the status register side. Therefore, the contents of the status register 6, ie, the status of "no write data" is read out (see FIG. 3--).

That is, as shown in FIG. 4, system B reads data from the data register or status register automatically selected by the selection circuit 51 via the gate circuit. Then, after recognizing the read data,
The CPU determines whether the read data is status or data.
21 makes a judgment, and if it is a status, the process moves to other processing or register reading.

However, if it is data, after writing it to the corresponding memory (not shown), the process moves to reading from the register (see FIG. 4--).

The number of steps for accessing external memory at this time is 4th.
The number of steps shown in FIG.

The above explanation is for data transfer from system A to system B, but in the case of data transfer from system B to system A, the transfer operation can be performed by setting the left side of Figure 2 to system B and the right side to system A. is exactly the same as above.

〔Effect of the invention〕

As described above in detail, the present invention has the effect of increasing the speed of data transfer.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, and Fig. 4 is an access process to the external memory of Fig. 2. FIG. 5 is a block diagram of a conventional example; FIG. 6 is a diagram illustrating the number of steps in the external memory access process in FIG. 5. In the figure, 3 is a data register means, 4 is a data holding means, 5 is a selection means, 6 is a status register, and 7 is a selection control means. , Non, I C Sun Moon n Hara Kori Fukuchi Soft Whistle Diagram ○ ■ ■ ■ ■ ■ Fig.

Claims (1)

[Claims] The data to be transferred is written and the data to be read.
a register means (3) and a status register (6) in which a status indicating whether data to be transferred has been written to the data register means is stored; In an inter-system data transfer method for transferring data to a system, preset coded data is used as the data to be transferred, data other than the coded data is used for the status, and data is read from the second system. data holding means (4) for holding data written in the data register means using signals; and either the data holding means or the status register depending on the state of the input selection control signal. a selection means (5) for selecting the status register at all times; however, when the status of the status register is in a writing state and a read signal is input from the second system, the data is selected; a selection control means (7) for transmitting a selection control signal for selecting the holding means, and the second system uses the data read signal to read the data held in the data holding means or the status information.
Inter-system data characterized in that a status stored in a register is read out, and of the read data, only the encoded data is taken in and the data is transferred from the first system to the second system. Transfer method.