JPH03246973A - Thin film transistor and its manufacture - Google Patents
Thin film transistor and its manufactureInfo
- Publication number
- JPH03246973A JPH03246973A JP4402090A JP4402090A JPH03246973A JP H03246973 A JPH03246973 A JP H03246973A JP 4402090 A JP4402090 A JP 4402090A JP 4402090 A JP4402090 A JP 4402090A JP H03246973 A JPH03246973 A JP H03246973A
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- semiconductor film
- thin film
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000010408 film Substances 0.000 claims abstract description 55
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 230000007935 neutral effect Effects 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 15
- 239000001301 oxygen Substances 0.000 claims description 15
- 229910052760 oxygen Inorganic materials 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 2
- 229910052799 carbon Inorganic materials 0.000 claims 2
- 239000010453 quartz Substances 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 241000257465 Echinoidea Species 0.000 description 1
- 206010021143 Hypoxia Diseases 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004868 gas analysis Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000001146 hypoxic effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、薄膜トランジスタおよびその製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a thin film transistor and a method for manufacturing the same.
（従来の技術）
多結晶シリコンを使用した薄膜トランジスタの開発か盛
んに行なわれ、これを応用したイメーンセンサ（特開昭
６０−２２８８１号公報）、感熱へ・ソト（特開昭８２
−１８１４７３号公報）、液晶デイスプレィ等、様々な
製品か生み出されている。(Prior art) Thin film transistors using polycrystalline silicon have been actively developed, and image sensors using this (Japanese Patent Application Laid-Open No. 60-22881), heat-sensitive transistors (Japanese Patent Application Laid-Open No. 1982)
-181473), liquid crystal displays, and various other products have been produced.
これらは、いずれも絶縁基板上に多結晶シリコンを用い
て薄膜トランジスタを形成し、駆動回路もしくはスイッ
チング素子を構成している。In each of these, a thin film transistor is formed using polycrystalline silicon on an insulating substrate, and a drive circuit or a switching element is configured.
多結晶シリコンは薄膜トランジスタの活性層として使用
され、次のような方法で基板上に形成されている。Polycrystalline silicon is used as the active layer of thin film transistors and is formed on a substrate in the following manner.
■低温で非晶質シリコンを成膜しその後熱処理をほどこ
し、結晶粒径を成長させ移動度等を向上させる。■Amorphous silicon is deposited at low temperatures and then heat treated to grow crystal grain size and improve mobility.
■多結晶シリコンを成膜しその後シリコンイオンインプ
ランテーションでアモルファス化し、その後熱処理を施
して結晶粒径を成長させ、移動度等を向上させる。■ Polycrystalline silicon is formed into a film, then made amorphous by silicon ion implantation, and then heat treated to grow the crystal grain size and improve mobility, etc.
また、多結晶シリコンの結晶粒の界面等に存在すると考
えられる未結合手の影響を軽減させるために、成膜後の
シリコン膜もしくは、上記■、■の技術を適用した膜に
、さらに水素プラズマアニールなとて水素を混入させ、
シリコンの未結合手と水素とを結合させて電気的に安定
させることか行われている。In addition, in order to reduce the effects of dangling bonds that are thought to exist at the interfaces of crystal grains of polycrystalline silicon, hydrogen plasma is applied to the silicon film after it has been formed or to the film to which the techniques ① and ③ above have been applied. Annealed and mixed with hydrogen,
Efforts have been made to bond silicon's dangling bonds with hydrogen to stabilize it electrically.
（発明か解決しようとする課題）
ところで、さらに高品質を目指してよりトランジスタ特
性を向上させるには、多結晶シリコンの結晶粒径サイズ
や界面の状態を改善してもあるところで限界か生じ、特
性を向上させることか難しくなっている。(Problem to be solved by invention) By the way, in order to further improve transistor characteristics with the aim of achieving even higher quality, even if the crystal grain size and interface conditions of polycrystalline silicon are improved, there will be a limit at some point, and the characteristics will have to be improved. It is becoming difficult to improve.
すなわち、電子の移動度がある値に達すると、測定温度
を徐々に変化させても移動度の値はほとんど温度に影響
されず、一定値のまま向上しないのである。In other words, once the electron mobility reaches a certain value, even if the measurement temperature is gradually changed, the mobility value is almost unaffected by the temperature and remains at a constant value and does not improve.
これは、多結晶シリコンに含まれる電気的中性不純物の
酸素か影響していると考えられる。この電気的中性不純
物である酸素は、多結晶中に１０１９／ｃＩＩ１３程度
混入しており、主にシリコンの成膜時、すなわち、化学
気相蒸着を行う際に混入すると考えられる。This is thought to be caused by oxygen, an electrically neutral impurity contained in polycrystalline silicon. Oxygen, which is an electrically neutral impurity, is mixed into the polycrystal at a rate of about 1019/cII13, and is thought to be mixed mainly during silicon film formation, that is, when chemical vapor deposition is performed.
化学気相蒸着は、通常、横型の減圧化学気相蒸着装置を
使用しているのであるが、この装置では炉に取りつけで
あるふたを開けた時点から、炉内に空気の進入が始まり
、ウニ／＼−の挿入、取り出しは、空気か混入した状態
で行なわれることになる。また、混入した空気を取り除
く技術も確立されていない。Chemical vapor deposition usually uses a horizontal reduced-pressure chemical vapor deposition device, but with this device, air begins to enter the furnace from the moment the lid attached to the furnace is opened, and the sea urchin Insertion and removal of /\- will be performed with air mixed in. Furthermore, no technology has been established to remove the mixed air.
そして、これらは、半導体膜成膜炉のふたの取りつけ部
か高真空排気に耐え得る構造になっていないという装置
的な要因が絡んでいる。These problems are related to equipment factors such as the attachment of the lid of the semiconductor film deposition furnace not having a structure that can withstand high vacuum exhaust.
本発明はこのような課題を解決するためになされたもの
で、より高い移動度を実現させる薄膜トランジスタと、
その製造方法を提供することを目的とする。The present invention was made to solve these problems, and includes a thin film transistor that achieves higher mobility,
The purpose is to provide a manufacturing method thereof.
［発明の構成］
（課題を解決するための手段）
本発明の薄膜トランジスタは、絶縁基体と、この絶縁基
体上に形成された半導体膜からなるチャネル部およびソ
ース・トレイン部と、前記半導体膜にゲート絶縁膜を介
して形成されたゲート配線とを有する薄膜トランジスタ
ーにおいて、前記チャネル部を構成する半導体膜か含有
する電気的中性不純物の濃度が、１０１８／Ｃ１１３以
下であることを特徴としている。[Structure of the Invention] (Means for Solving the Problems) A thin film transistor of the present invention includes an insulating base, a channel part and a source/train part made of a semiconductor film formed on the insulating base, and a gate formed on the semiconductor film. A thin film transistor having a gate wiring formed through an insulating film is characterized in that the concentration of an electrically neutral impurity contained in the semiconductor film constituting the channel portion is 1018/C113 or less.
また、本発明の薄膜トランジスタの製造方法は、半導体
膜を形成するための成膜用容器内部の全圧力月０−−５
ｔｏｒｒ以下になるまで排気し、排気後に絶縁基体上に
半導体膜を形成する工程と、前記半導体膜にゲート絶縁
膜を形成する工程と、前記ゲート絶縁膜上にゲート電極
を形成する工程と、前記半導体膜を、電気的不純物濃度
が１０１８／Ｃｌｌ１３以下であるチャネル部と、電気
的中性不純物を高濃度で含有するｒノース・ドレイン部
とに分離する工程と、前記絶縁基体上に絶縁層を形成す
る工程と、前記絶縁層上に配線層を形成する工程とを有
することを特徴としている。Further, in the method for manufacturing a thin film transistor of the present invention, the total pressure inside a film forming container for forming a semiconductor film is 0 to 5 months.
torr or less, forming a semiconductor film on an insulating substrate after evacuation, forming a gate insulating film on the semiconductor film, forming a gate electrode on the gate insulating film, and A step of separating the semiconductor film into a channel part having an electrical impurity concentration of 1018/Cll13 or less and an r north/drain part containing a high concentration of electrically neutral impurities, and forming an insulating layer on the insulating substrate. and forming a wiring layer on the insulating layer.
本発明において、多結晶シリコン膜はたとえばＬＸ １
０−’ ｔｏｒｒ未満に排気された装置内で成膜する
。このとき、残留ガスは空気であると考えると酸素の割
合は、３０％程度であるため酸素分圧は０．３ Ｘ １
０−’ ｔｏｒｒである。In the present invention, the polycrystalline silicon film is, for example, LX 1
The film is formed in an apparatus evacuated to less than 0-' torr. At this time, assuming that the residual gas is air, the proportion of oxygen is about 30%, so the oxygen partial pressure is 0.3 x 1
0-'torr.
この後、反応ガスを導入し成膜圧力を０．４ｔｏｒｒ程
度にもどす。このとき、酸素分圧は最大０．７５Ｘ１０
−’ ｔｏｒｒ（−０，３Ｘ １０−’ ） １０．
４）程度となる。Thereafter, a reaction gas is introduced to return the film forming pressure to approximately 0.4 torr. At this time, the oxygen partial pressure is maximum 0.75X10
-'torr(-0,3X10-') 10.
4) Approximately.
このような酸素分圧の条件において、装置内に含まれる
酸素のモル数ｎを気体の状態方程式に従って求めると、
ｎ −Ｐ Ｖ ／ ＲＴ
＝ （０，７５Ｘ １０−’ Ｘ １３３ Ｘ １．
３ Ｘ １Ｏ−２）８．３Ｘ （２７３＋６００）
−１，８Ｘ１０−８ ｓｏｌ
となる。Under such oxygen partial pressure conditions, when the number n of moles of oxygen contained in the device is determined according to the gas equation of state, n - P V / RT = (0,75X 10-' X 133 X 1.
3X1O-2)8.3X (273+600)-1,8X10-8 sol.
これがすべて反応生成物に取り込まれたとすると、その
濃度Ｃ８は、
Ｃ＝ｌＸ １０１６／ Ｃｍ” −（６Ｘ １０２３Ｘ
１．８ Ｘ １Ｏ−８）となる。Assuming that all this is incorporated into the reaction product, its concentration C8 is: C=lX 1016/ Cm" - (6
1.8 x 1O-8).
実際問題では、残留ガスが気体の状態方程式からはずれ
ることと、５ｉ−８ｉ結合よりも５ｔ−０結合の方か安
定であることから反応し易いため、実際の反応生成物中
・の酸素濃度は、はぼ１０１８／ｃｍ’程度となる。In actual problems, the residual gas deviates from the gas equation of state, and the 5t-0 bond is more stable than the 5i-8i bond, so it is easier to react, so the actual oxygen concentration in the reaction product is , is about 1018/cm'.
すなわちこのことから、成膜を行う装置内部の全圧を前
もって１０−’ ｔｏｒｒ以下に排気することにより
、成膜される膜の電気的中性不純物濃度は、１０１８／
ｃｍ３以下となり、薄膜トランジスタの移動度向上が可
能となる。That is, from this, by exhausting the total pressure inside the film forming apparatus to 10-' torr or less in advance, the electrically neutral impurity concentration of the film to be formed can be reduced to 1018/
cm3 or less, making it possible to improve the mobility of thin film transistors.
（作 用）
移動度の向上を妨げる原因としては、様々な要因が考え
られるが、本発明者らは多結晶シリコン中に含まれる電
気的中性不純物である酸素に着目した。(Function) Various factors can be considered to impede improvement in mobility, but the present inventors focused on oxygen, which is an electrically neutral impurity contained in polycrystalline silicon.
第４図は、多結晶シリコン中に含まれる酸素量を変え、
温度と移動度との関係を調べた結果である。Ｘ印は酸素
混入サンプルの結果であり、○印は低酸素サンプルの結
果を示している。Figure 4 shows that by changing the amount of oxygen contained in polycrystalline silicon,
This is the result of investigating the relationship between temperature and mobility. The X mark indicates the result of the oxygen-containing sample, and the O mark indicates the result of the hypoxic sample.
第４図から明らかなように、酸素含有量の多い多結晶シ
リコンは移動度の値が横這い状態で、向上が見られない
。As is clear from FIG. 4, the mobility value of polycrystalline silicon with a high oxygen content remains unchanged and no improvement is observed.
さらに、第３図に示した理論的な計算結果からも、電気
的中性不純物濃度が１０１８／ｃＩ０１を超えて混入す
ると移動度に影響か現れはじめることかわかる。Furthermore, from the theoretical calculation results shown in FIG. 3, it can be seen that when the electrically neutral impurity concentration exceeds 1018/cI01, the mobility begins to be affected.
本発明では、シリコンの薄膜形成時の雰囲気を所定の状
態にコントロールして、多結晶シリコンの含有する電気
的中性不純物濃度を１０１８／ｃｍ”以下としているた
め、移動度向上の範囲を拡大し、より高品質化を図るこ
とができる。In the present invention, the atmosphere during the formation of a silicon thin film is controlled to a predetermined state, and the concentration of electrically neutral impurities contained in polycrystalline silicon is kept below 1018/cm'', thereby expanding the range of mobility improvement. , higher quality can be achieved.
（実施例） 次に、本発明の実施例について図面を用いて説明する。(Example) Next, embodiments of the present invention will be described using the drawings.
第１図は、本発明の一実施例である薄膜トランジスタを
示す図である。FIG. 1 is a diagram showing a thin film transistor that is an embodiment of the present invention.
同図において、石英基板１上には多結晶シリコンによる
半導体膜２が、化学気相エツチング法（ＣＤＥ）等によ
って島状に２０００人の厚さで形成され、チャネル部を
構成している。In the figure, a semiconductor film 2 made of polycrystalline silicon is formed on a quartz substrate 1 in an island shape with a thickness of 2000 nm by chemical vapor phase etching (CDE) or the like, and forms a channel portion.
このチャネル部となる多結晶シリコンの電気的中性不純
物濃度は１０１８／ｃｍ１以下とされている。The electrically neutral impurity concentration of the polycrystalline silicon forming the channel portion is set to be 10 18 /cm 1 or less.
半導体膜２上には、塩酸酸化法等でゲート酸化膜３が数
１００人の厚さで形成され、さらに、ゲート電極用配線
が減圧化学気相蒸着法（ＬＰ−ＣＶＤ）等で形成され、
その後、反応性イオンエツチング法（ＲＩＥ）等でパタ
ーニングすることにより、ゲート電極４が形成されてい
る。A gate oxide film 3 is formed on the semiconductor film 2 to a thickness of several hundred layers using a hydrochloric acid oxidation method or the like, and further, a wiring for a gate electrode is formed using a low pressure chemical vapor deposition method (LP-CVD) or the like.
Thereafter, gate electrode 4 is formed by patterning using reactive ion etching (RIE) or the like.
半導体膜２の周囲には、イオン打ち込みによってソース
・ドレイン部５か形成されている。A source/drain portion 5 is formed around the semiconductor film 2 by ion implantation.
さらに、ソース・ドレイン部５の周囲の石英基板１上に
は、常圧化学気相蒸着法等により、層間絶縁膜６が形成
されており、ＲＩＥて形成された所定のコンタクトホー
ル７の部分に、アルミニウムまたはアルミニウム合金等
で配線層８が形成されている。Further, an interlayer insulating film 6 is formed on the quartz substrate 1 around the source/drain part 5 by atmospheric pressure chemical vapor deposition or the like, and is formed in a predetermined contact hole 7 formed by RIE. The wiring layer 8 is formed of aluminum, aluminum alloy, or the like.
このような薄膜トランジスタにおける半導体膜は、たと
えば第２図に示す縦型の減圧ＣＶＤ装置を用いて形成す
ることができる。The semiconductor film in such a thin film transistor can be formed using, for example, a vertical low pressure CVD apparatus shown in FIG.
第２図において、縦型の減圧ＣＶＤ装置２０には、底板
２１に高真空排気用のターボポンプ２２と、残留ガスの
分析を行なうためのモニター２３とが連結されている。In FIG. 2, a vertical reduced pressure CVD apparatus 20 has a bottom plate 21 connected to a turbo pump 22 for high vacuum evacuation and a monitor 23 for analyzing residual gas.
また、底板２１とペルジャー２４とは、２重のＯリング
２５でシールされ、１０−’ ｔｏｒｒ以下でも充分
に気密か保たれるようになっている。Further, the bottom plate 21 and the Pelger 24 are sealed with a double O-ring 25 to maintain sufficient airtightness even at 10-' torr or less.
この減圧ＣＶＤ装置２０を使用する場合は、ますはじめ
に装置内を加熱、排気する。そして、ウェハーを投入し
、さらに加熱して高真空排気を行い、装置内を１０−’
ｔｏｒｒ以下に設定する。When using this reduced pressure CVD apparatus 20, the inside of the apparatus is first heated and evacuated. Then, the wafer is loaded, heated further, and evacuated to a high vacuum, and the inside of the device is heated for 10-'
Set to below torr.
次いで、モニター２３による残留ガス分析を行ない、酸
素、窒素等の分圧が所定の値（たとえば１Ｏ−５ｔｏｒ
ｒ以下）に達した時点で反応ガスを導入口２６より導入
して成膜を行なう。Next, a residual gas analysis is performed using the monitor 23, and the partial pressure of oxygen, nitrogen, etc. is determined to a predetermined value (for example, 1O-5tor
At the time when the temperature reaches (below r), the reaction gas is introduced from the inlet 26 to form a film.
このような条件下で成膜を行うことにより、生成される
多結晶シリコンの電気的中性不純物濃度は１０１８／ｃ
Ｉ１１３以下となり、移動度の向上が実現された。By forming the film under these conditions, the electrically neutral impurity concentration of the polycrystalline silicon produced is 1018/c.
It became I113 or less, and an improvement in mobility was realized.
［発明の効果］
以上説明したように、本発明によれば半導体膜成膜前に
、成膜容器内部を１０−’ ｔｏｒｒ以下の圧力まで排
気し、低い分圧条件で多結晶シリコンを成膜することに
より、生成される多結晶シリコン膜の電気的中性不純物
濃度を所定の濃度以下に抑え、薄膜トランジスタにおけ
る移動度の向上を図ることかできる。[Effects of the Invention] As explained above, according to the present invention, before forming a semiconductor film, the inside of the film forming container is evacuated to a pressure of 10-' torr or less, and polycrystalline silicon is formed under low partial pressure conditions. By doing so, it is possible to suppress the electrically neutral impurity concentration of the produced polycrystalline silicon film to a predetermined concentration or less, and to improve the mobility of the thin film transistor.
第１図は本発明による一実施例の薄膜トランジスタを示
す断面図、第２図は多結晶シリコンの成膜装置を説明す
るための概念図、第３図は多結晶シリコンの移動度と電
気的中性不純物濃度との関係を示す図、第４図は温度変
化に伴う移動度の変化を示す図である。
１・・・・・・石英基板、２・・・・・・半導体膜、３
・・・・・・ゲート酸化膜、４・・・・・・ゲート電極
、５・・・・・・ソース・ドレイン部、
６・・・・・・層間絶縁膜、７・・・・・・コンタクト
ホール、８・・・・・・配線層、
２０・・・・・・縦型減圧ＣＶＤ装置、２１・・・・・
・底板、２２・・・・ターボポンプ、２３・・・・・・
モニター ２４・・・・・ベルジャ２５・・・・・・０
リング、２６・・・・・・導入口。
第
四′１
η
第
２［４
０
１００
シＬ
度
００
（Ｋ）FIG. 1 is a cross-sectional view showing a thin film transistor according to an embodiment of the present invention, FIG. 2 is a conceptual diagram for explaining a polycrystalline silicon film forming apparatus, and FIG. 3 is a diagram showing the mobility and electrical balance of polycrystalline silicon. FIG. 4 is a diagram showing the relationship with the concentration of sexual impurities, and FIG. 4 is a diagram showing the change in mobility due to temperature change. 1...Quartz substrate, 2...Semiconductor film, 3
...Gate oxide film, 4...Gate electrode, 5...Source/drain part, 6...Interlayer insulating film, 7... Contact hole, 8... Wiring layer, 20... Vertical low pressure CVD device, 21...
・Bottom plate, 22...Turbo pump, 23...
Monitor 24...Belljar 25...0
Ring, 26... Inlet. 4th'1 η 2nd [4 0 100 shiL degrees 00 (K)
Claims (5)
膜からなるチャネル部およびソース・ドレイン部と、前
記半導体膜にゲート絶縁膜を介して形成されたゲート配
線とを有する薄膜トランジスターにおいて、 前記チャネル部を構成する半導体膜が含有する電気的中
性不純物の濃度が、１０＾１＾８／ｃｍ＾３以下である
ことを特徴とする薄膜トランジスタ。(1) A thin film transistor having an insulating base, a channel part and a source/drain part made of a semiconductor film formed on the insulating base, and a gate wiring formed on the semiconductor film via a gate insulating film, A thin film transistor, wherein a concentration of electrically neutral impurities contained in the semiconductor film constituting the channel portion is 10^1^8/cm^3 or less.
記載の薄膜トランジスタ。(2) Claim 1, wherein the semiconductor film is polycrystalline silicon.
The thin film transistor described.
の中の少なくとも１種である請求項１記載の薄膜トラン
ジスタ。(3) The thin film transistor according to claim 1, wherein the electrically neutral impurity is at least one of oxygen, carbon, and nitrogen.
が１０＾−＾４ｔｏｒｒ以下になるまで排気し、排気後
に絶縁基体上に半導体膜を形成する工程と、前記半導体
膜にゲート絶縁膜を形成する工程と、前記ゲート絶縁膜
上にゲート電極を形成する工程と、 前記半導体膜を、電気的中性不純物濃度が１０＾１＾８
／ｃｍ＾３以下であるチャネル部と、電気的不純物を高
濃度で含有するソース・ドレイン部とに分離する工程と
、 前記絶縁基体上に絶縁層を形成する工程と、前記絶縁層
上に配線層を形成する工程と を有することを特徴とする薄膜トランジスタの製造方法
。(4) Evacuating until the total pressure inside the film forming container for forming a semiconductor film becomes 10^-^4 torr or less, forming a semiconductor film on an insulating substrate after evacuation, and forming a gate on the semiconductor film. forming an insulating film; forming a gate electrode on the gate insulating film; and forming the semiconductor film with an electrically neutral impurity concentration of 10^1^8
/cm^3 or less into a channel part and a source/drain part containing a high concentration of electrical impurities; a step of forming an insulating layer on the insulating substrate; and a step of forming wiring on the insulating layer. 1. A method for manufacturing a thin film transistor, comprising the step of forming a layer.
の各分圧を１０＾−＾５ｔｏｒｒ未満とした後に、半導
体膜を形成することを特徴とする薄膜トランジスタの製
造方法。(5) A method for manufacturing a thin film transistor, characterized in that a semiconductor film is formed after each partial pressure of oxygen, carbon, and nitrogen in the film forming container is reduced to less than 10^-^5 torr.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4402090A JPH03246973A (en) | 1990-02-23 | 1990-02-23 | Thin film transistor and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4402090A JPH03246973A (en) | 1990-02-23 | 1990-02-23 | Thin film transistor and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03246973A true JPH03246973A (en) | 1991-11-05 |
Family
ID=12679985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4402090A Pending JPH03246973A (en) | 1990-02-23 | 1990-02-23 | Thin film transistor and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03246973A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271066B1 (en) | 1991-03-18 | 2001-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor material and method for forming the same and thin film transistor |
| US6562672B2 (en) | 1991-03-18 | 2003-05-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor material and method for forming the same and thin film transistor |
| US6613613B2 (en) | 1994-08-31 | 2003-09-02 | Semiconductor Energy Laboratory Co., Ltd. | Thin film type monolithic semiconductor device |
| US7067844B2 (en) | 1990-11-20 | 2006-06-27 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device |
| US7081938B1 (en) | 1993-12-03 | 2006-07-25 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
| US7098479B1 (en) | 1990-12-25 | 2006-08-29 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
| US7115902B1 (en) | 1990-11-20 | 2006-10-03 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
| US7576360B2 (en) | 1990-12-25 | 2009-08-18 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device which comprises thin film transistors and method for manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60245173A (en) * | 1984-05-18 | 1985-12-04 | Semiconductor Energy Lab Co Ltd | Insulated gate semiconductor device |
| JPH01321625A (en) * | 1988-06-23 | 1989-12-27 | Hitachi Ltd | Thin film formation and device therefor |
-
1990
- 1990-02-23 JP JP4402090A patent/JPH03246973A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60245173A (en) * | 1984-05-18 | 1985-12-04 | Semiconductor Energy Lab Co Ltd | Insulated gate semiconductor device |
| JPH01321625A (en) * | 1988-06-23 | 1989-12-27 | Hitachi Ltd | Thin film formation and device therefor |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7067844B2 (en) | 1990-11-20 | 2006-06-27 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device |
| US7115902B1 (en) | 1990-11-20 | 2006-10-03 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
| US7098479B1 (en) | 1990-12-25 | 2006-08-29 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
| US7576360B2 (en) | 1990-12-25 | 2009-08-18 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device which comprises thin film transistors and method for manufacturing the same |
| US6271066B1 (en) | 1991-03-18 | 2001-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor material and method for forming the same and thin film transistor |
| US6562672B2 (en) | 1991-03-18 | 2003-05-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor material and method for forming the same and thin film transistor |
| US7081938B1 (en) | 1993-12-03 | 2006-07-25 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
| US7564512B2 (en) | 1993-12-03 | 2009-07-21 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
| US6613613B2 (en) | 1994-08-31 | 2003-09-02 | Semiconductor Energy Laboratory Co., Ltd. | Thin film type monolithic semiconductor device |
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