JPH03245399A - Rom writer - Google Patents

Abstract

PURPOSE:To exert write upon a set of ROM groups by one time of operation from the outside by providing plural ROM sockets loading a master ROM and an unwritten ROM and exerting write upon the plural types of ROM by one process. CONSTITUTION:A control part 7 connects a comparator part 9 equipped with a function to pass data signals or to collate both data, and a ROM socket group 10 composed of ROM sockets 11-13 loading the plural host ROM and the unwritten ROM. Between the comparator part 9 and the ROM sockets 11-13, a ROM data bus select part 14 is provided with a function to select and switch a ROM data bus. Then, the data bus with the comparator part 9 is received by three bus select circuit SEL 19 and according to the designation of a bus select signal from the control part 7, one of the three bus select circuits is activated so as to exchange the data with the ROM mounted to the ROM socket. Thus, the write can be exerted upon a set of the ROM groups by one time of operation from the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a ROM writing device, and more particularly to a ROM writing device that reads or writes to a plurality of types of ROMs in one step and is equipped with parity check data generation means for data.

[Conventional technology]

A conventional ROM writing device, as shown in the block diagram of FIG.
System ROM that stores the control program for PU21
23, a RAM section 2 that temporarily stores data read from the parent ROM, a keyboard control section 25 for inputting control commands by the operator, a display control section 26 for displaying the results controlled by the CPU 21; controlled from parent R
A control unit 27 that outputs address signals and control signals to the OM and unwritten ROM and sends and receives data signals, and a comparator that is connected to the control unit 27 and has the function of passing the data signal or collating data on both sides. part 28, parent ROM and unwritten R
It has a ROM socket 29 in which an OM is mounted.

The operation of a conventional ROM writing device is to first load the parent ROM into the ROM socket 29, and then load it onto the keyboard controller 25.
The CPU 2 ] instructs the parent I' (OM data readout. The CPU 2 ] that receives the data readout instruction sends an address to the control I/roll unit 27 in accordance with the control program stored in the system ROM 23 . The data and the control signal are sent to the RAM'M section 24, and the address data is sent to the RAM section 24.The control section 27, which has received the address data and the control signal,
Send ROM address data and ROM control signals to two ROM sockets and read data from the parent ROM. The read data is input to the control section 27 via the comparator section 28. The control unit 27 that has received the data from the iROM sends the data from the parent ROM and the control signal to the RAM unit 2 to the controller 1. The R and AM section 24 receives the address data from the CPU 2 and the data from the parent ROM and the write control signal from the control section 27.
Accumulates data from the parent ROM to the specified address,
[CPU 2] is notified that the copy cycle of - times has been completed. Upon receiving this notification, the CPU 21 determines whether or not all copy cycles have been completed. If not, it continues the copy cycle, and if it has completed, it starts a verification operation. The CPU 21 that started the verification operation checks the RA,
The M section 24 and the control section 27 are each instructed to read data. RA receiving instructions to read data
M section 2 section upper 4 Sends the data accumulated so far to the comparator section 28 via the read control section 27.

The control unit 27 also instructs the ROM socket 29 to read data, and inputs the data read from the parent OM to the comparator unit 28.

The comparator unit 28 that has received the two pieces of data collates the data for each address and notifies the CPU 2 of the results. When the CPU 21 receives the comparison result, if the result does not match, it sends error information to the display control unit 26 and enters a command input waiting state. The display control unit 26 that has received the error information displays the read error. If the matching results match, the CPU 21 determines whether or not the matching operation for all data has been completed.If the matching operation has not been completed, the CPU 21 continues the matching operation, and if it has finished, the CPU 21 sends a message to the display control unit 26. It sends normal completion information to the host and enters a command input waiting state. The display control unit 26 displays normal completion and ends the series of data reading operations from the parent ROM.

The operation when the data read from the parent ROM cannot be used as is and is modified and used will be described.

First, from the keyboard control unit 25 to the CPU 21, R
Instructs to change the contents of the data accumulated on AM section 2 and 4.

Upon receiving this instruction, the CPU 21 transfers control over the R, AM section 24 to the keyboard control section 25. The keyboard control unit 25, which took over the control of the RAM unit 2 and 4,
The RAM section 2 sends out address data, write data, and a write control signal, and the RAM section 2 receives these signals and rewrites the data at the designated address. When the rewriting of the required portion of data is completed, the keyboard control section 25 sends a rewriting completion signal to the CPU 21. CP that received the rewriting completion signal
U21 enters a command input waiting state and uses a series of RAM
The operation of rewriting the contents of the data multiplied by part 2 and part 4 is completed.

Next, the case of writing to an unwritten ROM will be described.

First, remove the parent ROM from the ROM socket 29,
Install unwritten ROM. Next, the keyboard control section 2
5 instructs the CPU 21 to write into the ROM. R
Upon receiving the OM write instruction, the CPU 21 writes the R, AM section 2
The data stored in the controller 2 is read out and the data stored in the control unit 2 is read out.
Instruct 7 to send it. The data stored in the upper 4 addresses of the RAM section 2 is read out, and the control I/roll section 27
Send to. The control section 27 writes the received data via the comparator section 28 into unwritten ROMs mounted in two ROM sockets.

When the data writing is finished, the CPU 21 writes the unwritten RO
Similarly to the case where the data written to M was checked against RAM section 2, +t, A was read from M section 2/1 and the unwritten ROM mounted in the two ROM sockets. This is done by comparing the data using the comparator section 28. The comparator unit 28 that has received the two pieces of data collates the data for each address and sends the results to the CPU.
Notify 21. When the CPU 21 receives the comparison result, if the result does not match, it sends error information to the display control unit 26 and enters a command input waiting state. If the matching results match, the CPU 2 determines whether or not the matching operation for all data has been completed, and if it has not been completed, continues the matching operation, and if it has been completed, the CPU 2 It sends normal completion information to the server and waits for command input. The display control unit 26 displays normal completion and displays a series of unwritten ROMs.
Terminates the write operation for.

[Problem to be solved by the invention]

The conventional ROM writing device described above has only one ROM socket, and therefore can only write one ROM at a time. Therefore, when writing to a ROM group consisting of a ROM that stores even address data, an R, OM that stores odd address data, and a ROM that stores parity data, There is a problem in that the series of operations from reading from the parent ROM to completing writing to the unwritten ROM must be repeated three times. In addition, since the structure was always configured to correspond to one ROM, and there was no particular practice of generating and using parity check data, when it was necessary to divide and store it in multiple ROMs as mentioned above. However, there is also a problem in that the parity check data must be changed by a human outside.

An object of the present invention is to provide a set of RO
It is an object of the present invention to provide a ROM writing device that can write M groups in one external operation and can simultaneously generate parity check data and use it as new data.

[Means to solve the problem]

The I'(0M writing device of the present invention reads data from the fflROM that stores basic data, stores it in a temporary storage device, reads the data again from the parent ROM, and compares it with the data stored in the temporary storage device. In a ROM writing device that writes data stored in the temporary storage device to an unwritten ROM that has not yet been written to after writing, an R equipped with the parent ROM and the unwritten ROM is provided.
It has a configuration in which multiple OM sockets are provided and multiple types of ROM can be written in one process.

The ROM writing device of the present invention may include parity check data generation means for generating parity check data for data read from the parent ROM and data stored in the temporary storage device.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The CPUI is connected via an address data control bus 2 to a system RO, M3 that stores a program for controlling the CPUI, a RAM section 4 that temporarily stores data read from a parent ROM, and a control command that an operator a keyboard control section 5 for inputting information; a display control section 6 for displaying the results controlled by the CPU 1;
A control unit 7 that outputs address signals and control signals for the OM and unwritten ROM and sends and receives data signals, and a parity check data generation unit that is connected to the RAM unit 4 and generates parity check data for stored data under control from the CPU. It is connected to section 8. Furthermore, the control section 7 is composed of a comparator section 9 which has a function of passing a data signal or collating both data, and a ROM socket ~101], 12.13 in which a plurality of parent ROMs and unwritten ROMs are mounted. ROM7771 group 1
Connected to 0.

An OM data bus selection section 14 is provided between the comparator section 1 and the ROM sockets 11, 12, 1.3 in the ROM socket group 10, which has a function of selectively switching the ROM data bus.

Next, an explanation will be given of the operation when changing the conventionally used ROM data and writing it into a new ROM.

The ROM data will be explained as having 16 bits + 1 bit of parity.

First, a parent ROM for storing even address data is installed in ROM socket]1 of the ROM socket group 10, and the ROM
Parent RO to store odd address data in socket 12
A parent ROM for storing parity data is installed in the R, 0M socket 13. Next, the keyboard control unit 5 instructs the CPUI to read the stored contents from each set of ROMs mounted in the ROM sockets. The parent ROM was installed and received an instruction not to read the memory contents.
The PUI sends address data and a control signal to the control section 7, and address data to the RAM section 4 and parity check data generation section 8, according to a control program stored in the system ROM 3. Send. The control section 7 that has received the address data and control signal stores the received data and signal as ROM data bus selection information, and stores the received data and signal as ROM data bus selection information.
ROM address data and a ROM control signal are sent to the first group 10, a bus selection signal is sent to the ROM data bus selection section 4, and no data is read from each set of ROMs.

The read data is sent to the ROM data bus selection section upper 4.
The signal is input to the control section 7 via the comparator section 9. Control unit 7 that received data from the parent ROM
sends data from the fgIROM and a write control signal to the R, AM section 4, and sends data from the parent ROM to the parity check data generation section 8.

The RAM section 4 receives the address data from the CPUI and receives the data from the parent ROM and the write control signal from the control section 7, and transfers the data from the parent ROM to the specified address.
The parity check data generator 8 instructs the parity check data generation unit 8 to generate parity check data. C
The parity check data generation unit 8 receives the address data from the PU 1, the data from the parent ROM from the control unit 7, and the parity check data generation instruction from the R, AM unit 4, and generates parity check data and performs the parity check. The data is stored in the parity data RAM in the data generation unit 8, and at the same time, the CPU is notified that one copy cycle has been completed. Upon receiving this notification, C P LJ 1 determines whether or not all copy cycles have been completed. If not, it continues the copy cycle, and if it has completed, it starts a verification operation.

The CPUI that has started the verification operation instructs the RAM section 4, parity check data generation section 8, and control section 7 to read data, respectively.

The RAM section 4 and the parity check data generation section 8 that have received the data read instruction send out the data accumulated so far to the comparator section 9 via the read control section 7. In addition, the control section 7 includes a ROM 7771 group 10.
The data read from each set of ROMs is sent to the ROM data bus selection section 4 and inputted to the comparator section 9.

The comparator unit 9 that has received the two pieces of data compares the data for each address and notifies the CPU 1 of the results.

When the CPUI receives the comparison result, if the result does not match, it sends error information to the display control unit 6 and enters a command input waiting state.

The display control unit 6 that has received the error information displays the read error. If the matching results match, the CPU
determines whether or not the verification operation for all data has been completed, and if it has not been completed, continues the verification operation, and if it has been completed, sends normal completion information to the display control unit 6, and waits for command input. state.

The display control unit 26 displays normal completion and ends the series of data reading operations from the parent ROM.

Next, the operation f1 when the data read from the parent ROM cannot be used directly as write data but is modified and used will be explained in detail.

From the keyboard control unit 5 to CPIJ], R
A: Instructs to change the contents of data stored in the AM section 4.

Upon receiving this instruction, the C P LJ 1 issues control over the R, AM section 4 to the keyboard control section 5 . R,,
The keyboard control section 5, which has taken over control of the AM section 1, sends the RAM section 4 to the address -j-Kazuto!
z-inclusive data and write 1 to control l-o-small signal and 6: Send j, vari-i test data raw j& Address data is sent to unit 8. R and A who received these Shinkyu
After changing the data at the specified address to jl:, the M section 4 instructs the valid test data generating section 8 to generate parity test data.

1"?, A, M section 4 and keyboard control section 5 send various kinds of pariday inspection data (y;;;
The generation unit 8 generates validation check data, and J) changes the contents of the parity data RAM 2 in the parity check data generation unit 8. After completing the δ conversion of the data of the part required by the RA, M section 4 and the parity check data LL section 8, the keyboard control section 5 transfers the data to the CP (, J]
Sends a rewrite end signal to. Upon receiving the rewrite completion signal 9, the C P tJ 21 enters a command waiting state and completes a series of operations for rewriting the contents of the data stored in the RAM section 24.

FIG. 2 is a detailed block diagram of the RAM section 4 and the parity check data generation section 8.

The RAM section 4 has an internal RAM 15 and a ROM access controller 16.
6 sends out a pariday access signal. The parity check data generation unit 8 has a parity check data RAM 17 and a parity check data controller 1-roller 18, and has an RO
The parity access signal from the M access controller 16 is received by the parity check data controller 18.

FIG. 3 is a detailed block diagram of the R(,)M data bus selection section 14.

The data bus to and from the comparator section 9 is received by three bus selection circuits (hereinafter referred to as SEL) 19, and one of the three white circuits is activated according to the specification of the bus selection signal from the control section 7. and T1. F<, which is mounted on the OM socket, exchanges data with the OM.

Next, we will explain the case of writing to a ROM that has not yet been loaded with 1L1.
Remove the parent lZ OM and mount an unwritten ROM.

Next, the key fob control unit 5 sends the ROM to the CPU.
Instruct r'F÷include. CI) U1, which received the FZOM write instruction, reads out the data accumulated in the R, AM section 4 and the parity inspection data generation section 8, Send to section 7 i11, L
give instructions.

The R, A M section 4 and the L parity check data generation section 8 read out the data accumulated in the A1 to RES1:l+i and send it to the CON1 to CON17 unit 7. :1 nt l full part 7
The received (Jj) data is transferred to the comparator section 9 and the ROM.
The data is sequentially written into a plurality of wooden write ROMs mounted in the ROM socket I/group 10 through the data bus selector 14 and controlled by a bus selection signal. CP LJ], which has been writing data for half a winter, checks the RAM section 4 and the parity check data generation section 8 in the same way as when collating the data written to the last written ROM with respect to the RAM section 4 and the parity check data generation section 8. This is performed by comparing the parity check data generation section 8 with the data read from the unwritten ROM mounted in the ROM socket group 10 using the =1 comparator section 9 . The comparator unit 9 that has received the two pieces of data collates the data for each address and notifies the result to the CPU. Upon receiving the verification result, the CPUI sends error information to the display control unit 6 if the result is non-matching.
It enters the command waiting state. If the matching results match, the CPU determines whether the matching operation for all data has been completed, continues the matching operation if not completed, and sends a message to the display control unit 6 if the matching has been completed. It sends normal completion information to the computer and enters a command waiting state. The display control unit 6 displays normal completion and ends the series of write operations for the unwritten ROM.

〔Effect of the invention〕

As explained above, the present invention is equipped with a plurality of ROM sockets and a parity check data generation means, thereby making it possible to write data into one set of ROMs with a single external operation, and at the same time perform parity check data generation means. This has the advantage that inspection data can be generated and used as new data.

Data bus selection section, 15...Internal RAM, 16
...ROM access controller, 17...
...RA for parity check data, M, 18...
- Parity check data controller, 19...
- Bus selection circuit (SEL).

Claims (1)

[Claims] 1. Data is read from a parent ROM that stores basic data and stored in a temporary storage device, and data is read out from the parent ROM again and compared with the data stored in the temporary storage device. Unwritten RO that has not yet been written to
A ROM in which data stored in the temporary storage device is written to M.
The writing device includes a plurality of ROM sockets in which the parent ROM and the unwritten ROM are mounted, and writes a plurality of types of ROM in one process.
M writing device. 2. The ROM writing device according to claim 1, further comprising parity check data generation means for generating parity check data for data read from the parent ROM and data stored in the temporary storage device.