JPH0324058B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having an intrinsic gettering effect.

Process-induced defects and harmful impurities are major causes of defective characteristics of semiconductor devices. In order to eliminate these factors in the device operation region, crystal defects are intentionally generated inside the wafer, and a defect-free denuded zone (hereinafter abbreviated as DZ) is created near the wafer surface related to device operation. The IG method has been adopted in semiconductor devices to clean the device operating region by forming a region called a "DZ" and causing harmful impurities mixed in the DZ to getter into internal crystal defects.

As a method for forming the above-mentioned DZ and internal crystal defects, generally, prior to the semiconductor device manufacturing process,
Silicon wafers are often subjected to pre-heat treatment. An example of this heat treatment will be described with reference to patent applications filed by the present applicant, Japanese Patent Application No. 56-035023 (Japanese Patent Application Laid-open No. 57-167636) and Japanese Patent Application No. 56-035024 (Japanese Patent Application No. 57-167637).

This heat treatment method is the method described below [A] + [B]
Consisted of.

[A] Heat treatment is performed on the silicon wafer at a temperature of 950°C or higher for 10 minutes or more.

[B] After the heat treatment in [A] above, heat treatment is performed at least once at a temperature increase rate of 14° C./min or less. In addition,
In order to obtain a particularly thin DZ, it is desirable that at least the first heating rate is 5° C./min or less.

The first constant temperature heat treatment [A] of the heat treatment method is:
This eliminates crystal defect nuclei near the wafer surface and out-diffuses interstitial oxygen in the defects.

The second temperature-raising heat treatment [B] has the primary purpose of forming internal crystal defects, and its situation will be explained with reference to FIGS. 1a to 1c.

FIGS. 1a to 1c are diagrams showing changes in the size versus density distribution of internal crystal defects or defect nuclei due to the present heat treatment method. In the figure, the vertical axis shows the size of internal crystal defects or defect nuclei, the broken line shows the critical size that disappears at the temperature at which the temperature-raising heat treatment starts, and the broken line shows the internal crystal defects at the highest temperature used in the subsequent semiconductor device manufacturing process. Indicates the extinction critical size. Further, the horizontal axis indicates the density of internal crystal defects or defect nuclei.

FIG. 1a shows the wafer formation state before the start of the main heat treatment. In this state, internal crystal defects or defect nuclei of various sizes exist inside the wafer, and the larger the amount of interstitial oxygen, the larger the size and density of the defects are distributed. However, in silicon wafers produced by the usual CZ method (Czochralski method), all crystal defects are smaller than the broken line in size.

FIG. 1b shows the state after the temperature-raising heat treatment [B] has been performed once. In this state, most of the crystal defect nuclei grow into crystal defects, the distribution of crystal defect sizes moves upward in the figure, and some of them even reach the critical size shown by the broken line. On the other hand, some crystal defect nuclei smaller than the critical size for the heating start temperature shown by the broken line, which existed in the wafer formation state shown in FIG. 1a, disappear or dissolve into solid solution.

It is controlled by the interstitial oxygen concentration of internal crystal defects formed by this heating heat treatment and the heating rate.
That is, when the interstitial oxygen concentration is high or the temperature increase rate is low, the density of internal crystal defects becomes high.

On the other hand, regarding the width of the DZ, the temperature increase rate is low;
Alternatively, the width of the DZ becomes thinner when the maximum temperature increase is low.

In order to obtain the required internal crystal defect density and DZ width, it is necessary to select a combination of the above factors.

FIG. 1c shows the state after repeated implementation of the temperature increasing heat treatment [B]. In this state, all of the formed internal crystal defects exceed the defect extinction critical size at the maximum temperature used in the subsequent semiconductor device manufacturing process, which is shown by the broken line.

The second and subsequent temperature raising heat treatments [B] are for the purpose of growing the internal crystal defect size, and the DZ
The width of the DZ is determined by the first constant temperature heat treatment [A] and the first temperature raised heat treatment [B], and the second and subsequent temperature raised heat treatments [B] do not change the width of the already formed DZ. Implemented under certain conditions.

When internal crystal defects are formed as described above, interstitial oxygen within the silicon wafer moves and precipitates to the internal crystal defect portion, and the interstitial oxygen concentration decreases. Therefore, the initial value of the interstitial oxygen concentration (the value of the wafer formation state) is considered to be the concentration at the time when the state of growth of internal crystal defects due to the pre-heat treatment of the silicon wafer as in the above example or after the completion of the semiconductor device is considered as the initial value of the interstitial oxygen concentration (value of the wafer formation state). It becomes possible to express the difference between the two, that is, the amount of interstitial oxygen precipitated per unit volume.

In a semiconductor device manufacturing process in which a semiconductor device is formed on a silicon wafer in which DZ and internal crystal defects have been formed by the above-mentioned pre-wafer heat treatment, this wafer is usually further subjected to several high-temperature heat treatments.
These high-temperature heat treatments during the semiconductor device manufacturing process are
Similar to the preheat treatment described above, this has the effect of growing internal crystal defects. As a result, if internal crystal defects grow excessively, the wafer will warp and furthermore, dislocations called slip lines will occur.
These warps or sliplines impede the characteristics or lifespan of the semiconductor device. Conversely, when the growth of internal crystal defects is small, the gettering effect of harmful impurities is small.

Furthermore, in the actual manufacturing process of the semiconductor device, after the above-mentioned high-temperature heat treatment is completed, low-temperature heat treatment of about 450° C. is performed, such as heat treatment of the aluminum (Al) layer forming the electrode wiring pattern and heating in the assembly process after forming the chip. Although the effects of these low-temperature heat treatments on DZ and internal crystal defects can be ignored, these low-temperature heat treatments tend to convert interstitial oxygen into donors, increase the carrier concentration, and change the characteristics of the semiconductor device.

The present invention aims to provide a method for manufacturing a semiconductor device that has a good IG effect, does not cause warping or slip lines in a silicon wafer, and further suppresses changes in resistivity of the wafer due to donorization of interstitial oxygen. purpose.

Among the above-mentioned objects of the present invention, prevention of warpage or slip lines in silicon wafers (substrates) is a method for preventing silicon wafers (substrates) from being warped or slip-lined.
After heat treatment at a temperature of 950℃ or higher for 10 minutes or more
By performing heat treatment including a temperature raising step of 14°C/min or less once or more, the interstitial oxygen contained in the substrate is reduced to 0.1×10 ¹⁸ /cm ^-3 or more and 0.8×10 ¹⁸ /cm ^-3 or less. This is achieved by precipitating oxygen to form crystal defects inside the substrate and at the same time making the concentration of residual interstitial oxygen inside the substrate 0.7×10 ¹⁸ /cm ^-3 or more. In order to suppress changes in resistivity of the substrate due to donor formation, the concentration of interstitial oxygen in the substrate after the completion of the treatment is reduced to 1.2
This is achieved by setting it to less than ×10 ¹⁸ /cm ^-3 .

FIG. 2 is a chart showing the features of the present invention, in which the horizontal axis is the interstitial oxygen precipitation amount Δ[Oi], the vertical axis is the interstitial oxygen concentration [Oi] f after the completion of the high-temperature heat treatment, and the parallel The diagonal line corresponds to the initial value [Oi]o of the interstitial oxygen concentration, and the straight lines A, B, C, and D each indicate the limit value.

For a silicon wafer with an initial value of interstitial oxygen concentration [Oi]o, the interstitial oxygen precipitation amount Δ
The value of [Oi] and the interstitial oxygen concentration [Oi] f after completion of high-temperature heat treatment is determined by the intersection of the straight line representing [Oi]o in FIG. 2 with straight line A or straight line B and the straight line C or D. The object of the present invention is achieved when the amount of precipitated interstitial oxygen that forms the required internal crystal defects and size Δ[ Oi〕
Based on the above, select a silicon wafer that satisfies the above requirements, and calculate the amount of interstitial oxygen precipitated by subtracting the amount of interstitial oxygen precipitated during the semiconductor device manufacturing process from the reference value of the interstitial oxygen precipitated amount. There is a method of subjecting the silicon wafer to a heat treatment to form DZ and internal crystal defect nuclei or internal crystal defects.

Hereinafter, the process of completing the present invention will be explained, the structure and unique effects of the present invention will be clarified, and furthermore, the method of implementation will be described.

Figure 3 shows the amount of interstitial oxygen precipitation Δ[Oi] and the amount of wafer warpage from the untreated state to the completion of high-temperature heat treatment at 950°C or higher in the semiconductor device manufacturing process for silicon wafers manufactured by the CZ method. This is a chart showing the correlation between In the figure, the horizontal axis shows the amount of oxygen precipitated Δ[Oi], the vertical axis shows the amount of warpage of the wafer, and the solid line A and the circle mark in the figure indicate [Oi]o.
=1.7×10 ¹⁸ /cm ^-3 , broken line B and △ mark are [Oi] o =
The case of 1.5×10 ¹⁸ /cm ^-3 is shown.

As is clear from the figure, the amount of interstitial oxygen precipitation Δ
When [Oi] is small, 0.8×10 ¹⁸ /cm ^-3 or less, wafer warpage hardly occurs, and when this value is exceeded, wafer warpage increases rapidly and even creates a slip line. reach. Note that as the amount of precipitated interstitial oxygen decreases, the amount of crystal defects that cause the IG effect also decreases, so there is naturally a limit to reducing the amount of precipitated interstitial oxygen, and it is difficult to achieve a good IG effect. In order to obtain this, the amount of precipitated interstitial oxygen is preferably 0.1×10 ¹⁸ /cm ⁻³ or more.

When the initial value of interstitial oxygen concentration [Oi]o is small, the warpage of the wafer increases rapidly.The value of Δ[Oi] becomes small, and when [Oi]o is smaller than 1.5×10 ¹⁸ /cm ^-3 The limit is determined by the interstitial oxygen concentration [Oi]f after the completion of high temperature heat treatment, which will be described below.

FIG. 4 is a diagram showing the correlation between the interstitial oxygen concentration [Oi] f and the amount of wafer warpage after the completion of high-temperature heat treatment during the semiconductor device manufacturing process, and the horizontal axis is the interstitial oxygen concentration after the completion of the high-temperature heat treatment. Concentration [Oi] f,
The vertical axis indicates the amount of warpage of the wafer. In FIG. 3, the solid line A and the circle mark indicate the case where [Oi]o=1.5×10 ¹⁸ /cm ⁻³ , and the broken line B and the triangle symbol show the case where [Oi]o=1.3×10 ¹⁸ /cm ⁻³ .

As is clear from Figure 4, [Oi]o is 1.5×
The interstitial oxygen concentration [Oi] after completion of the above-mentioned high-temperature heat treatment for silicon wafers smaller than 10 ¹⁸ /cm ^-3
When f is less than 0.7×10 ¹⁸ /cm ^-3 , the warpage of the wafer increases rapidly and even leads to the formation of slip lines.

The upper limit of the interstitial oxygen precipitation amount Δ[Oi] and the interstitial oxygen concentration [Oi] after completion of high-temperature heat treatment explained above
The lower limit of f is to prevent the silicon wafer from warping or even forming a slip line due to excessive growth of internal crystal defects.

On the contrary, when the amount of precipitated interstitial oxygen Δ[Oi] is small, or the initial value of interstitial oxygen concentration [Oi]
When o is large, the interstitial oxygen concentration [Oi] f after high-temperature heat treatment is large, and as mentioned earlier, low-temperature heat treatment may cause interstitial oxygen to become a donor, increasing the carrier concentration and changing the characteristics of the semiconductor device. There is.

Figure 5 shows P(100) due to donorization of interstitial oxygen.
This is a chart showing changes in resistivity of a wafer with a resistivity of 10 Ωcm, where the horizontal axis shows the heat treatment time at 450°C and the vertical axis shows the resistivity of the wafer. In the figure, curve A
is [Oi] f=0.5×10 ¹⁸ /cm ^-3 , and curve B is [Oi]
f=0.7×10 ¹⁸ /cm ^-3 , curve C is [Oi] f=0.9×
10 ¹⁸ /cm ³ , curve D is [Oi] f=1.0×10 ¹⁸ /cm ³ , curve E is [Oi] f=1.2×10 ¹⁸ /cm ³ , curve F is [Oi]
f=1.4×10 ¹⁸ /cm ³ , curve G is [Oi] f=0.9×
The case of 10 ¹⁸ /cm ³ is shown, but [Oi] f shown in curve F
For =1.4×10 ¹⁸ /cm ³ , when heat treatment is 20 hours,
For [Oi]f=1.9×10 ¹⁸ /cm ³ shown in curve G, N reversal was shown when the heat treatment time was 10 hours.

Although the cumulative total of this type of low-temperature heat treatment time during actual semiconductor device manufacturing does not reach 5 hours at most, the resistivity decreases from 10 Ωcm to about 20 Ωcm in 5 hours, as shown in curve E [Oi]f=1.2× It is reasonable to set the upper limit to 10 ¹⁸ /cm ³ .

Based on the above research results, the straight lines A, B in Figure 2,
Although the limit values shown in C and D were obtained, an example of a semiconductor device manufacturing method that satisfies these requirements is based on the precipitated amount Δ[Oi] of interstitial oxygen that forms the required internal crystal defect density and size. , select an untreated silicon wafer with a precipitated amount [Oi]o of interstitial oxygen concentration that has a necessary margin with respect to the lower and upper limits of the interstitial oxygen concentration [Oi]f after the completion of the high-temperature heat treatment.
On the other hand, the amount of precipitated interstitial oxygen during the semiconductor device manufacturing process is determined in advance, and the amount of interstitial oxygen precipitated on the wafer with the reference value of Δ[Oi] and the selected [Oi]o during the semiconductor device manufacturing process. Compare with. Generally, the former is larger than the latter, and a heat treatment that gives the amount of precipitated interstitial oxygen equal to the difference between them is performed as a wafer pretreatment prior to the semiconductor device manufacturing process.

If the pre-wafer heat treatment of the present invention is carried out according to the method of the aforementioned Japanese Patent Application No. 56-035023 and No. 56-035024, the maximum temperature increase in the heat treatment [B] following the heat treatment [A] In many cases, it is appropriate to keep the temperature in a low temperature range of 950°C or less to keep the defect nucleus in a state that has not yet grown into an internal crystal defect, and it is usually unnecessary to repeat heat treatment [B] two or more times. It is.

As explained above, according to the present invention, in the manufacturing process of a semiconductor device, an unheated silicon substrate manufactured by the CZ method is heat-treated at a temperature of 950°C or more for 10 minutes or more, and then the heat treatment is performed at a rate of 14°C/min. A heat treatment including the following temperature raising process is performed one or more times to remove 0.1×10 ¹⁸ /cm ^-3 of the interstitial oxygen contained in the substrate.
Crystal defects are formed inside the substrate by precipitating oxygen of 0.8×10 ¹⁸ /cm ^-3 or more, and the concentration of residual interstitial oxygen inside the substrate is 0.7×10 ¹⁸ /cm ^-3 or more. By doing so, it is possible to obtain a good IG effect while preventing the occurrence of substrate warpage or slip lines, and furthermore, the concentration of interstitial oxygen in the substrate after the completion of the above treatment can be reduced to 1.2×10 ¹⁸ /cm ³ or less. By doing so, it is possible to suppress changes in the resistivity of the substrate due to donorization of interstitial oxygen.
This has a great effect on improving the quality of semiconductor devices using this effect.

[Brief explanation of the drawing]

Figures 1 a to c are diagrams showing the growth of internal crystal defect size and density according to the prior art, Figure 2 is a diagram showing the features of the present invention, and Figure 3 is a diagram showing the amount of interstitial oxygen precipitation and the amount of wafer warpage. Figure 4 shows the correlation between the interstitial oxygen concentration and the amount of wafer warpage after high-temperature heat treatment, and Figure 5 shows the correlation between 450°C heat treatment time and wafer resistivity. FIG.

Claims (1)

[Claims] 1. In the manufacturing process of a semiconductor device, a silicon substrate in an unheated state manufactured by the CZ method is
After heat treatment for more than 10 minutes at a temperature above 14℃
By performing heat treatment including a temperature raising step of ℃/min or less once or more, oxygen of 0.1×10 ¹⁸ /cm ^-3 or more and 0.8×10 ¹⁸ /cm ^-3 or less of the interstitial oxygen contained in the substrate is removed. 1. A semiconductor device characterized by comprising a step of depositing crystal defects to form crystal defects inside a substrate, and at the same time making the concentration of residual interstitial oxygen inside the substrate 0.7×10 ¹⁸ /cm ^-3 or more. Production method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the concentration of interstitial oxygen in the substrate after the completion of the step is 1.2×10 ¹⁸ /cm ⁻³ or less.