JPH03240027A - Display device - Google Patents
Display deviceInfo
- Publication number
- JPH03240027A JPH03240027A JP2037704A JP3770490A JPH03240027A JP H03240027 A JPH03240027 A JP H03240027A JP 2037704 A JP2037704 A JP 2037704A JP 3770490 A JP3770490 A JP 3770490A JP H03240027 A JPH03240027 A JP H03240027A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- drain electrode
- array substrate
- electric conductor
- source electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明はTFTアレイ基板及び上記TFTアレイ基板を
用いた表示装置の、信頼性向上に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improving the reliability of a TFT array substrate and a display device using the TFT array substrate.
[従来の技術]
液晶表示装置は、通常2枚の対向した基板の間に液晶等
の表示材料が挟持され、この表示材料に電圧を印加する
方法で構成される。この際、少なくとも一方の基板にマ
トリクス状に配列した画素電極を設け、これらの画素を
選択的に動作するために各画素毎にTFT等の非線型特
性を有する能動素子を設けている。[Prior Art] A liquid crystal display device is usually constructed by a method in which a display material such as a liquid crystal is sandwiched between two opposing substrates, and a voltage is applied to the display material. At this time, pixel electrodes arranged in a matrix are provided on at least one of the substrates, and in order to selectively operate these pixels, an active element having nonlinear characteristics such as a TFT is provided for each pixel.
従来この種の装置としては、第3図及び第4図に示す様
なものがあり、第3図は従来の装置の部分平面図、第4
図は第3図のB−BIFi面図である。Conventionally, there are devices of this type as shown in FIGS. 3 and 4. FIG. 3 is a partial plan view of the conventional device, and FIG. 4 is a partial plan view of the conventional device.
The figure is a B-BIFi plane view of FIG. 3.
まず、洗浄されたガラス等の透明絶縁性基板(1)上に
EB蒸着法、またはスパッタリング法によりI To
(Indium Tin 0xide)を成膜する。こ
れをフォトエツチング法等により所望のパターンに加工
し、画素電極(2)及び電極端子等を形成する。2番目
にCrあるいはMo等の高融点金属をスパッタリング法
等で成膜し、同様にパターン加工してゲート電極及び配
線等(3)を形成する。3番目にゲート絶縁膜(4)と
してSiO2やSiN、半導体層(5)として1−a−
Si:Hや poli−Siそしてエツチングストッパ
ー(6)としてSiNやSiO2を連続的にプラズマC
VD法等で成膜する。4番目にエツチングストッパーに
ソース及びドレインコンタクト用のコンタクトホールを
形成し、前処理後ソース及びドレインのオーミックコン
タクト層(7)としてのn−a −3i :Hを、プラ
ズマCVD法等で成膜する。5番目に画素電極とドレイ
ン電極(9)をつなぐためのコンタクトホールを形成す
る。6番目にA l / Cr及びAl/MO等をスパ
ッタリング法等で成膜し、パターン加工してソース電極
・配線(8)及びドレイン電極(9)を形成する。この
時、パターンあるいはプロセスによってはA l ((
8−1)及び(9−1))とCr(orM o )
((8−2)及び(9−2))の成膜あるいはパターン
加工を2回に分けることもある。First, I to
(Indium Tin Oxide) is formed into a film. This is processed into a desired pattern by photoetching or the like to form a pixel electrode (2), an electrode terminal, etc. Second, a film of high melting point metal such as Cr or Mo is formed by sputtering or the like, and patterned in the same manner to form gate electrodes, wiring, etc. (3). Thirdly, SiO2 or SiN is used as the gate insulating film (4), and 1-a- is used as the semiconductor layer (5).
Si:H, poli-Si, and SiN or SiO2 as an etching stopper (6) are continuously exposed to plasma carbon.
A film is formed using a VD method or the like. Fourth, contact holes for source and drain contacts are formed in the etching stopper, and after pretreatment, a film of n-a-3i:H is formed as an ohmic contact layer (7) for the source and drain by plasma CVD or the like. . Fifth, a contact hole is formed to connect the pixel electrode and the drain electrode (9). Sixth, a film of Al/Cr, Al/MO, etc. is formed by sputtering or the like, and patterned to form a source electrode/wiring (8) and a drain electrode (9). At this time, depending on the pattern or process, A l ((
8-1) and (9-1)) and Cr(orMo)
The film formation or pattern processing ((8-2) and (9-2)) may be divided into two steps.
この後、ソース電極とドレイン電極の間等に残っている
n−a−Si:Hを除去する。そして、最後にTFTの
保ig(10)としてSiNあるいはSi02等の絶縁
膜をプラズマCVD法等で成膜しパターン加工する。Thereafter, na-Si:H remaining between the source electrode and the drain electrode is removed. Finally, an insulating film such as SiN or Si02 is formed as a TFT insulator (10) by plasma CVD or the like and patterned.
以下のTFTアレイ基板は構成される。このTFTアレ
イ基板に対向して、透明電極及びカラーフィルタ等を設
けた対向型pi基板を設け、この両者の間に液晶等を挟
持して液晶平面デイスプレィが構成される。The following TFT array substrate is constructed. Opposed to this TFT array substrate is a counter-type Pi substrate provided with transparent electrodes, color filters, etc., and a liquid crystal flat display is constructed by sandwiching a liquid crystal or the like between the two.
[発明が解決しようとする課題]
上記の様にしてTFTアレイ基板を形成する際、最後に
形成する保護膜(10)にはソース電極・配線及びドレ
イン電極に入力される信号のDC成分をカットする役割
もある。しかし、ソース電極・配線及びドレイン電極に
使われているAlは、SiNあるいはSi02を成膜す
る際やその他のプロセスの加熱(WaX約300℃)に
より、ヒロック(12)が成長し、これをSiNやSi
02等で覆うには、かなりの膜厚(1,5μm)以上必
要である(通常は第4図に示す様に覆えない)。しかし
、この様な厚い膜厚では画素電極に入った信号が減衰し
て、液晶に電圧がかからないか、それを防ぐためのパタ
ーン加工及びエツチング技術の開発が必要となるという
課題があった。[Problems to be Solved by the Invention] When forming the TFT array substrate as described above, the protective film (10) formed last is designed to cut the DC component of the signal input to the source electrode/wiring and drain electrode. There is also a role to play. However, when Al used for the source electrode, wiring, and drain electrode, hillocks (12) grow when SiN or Si02 is formed or by heating (WaX approximately 300°C) during other processes, and this YaSi
In order to cover with 02 etc., a considerable film thickness (1.5 μm) or more is required (normally, it cannot be covered as shown in FIG. 4). However, with such a thick film, the signal entering the pixel electrode is attenuated, causing no voltage to be applied to the liquid crystal, or requiring the development of pattern processing and etching techniques to prevent this.
本発明は上記のような課題を解決するためになされたも
ので、ソース電極・配線及びドレイン電極の表面を陽極
酸化法により酸化し、ソース電極・配線及びドレイン電
極の表面を絶縁体Al2O3で覆いDCカット性及びそ
の信頼性を向上させるとともに、上記のTFTアレイ基
板形成プロセスの高コストな保護膜形成プロセスを削減
することによる低コスト化を目的としている。The present invention has been made to solve the above problems, and involves oxidizing the surfaces of the source electrode, wiring, and drain electrode by anodizing, and covering the surfaces of the source electrode, wiring, and drain electrode with an insulator, Al2O3. The purpose of this invention is to improve DC cut performance and its reliability, and to reduce costs by eliminating the expensive protective film formation process in the above-mentioned TFT array substrate formation process.
[課題を解決するための手段]
この発明に係る表示装置は、酒石酸アンモニウム溶液等
を用いた陽極酸化法でソース電極・配線及びドレイン電
極のAl表面を酸化し、ソース電極・配線及びドレイン
電極のAIが絶縁体Al2O、で覆われた構造にしたも
のである。[Means for Solving the Problems] A display device according to the present invention oxidizes the Al surface of the source electrode/wiring and drain electrode by an anodic oxidation method using an ammonium tartrate solution or the like. It has a structure in which AI is covered with an insulator Al2O.
[作用]
この発明における表示装置は、酒石酸アンモニウム溶液
等を用いた陽極酸化法でソース電極・配線、及びドレイ
ン電極のAl表面を酸化し、ソース電極・配線及びドレ
イン電極のAlが絶縁体Al2O3で覆われた構造にす
ることにより、従来法で用いていたDCカット膜が不要
になるばかりでな(、DCもれを完全になくすことがで
きる[実施例コ
以下に本発明のTFTアレイ基板及びそれを用いた液晶
平面デイスプレィの構成について説明する。[Function] In the display device of the present invention, the Al surfaces of the source electrode, wiring, and drain electrode are oxidized by an anodic oxidation method using an ammonium tartrate solution, etc., so that the Al of the source electrode, wiring, and drain electrode becomes an insulator Al2O3. The covered structure not only eliminates the need for the DC cut film used in the conventional method, but also completely eliminates DC leakage. The structure of a liquid crystal flat display using this will be explained.
第1図及び第2図は本発明の構成を示す図で、第1図は
本発明のTFTアレイ基板の部分平面図、第2図は第1
図のA−Alyt面図である。1 and 2 are diagrams showing the configuration of the present invention. FIG. 1 is a partial plan view of the TFT array substrate of the present invention, and FIG.
It is an A-Alyt side view of a figure.
まず、透明絶縁性基板(1)にITOをEBi着法、ま
たはスパッタ法等で約1000人成膜し、これをフォト
エツチング法等でパターン加工し、画素電極(2)及び
電極端子等を形成する。2番目にCr等の高融点金属を
スパッタ法等で、約2000人成膜し、パターン加工し
てゲート電極・配線(3)、ゲート及びソース端子配線
、それらをTFTアレイの外周で接続しているショート
リング。First, approximately 1,000 people deposit ITO on a transparent insulating substrate (1) using the EBi deposition method or sputtering method, and pattern this using photoetching methods to form pixel electrodes (2), electrode terminals, etc. do. Second, about 2000 people deposited a high-melting point metal such as Cr by sputtering, patterned it, and connected the gate electrode/wiring (3), gate and source terminal wiring, and the outer periphery of the TFT array. Short ring.
そしてそのショートリングに接続している陽極酸化用パ
ッドを形成する。3番目にゲート絶縁膜(4)としての
Si07やSiNを1000〜5000人、半導体層(
5)として1−a−3i:Hやpoli−Si を1
00〜2000人、そしてエツチングストッパー(6)
としてのSiNやSiO22000〜3000人を連続
的にプラズマCVD法等で成膜する。4番目にエツチン
グストッパーにソース及びドレインコンタクト用のコン
タクトホールを形成し、前処理後ソース及びドレインコ
ンタクト層(7)としてのn−a−3i:Hをプラズマ
CVD法等で成膜する。5番目に画素電極(2)とドレ
イン電pi(9)をつなぐためのコンタクトホールを形
成する。6番目にA l / CrおよびA l /
M o等をスパッタリング法等で成膜し、フォトエツチ
ング法等でパターニングし、ソース電極・配線(8)及
びドレイン電極(9)を形成する。この時、Al((8
−1)及び(9−1))とCr (M o ) ((
8−2)及び(9−2))を別々に成膜及び加工しても
良い。また、Cr(Mo) の膜厚は1000〜20
00人、Alは約5000〜10000人とする。7番
目に酒石酸アンモニウム溶液やシュウ酸溶液等を用いた
陽極酸化法により、ソース・ドレイン電極のAl表面に
約500〜5000人の酸化膜(11)を形成する。最
後にソース電極とドレイン電極の間等に残っているn−
a−Si:H等をエツチング除去する。Then, an anodic oxidation pad connected to the short ring is formed. Third, Si07 or SiN as the gate insulating film (4) is deposited by 1,000 to 5,000 layers, and the semiconductor layer (
5) as 1-a-3i:H or poli-Si as 1
00-2000 people, and etching stopper (6)
A film of 2,000 to 3,000 SiN or SiO2 is continuously formed using a plasma CVD method or the like. Fourth, contact holes for source and drain contacts are formed in the etching stopper, and after pretreatment, a film of n-a-3i:H is formed as a source and drain contact layer (7) by plasma CVD or the like. Fifth, a contact hole is formed to connect the pixel electrode (2) and the drain electrode pi (9). sixth, A l /Cr and A l /
A film of Mo or the like is formed by a sputtering method or the like, and patterned by a photoetching method or the like to form a source electrode/wiring (8) and a drain electrode (9). At this time, Al((8
-1) and (9-1)) and Cr (Mo) ((
8-2) and (9-2)) may be formed and processed separately. In addition, the film thickness of Cr(Mo) is 1000 to 20
00 people, and Al about 5,000 to 10,000 people. Seventh, an oxide film (11) of approximately 500 to 5,000 layers is formed on the Al surface of the source/drain electrode by an anodic oxidation method using an ammonium tartrate solution, an oxalic acid solution, or the like. Finally, the remaining n-
a-Si:H etc. are removed by etching.
以上の様にして、本発明のTFTアレイ基板は構成され
る。このTFTアレイ基板に対向して、透明電極及びカ
ラーフィルタ等を設けた対向電極基板を設け、この両者
の間に液晶等の表示材料を挟持して、本発明の液晶平面
デイスプレィが構成される。The TFT array substrate of the present invention is constructed as described above. A counter electrode substrate provided with transparent electrodes, color filters, etc. is provided opposite to this TFT array substrate, and a display material such as liquid crystal is sandwiched between the two, thereby constructing the liquid crystal flat display of the present invention.
[発明の効果]
以上のように、この発明によれば、ソース電極・配線及
びドレイン電極のAlはAl2O,(絶縁膜)で完全に
覆われるため、ソース電極・配線及びドレイン電極に入
力される信号にDC成分が発生したとしても、このAl
2O3で吸収されるため液晶を劣化させることがない。[Effects of the Invention] As described above, according to the present invention, Al of the source electrode/wiring and drain electrode is completely covered with Al2O (insulating film), so that Al2O is input to the source electrode/wiring and the drain electrode. Even if a DC component occurs in the signal, this Al
Since it is absorbed by 2O3, it does not deteriorate the liquid crystal.
叉このAl2O,膜は溶液を用いた陽極酸化法で形成さ
れているため、ピンホールのない均一な膜が形成でき、
仮にこの陽極酸化工程に入る前にAlにヒロック(12
)が発生したとしても、陽極酸化法の場合はヒロック全
体を覆う形でAl2O,が形成されるので、ヒロック上
に別の絶縁膜を堆積した時に生じる様なカバーレージ不
良が発生しないので、それによる点欠陥レベルのDCも
れも発生しない。This Al2O film is formed by an anodic oxidation method using a solution, so a uniform film without pinholes can be formed.
Before starting this anodic oxidation process, it is assumed that hillocks (12
) occurs, in the case of anodic oxidation, Al2O is formed to cover the entire hillock, so coverage defects that occur when another insulating film is deposited on the hillock will not occur. DC leakage at the level of point defects does not occur.
従って本発明の構造を用いて、TFTアレイ基板及び液
晶平面デイプレイを作成すれば従来法で用いていたDC
カット膜が不要になるばかりでなく、DCもれを完全に
なくすことができるので、表示品質及び製造歩留の向上
が期待できる。Therefore, if the structure of the present invention is used to create a TFT array substrate and a flat liquid crystal display, the DC
Not only does a cut film become unnecessary, but also DC leakage can be completely eliminated, so improvements in display quality and manufacturing yield can be expected.
第1図はこの発明の一実施例による液晶表示装置δに用
いられるTFTアレイ基板の要部を示す平面図。第2図
は第1図のA−Alti面図、第3図は従来の液晶表示
装置に用いられるTFTアレイ基板の要部を示す平面図
、第4図は第3図のB−B断面図である。
図において(1)は透明絶縁基板、(2)は画素電極、
(3)はゲート電極・配線、(4)はゲート絶縁膜、(
5)は半導体層、(6)はエツチングストッパー(7)
はオーミックコンタクト層、(8はソース電極・配線、
(8−1)はAl、(8−2)はCr orM o
、(9)はドレイン電極、(10)は保ys膜、(11
)は陽極酸化膜Al2O3、(12)はヒロックである
。
なお、図中、同一符号は同一または相当部分を示す。FIG. 1 is a plan view showing the main parts of a TFT array substrate used in a liquid crystal display device δ according to an embodiment of the present invention. Fig. 2 is an A-Alti plane view in Fig. 1, Fig. 3 is a plan view showing the main parts of a TFT array substrate used in a conventional liquid crystal display device, and Fig. 4 is a sectional view taken along B-B in Fig. 3. It is. In the figure, (1) is a transparent insulating substrate, (2) is a pixel electrode,
(3) is the gate electrode/wiring, (4) is the gate insulating film, (
5) is a semiconductor layer, (6) is an etching stopper (7)
is an ohmic contact layer, (8 is a source electrode/wiring,
(8-1) is Al, (8-2) is Cr orMo
, (9) is the drain electrode, (10) is the ys retention film, (11
) is an anodic oxide film Al2O3, and (12) is a hillock. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
ium Tin Oxide)等の透明導電膜で形成さ
れた画素電極、CrあるいはMo等の高融点金属で形成
されたゲート電極、SiNやSiO_2等の絶縁体で形
成されたゲート絶縁膜、i−a−Si:Hあるいはpo
li−Si等で形成された半導体層、SiNやSiO_
2等の絶縁膜で形成されたエッチングストッパー、n−
a−Si:H等で形成されたソース及びドレインコンタ
クト層、そしてAl/Mo、叉はAl/Cr等で形成さ
れたリース電極及びドレイン電極を有する薄膜トランジ
スタ(以下TFTという)アレイ基板、及び上記TFT
アレイ基板と透明電極及びカラーフィルタ等を有する対
向電極基板との間に液晶等の表示材料を挟持したマトリ
クス型表示装置において、酒石酸アンモニウム溶液等を
用いた陽極酸化法でソース電極・配線及びドレイン電極
のAl表面を酸化し、ソース電極・配線及びドレイン電
極のAlが絶縁体Al_2O_3で覆われた構造をする
ことを特徴とするTFTアレイ基板及びマトリクス型表
示装置。At least ITO (Ind.
A pixel electrode formed of a transparent conductive film such as (Ium Tin Oxide), a gate electrode formed of a high melting point metal such as Cr or Mo, a gate insulating film formed of an insulator such as SiN or SiO_2, ia- Si:H or po
Semiconductor layer formed of li-Si etc., SiN and SiO_
Etching stopper formed of a second grade insulating film, n-
A thin film transistor (hereinafter referred to as TFT) array substrate having source and drain contact layers formed of a-Si:H etc., and lease electrodes and drain electrodes formed of Al/Mo, Al/Cr etc., and the above TFT
In a matrix display device in which a display material such as a liquid crystal is sandwiched between an array substrate and a counter electrode substrate having transparent electrodes, color filters, etc., source electrodes, wiring, and drain electrodes are formed by anodizing using an ammonium tartrate solution, etc. A TFT array substrate and a matrix type display device characterized in that the Al surface of the substrate is oxidized and the Al of the source electrode, wiring, and drain electrode is covered with an insulator Al_2O_3.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2037704A JPH03240027A (en) | 1990-02-19 | 1990-02-19 | Display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2037704A JPH03240027A (en) | 1990-02-19 | 1990-02-19 | Display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03240027A true JPH03240027A (en) | 1991-10-25 |
Family
ID=12504917
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2037704A Pending JPH03240027A (en) | 1990-02-19 | 1990-02-19 | Display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03240027A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5418636A (en) * | 1992-06-05 | 1995-05-23 | Matsushita Electric Industrial Co., Ltd. | Liquid crystal image display apparatus with anodized films of the same thickness and a method of fabricating the same |
US6259495B1 (en) | 1998-01-20 | 2001-07-10 | Nec Corporation | Liquid crystal display panel and method of manufacturing the same, including a structure for, and a method of preparing, terminal or connecting electrodes for connecting liquid crystal display panel to an external drive circuit |
KR100434310B1 (en) * | 1998-09-02 | 2004-06-05 | 엘지.필립스 엘시디 주식회사 | A thin film transistor substrate using aluminum as a low resistance wiring and a liquid crystal display deuice using the same |
US7294924B2 (en) | 2003-12-22 | 2007-11-13 | Samsung Sdi Co., Ltd. | Flat panel display device and method of fabricating the same |
CN102709238A (en) * | 2011-12-22 | 2012-10-03 | 友达光电股份有限公司 | Array substrate and manufacturing method thereof |
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JPS5448681U (en) * | 1977-09-12 | 1979-04-04 | ||
JPS5739318U (en) * | 1980-08-15 | 1982-03-03 | ||
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JPH01167625U (en) * | 1988-05-17 | 1989-11-24 |
Cited By (9)
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US5418636A (en) * | 1992-06-05 | 1995-05-23 | Matsushita Electric Industrial Co., Ltd. | Liquid crystal image display apparatus with anodized films of the same thickness and a method of fabricating the same |
US6259495B1 (en) | 1998-01-20 | 2001-07-10 | Nec Corporation | Liquid crystal display panel and method of manufacturing the same, including a structure for, and a method of preparing, terminal or connecting electrodes for connecting liquid crystal display panel to an external drive circuit |
US6356336B2 (en) | 1998-01-20 | 2002-03-12 | Nec Corporation | Liquid crystal display panel and method for manufacturing the same |
US6362867B2 (en) | 1998-01-20 | 2002-03-26 | Nec Corporation | Method of manufacturing a liquid crystal display panel including preparing terminal or connecting electrodes for connecting liquid crystal display panel to an external drive circuit |
US6452648B2 (en) | 1998-01-20 | 2002-09-17 | Nec Corporation | Liquid crystal display panel and method for manufacturing the same |
US6515730B1 (en) | 1998-01-20 | 2003-02-04 | Nec Corporation | Method of manufacturing a liquid crystal display panel including a terminal electrode part thereof |
KR100434310B1 (en) * | 1998-09-02 | 2004-06-05 | 엘지.필립스 엘시디 주식회사 | A thin film transistor substrate using aluminum as a low resistance wiring and a liquid crystal display deuice using the same |
US7294924B2 (en) | 2003-12-22 | 2007-11-13 | Samsung Sdi Co., Ltd. | Flat panel display device and method of fabricating the same |
CN102709238A (en) * | 2011-12-22 | 2012-10-03 | 友达光电股份有限公司 | Array substrate and manufacturing method thereof |
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