JPH0323712A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To suppress ringing and also, to obtain VOH and VOL margins by inserting a resistor with a comparatively large resistance value between an output transistor and an output terminal, and providing a switching element to bias the resistor with certain delay time. CONSTITUTION:The resistor with the comparatively large resistance value is inserted between the output transistors TR1, TR2 and the output terminal, and an N-channel MOS transistor TR3 is provided in parallel with the resistor. And the output of a NOR gate 8 setting a node A and a node B as two input is connected to the gate of the N-channel MOS transistor TR3 connected in parallel with the resistor via delay circuits 5-7. Thereby, the output of the transistor TR1 or TR2 goes to 'H' via the resistor R when it is energized, however, at this time, the rise of the output is moderated since it passes through the resistor R, thereby, the ringing is suppressed. When a node C goes to 'H' with certain delay, the transistor TR3 is energized, and the resistor R is bypassed after a time t3, therefore, a final level of 'L' goes to almost 0V.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application J] This invention relates to a method of structuring a data output circuit of a semiconductor integrated circuit.

[Conventional technology]

Conventional semiconductor integrated circuits, particularly output circuits for buttoning digital p-circuits, have a structure as shown in FIG.

In the figure, Tri and Tr2 are N-channel type l1! O
S transistors (l) to (4) are inverters.

Next, the operation will be explained. Now node A. If the potential of B is in the "L" state, the transistors Tri, Tr
The gate of 2 is a transistor Trl that becomes 'L' level.
, Tr2 are in a non-conductive state. Therefore, the output terminal is '
High 'impedance state. Next, when the potential of node A changes from #L1 to "R1," the gate potential of transistor Tri becomes 1R# and transistor Tr
i becomes conductive. Therefore, "H#" is output to the output terminal. On the other hand, when the potential of node B changes from "L" to "H", the gate potential of transistor Tr2 becomes #H1 and transistor Tr2 becomes conductive.

Therefore, a low level is output to the output terminal. However, on the other hand, there is generally a certain amount of inductance L and a certain amount of capacitance C as shown in FIG. 3 as a load, and ringing as shown in FIG. 4 occurs in the output signal. In this case, when C or L is not effective, the output is determined at time tl, but if ringing occurs, the output is determined at time tzt with a delay, and the effective switching speed is There is a problem with the delay.

Further, in order to suppress this ringing, there is an output circuit as shown in FIG. This output circuit attempts to suppress ringing by inserting a resistor R between the output transistor and the output terminal.

[Problem to be solved by the invention]

Since the data output circuit of the conventional semiconductor integrated circuit was constructed as described above, the resistance between the output transistor and the output terminal could only be about 100 at most, and the effect was insufficient. The reason for this is that generally 1 of the output
L# level (VoLmax) and “R# level (VoH
With a current of approximately 5 mA flowing as the specification value of min), VoLa1ax is OAV and VoHmi is
There was a problem that it was necessary to set n to 2.4V, and if the resistance was increased, these specifications could no longer be satisfied.

This invention was made to eliminate the above-mentioned problems, and by inserting a relatively large resistance between the output transistor and the output terminal and inserting a switching element in parallel with this resistance, it is possible to reduce the and V
The purpose is to obtain an output circuit that satisfies the specifications of OL and VoH.

[Means for Solving the Problems] In the semiconductor integrated circuit according to the present invention, a relatively large resistance is inserted between the output transistor and the output terminal, an N-channel MOS transistor is provided in parallel with this resistance, and the node A and The output of the NOR gate with two node B inputs is connected to the gate of an N-channel MOS transistor connected in parallel with a resistor through a delay circuit made up of an N-channel MO8 transistor.

[Effect]

The output circuit of the semiconductor integrated circuit according to the present invention has a relatively large resistance between the output transistor and the output terminal, and a transistor that bypasses this resistance, so that it is possible to obtain a sufficient VOH VOL margin with little ringing. .

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, Tri to Tr3 are N-channel MOS
Transistors, (1) to (7) are inverters, and (8) is a NOR gate with two nodes A and B.

Next, the operation will be explained. Now the potential of nodes A and B is “
If it is in the L# state, the transistors Trl, Tr
The gate of TriTr2 becomes "L" level, so that TriTr2 becomes non-conductive, and the output becomes "High" impedance state. Next, the potential of node A changes from "L1 to #H1"
When the voltage becomes “H1”, the gate potential of the transistor Tri becomes “H1”.
The transistor Tri becomes conductive. Therefore, the output becomes "H#" through the resistor R, but at this time, since the output goes through the resistor R, its rise becomes gradual and linking is suppressed.On the other hand, while the output becomes "Ill", the node Since C becomes "H", the transistor Tr3 becomes conductive. Therefore, as shown in FIG. 2, since the resistor is bypassed after time t3, the final level of 1H1 becomes a sufficiently high voltage. On the other hand, the potential of node B changes from 1L# to ″
When it becomes H'', the transistor Tri is non-conductive and the transistor Tr2 is conductive, so the output is 1 through the resistor R.
However, at this time as well, since the voltage falls through the resistor R, the silling is suppressed relatively slowly at the beginning.Then, with a certain delay, the node C becomes 1H. The transistor Tr3 becomes conductive and the resistor R is bypassed after time t3, so the final "L"
The level of # is almost Ov.

[Effects of the Invention] As described above, according to the present invention, a resistor having a relatively large resistance value is inserted between the output transistor and the output terminal, and a switching element is provided that bypasses this resistor after a certain delay time. This has the effect that an output circuit with less ringing and sufficient VoH and VOL margins can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an output circuit showing an embodiment of the present invention;
Fig. 2 is a timing chart of each node to explain the operation of Fig. 1, Fig. 3 is a conventional output circuit k and equivalent load circuit diagram, and Fig. 4 is a potential change of each node to explain the operation of Fig. 3. FIG. 5 is a circuit diagram showing an improved example of the conventional output circuit shown in FIG. 3. (1) ~ (7) ... Imperter, (8) ・N
OR gate, Tri~Tr3...N channel M
OS }Ran resistor. In the middle, it shows. In the figures, the same reference numerals refer to the same or corresponding parts, Figure 3, Figure 11!1, Figure 4, Figure 2, t. tz 5th break 1J

Claims (2)

[Claims] (1) In a semiconductor integrated circuit equipped with a first switching element and an output terminal for receiving some signal generated on a chip and outputting this signal to the outside of the chip, a connection between the first switching element and the output terminal is provided. A resistor is provided, and a second switching element is provided in parallel with the resistor, and the second switching element conducts with a certain delay from an input signal that drives the first switching element. 1. A semiconductor integrated circuit characterized by having means for controlling it in such a manner. (2) The drain end is connected to the power supply, and the gate end is “H”
a first transistor connected to the output signal line and having a source end connected to a first electrode of the resistor; a drain end connected to the source end of the first transistor and a second electrode of the resistor; , a second transistor having a gate end connected to an "L" output signal line and a source end connected to a ground end, a second electrode of the resistor connected to an output terminal,
Its drain end and source end are connected to the first and second electrodes of the resistor, respectively, and its gate end is connected to the output of the means for generating a delay signal of the "H" and "L" output signals. A semiconductor integrated circuit comprising a third transistor connected to the semiconductor integrated circuit.