JPH0323584A - Picture data storage circuit - Google Patents

Abstract

PURPOSE:To efficiently use a storage means by providing a storage means where picture data is stored in a storage block designated by the block address based on the subordinate address. CONSTITUTION:Signal processing means 2 to 5 which convert an inputted video signal Vs to generate picture data Vd and addresses Ah and Av and horizontal and vertical address converting means 6a and 6b which separate addresses Ah and Av to host addresses Ah1 and Av1 and subordinate addresses Ah2 and Av2 and convert host addresses Ah1 and Av1 to the block address which designates a prescribed storage block of a storage means PROM are provided. A storage means (frame memory) 7 is provided where picture data is stored in the storage block designated by the block address based on subordinate addresses Ah2 and Av2. The prescribed storage block in the storage means 7 is designated by the block address and picture data Vd is stored in the designated storage block in accordance with subordinate addresses Ah2 and Av2 in this manner. Thus, the storage means is efficiently used.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an image data storage circuit suitable for use in a video printer device or the like for capturing the dots on a display screen.

``Prior Art'' This type of video printer device is equipped with an image data storage circuit for storing images (still images) displayed on a display device. FIG. 7 shows this image data storage circuit. FIG. 2 is a block diagram showing an example of a circuit. In this figure, 11 is a video signal input circuit, which digitalizes the input video signal Vs (NTSC composite signal) by A/D conversion (analog/digital conversion) and converts it into image data Vd and dot cross Ck.
At the same time, it outputs a horizontal synchronization pulse Ph1 and a vertical synchronization pulse Pv. 12 is a data port. l3 is a horizontal address counter, which counts Ck and Ck using the horizontal synchronizing pulse ph as a reset signal;
A horizontal address Ah is generated and output. A vertical address counter 14 counts the horizontal synchronization pulse ph using the vertical synchronization pulse Pv as a reset signal, and generates and outputs a vertical address Av. Reference numeral 15 denotes a frame memory, which is composed of a plurality of DRAMs (Guinaminoku RAM) and stores image data Vd according to horizontal addresses Ah and vertical addresses Av.

"Problems to be Solved by the Invention" By the way, in the above-mentioned image data storage circuit, the positions of dots (pixels) constituting the display area of the display device (pit map display method) and the address of the frame memory (horizontal address/ vertical address) is 1
There is a correspondence relationship of pair l.

Therefore, when applying the present invention to a plurality of display devices having different display area sizes, the memory size of the frame memory must be adjusted to the largest display area. For example, the size of the display area (horizontal dots x
(represented by vertical dots) are 640 x 320, 32, respectively.
When applied to a 0x640 display device, a frame memory is required that can allocate addresses corresponding to the maximum display area in both the horizontal and vertical directions, that is, 640 dots in the horizontal direction x 640 dots in the vertical direction.

However, the capacity of the frame memory is 6, which can store image data for the display area of the display device.
It is sufficient to have a capacity of 40 x 320 dots, and the above-mentioned memory size (640 x 640 dots) causes a problem in that the memory capacity is wasted and the frame memory is not used efficiently.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide an image data storage circuit that can efficiently use a frame memory.

"Means for Solving the Problems" The present invention includes a signal processing means that converts an input video signal and generates image data and an address, and separates the address into an upper address and a lower address. address conversion means for converting an address into a block address specifying a predetermined storage block of the storage means; storage means for storing the image data in the storage block specified by the block address based on the lower address; It is characterized by having the following.

"Operation" According to the present invention, a predetermined storage block within the storage means is specified by a block address, and image data is stored in the specified storage block according to the lower address.

"Embodiment" Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the basic configuration of an image data storage circuit 1 according to an embodiment of the present invention. In this figure, 2 is a video signal input circuit, which digitizes the manually input video signal Vs (NTSC composite signal) by A/D conversion (analog/digital conversion), and converts it into image data Vd and dot clock Ck.
At the same time, it separates a horizontal synchronizing signal and a vertical synchronizing signal from the video signal v8, and outputs a horizontal synchronizing pulse ph and a vertical synchronizing pulse Pv generated based on each signal. 3 is a data boat. A horizontal address counter 4 counts the dot clock Ck as a horizontal synchronizing pulse PholJ-trt signal, generates and outputs a horizontal address Ah. A vertical address counter 5 counts horizontal synchronizing pulses ph using the vertical dome pulse Pv as a reset signal, and generates and outputs a vertical address Av. 6a is a horizontal address conversion circuit which divides the manually entered horizontal address Ah into 5 bits of an upper address and 5 bits of a lower address, and provides the 5 bits of the upper address as an address value of a writable non-volatile memory (FROM). This FROM outputs conversion data (described later) according to a conversion pattern written in advance in accordance with a given address value, and the output data becomes the horizontal block address Ahl. Furthermore, the 5 bits of the lower address are output as they are as the horizontal lower address Ah2.

6b is a vertical address conversion circuit which, like the horizontal address conversion circuit 6a, divides the vertical address Av into 5 upper address bits and 5 lower address bits, and converts the 5 upper address bits into a vertical block address Avl converted by FROM. The 5 bits of the lower address are output as is as the lower vertical address AV2.

FIGS. 2 and 3 show an example of address conversion in the FROM mentioned above. Figure 2 shows 640 donots in the horizontal direction.
FIG. 3 shows an example of address conversion when χ·1 is applied to a display device with 320 dots in the vertical direction.
An example of address conversion is shown in the case of a display device with a size of 20 dots and 640 donts in the vertical direction. In these figures, the manual address is the upper five bits of the horizontal address Av and vertical address Ah input to the FROM, and each address value is expressed in decimal notation. In addition, the output data is a memory block (described later) number of the frame memory 7 specified by the horizontal block address Ahl and vertical block address Awl converted corresponding to the manual address value, and the number is expressed in lO base. ing.

Next, the frame memory 7 is composed of a plurality of DRAMs (dynamic RAMs), and its memory capacity corresponds to the image data Vd for the largest display area of the plurality of display devices to which it is applied. For example, when corresponding to the example shown in Fig. 2 or Fig. 3, 204800
This is the memory capacity to store image data Vd for dots (640x320). The memory 7 also has a horizontal lower address Ah2 (5 bits) and a vertical lower address Av2.
(5 bits) in the horizontal direction defined by 3 2
(= 25) DonotoX Vertical direction 3 2 (-2') Separated into storage blocks of Do, G.

FIG. 4 shows the configuration of the storage block. In this figure, O~1023 in the memory block indicates an address;
Each address is designated by a horizontal lower address Ah2 and a vertical lower address Av2, and image data Vd is stored in the designated address.

Each such storage block has a horizontal block address A
hl and a vertical block address Avl. For example, 640 in the horizontal direction, 320 in the vertical t1 direction
In the case of supporting a dot display device, each storage block is designated based on the output data shown in FIG. 2, and as a result, the frame memory 7 has the memory structure shown in FIG. 5. In addition, when responding to a display device with 320 dots in one direction and 6401 dots in the vertical direction, each memory block is designated based on the output data shown in FIG. 3, and as a result, the memory 7 has the memory configuration shown in FIG.

Next, the operation of the image data storage circuit 1 in the configuration described above will be explained. First, for example, when a video signal S from a display device with a display area of 640 dots in the horizontal direction x 320 dots in the vertical direction is manually input, the video signal input circuit 2 inputs image data Vd, dots.
Notoclock Ck, water i11 tJl pulse ph and vertical synchronization pulse Pv are generated. Next, the clock pulse Ck and the horizontal synchronization pulse ph are input to the horizontal address counter 4, and the horizontal synchronization pulse ph and the vertical clock pulse Pv are input to the vertical address counter 5. A horizontal address Ah and a vertical address Av corresponding to the address (donoto) are generated and output.

Next, the horizontal address Ah and the vertical address Av are input to a horizontal address conversion circuit 6a and a vertical address conversion circuit 6b, respectively, and the conversion shown in FIG. 2 is performed. Then, the image data Vd is sequentially transferred to each memory block (see FIG. 5) of the frame memory 7 designated by the conversion via the data boat 3 based on the horizontal lower address Ah2 and the direct lower address Av2. is written and stored.

Next, for example, a video f from a display device with a display area of 320 mm in the horizontal direction x 640 mm in the vertical direction.
When No. 3 VS is input, each signal is generated by the video signal human power circuit 2 in the same manner as described above, and each signal is output from the horizontal address counter 4 and the vertical address counter 5 to the display area (320 donots) of the display device. ×
640 dots)). h and vertical address AV are output. And horizontal address A
h and the vertical address Av are respectively input to the horizontal address conversion circuit 6a and the vertical address conversion circuit 6b, and the conversion shown in FIG. (See FIG. 6) Image data Vd is sequentially written and stored via the data port 3 based on the horizontal lower address Ah2 and the vertical lower address AV2.

In this way, the horizontal block address Ahl and the vertical block address Awl are converted according to the conversion patterns respectively stored in the PROMs provided in the horizontal address conversion circuit 6a and the vertical address conversion circuit 6b.
The memory structure of the frame memory 7 is made to correspond to the display area. Therefore, when applying the image data storage circuit l to various display devices, a plurality of conversion patterns corresponding to the display area are stored in the PROM as described above, and furthermore, based on a selection signal from the outside, The circuit structure is such that these can be selected arbitrarily.

Further, the frame memory 7 is not limited to DRAM, and it goes without saying that memory elements such as SRAM that can be accessed at higher speeds can also be used. Further, color processing can be easily realized by taking in a color image signal, having a frame memory for each color component (R, G, B), and performing the same processing as in this embodiment.

In addition, when the image data storage circuit l becomes capable of handling multiple display areas as in the above case, it is possible to store image data for only the necessary display area of the display device, or store image data for multiple display areas within the capacity of the frame memory. It is also possible to store image data for the display area. In this case, if the image data storage circuit 1 is used in a video printer device, it becomes possible to take hard copies of a plurality of display screens by one printing.

"Effects of the Invention" As explained above, according to the present invention, there is provided a signal processing means for converting a manually generated video signal to generate image data and an address, and converting the address into an upper address and a lower address. address conversion means for converting the upper address into a block address specifying a predetermined storage block of the storage means; and the image data is stored in the storage block specified by the block address based on the lower address. Since the storage means is provided, there is an effect that the storage means can be used efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of an embodiment of the present invention, and FIGS.
FIG. 4 is a diagram showing an example of address conversion of a ROM, FIG. 4 is a diagram showing a structure of a storage block in the same embodiment, FIGS. 5 and 6 are diagrams each showing a memory structure of a frame memory in the same embodiment, FIG. 7 is a block diagram showing a basic configuration example of a conventional image data storage circuit.

Claims (1)

[Scope of Claim] A storage circuit that stores image data corresponding to display dots of a display device, comprising: a signal processing means that converts an input video signal and generates image data and an address; address converting means for separating an address and a lower address and converting the upper address into a block address specifying a predetermined storage block of the storage means; An image data storage circuit comprising: storage means in which the image data is stored.