JPH03235143A - Cache memory controller - Google Patents

Abstract

PURPOSE:To curtail the number of times of flash of the cache contents, while contriving the high speed conversion of an access by adding a process identification number as an address of a cache memory, and dividing and using the cache memory at every process. CONSTITUTION:With respect to an address of a cache memory 4, a process identification number from a register B9, and an index of a virtual address VA are given to a high order one and a subordinate one, respectively. Accordingly, a data memory 5 and a tag memory 6 are divided into four areas corresponding to the process identification number, and in these areas, data and tag information are written or read out in or from an entry subjected to address designation by the index. In such a way, while holding the high speed conversion of an access, based on a virtual address cache, the number of times of flash of the cache contents by a context switch can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a virtual address cache memory that stores a copy of a portion of data in a main memory and stores a virtual address of the stored data as tag information.

(b) Conventional technology "Interface February 1989 issue P, 263-F,
As disclosed in 276, cache memory can be roughly divided into two types: one is a virtual address cache that stores tag information based on virtual addresses, and the other is a virtual address cache that stores tag information based on virtual addresses. This is a physical address cache that stores physical addresses converted by a conversion unit (referred to as MMU) as tag information.

Virtual address cache has the advantage of speeding up access because it accesses the cache using the virtual address output by the processor as is, but it also has the advantage of speeding up access.
The disadvantage is that the contents of the cache must be flushed every time a so-called context switch occurs.

On the other hand, a physical address cache maintains information consistency between the cache and main memory, so there is no need to flush the contents of the cache every time a context switch occurs, but it does require translation to a physical address for access. Therefore, cache access is delayed by the conversion time.

(c) Problems to be Solved by the Invention In the conventional technology, both virtual address cache and physical address cache have advantages but each has its own disadvantages, and ideal cache memory control cannot be achieved. I couldn't make it happen.

Therefore, an object of the present invention is to reduce the number of times cache contents are flushed while taking advantage of high-speed access in a virtual address cache.

(d) Means for Solving the Problems The present invention includes a data memory that stores a copy of a part of data in the main memory, and a first part of the virtual address of the data stored in the data memory as tag information. , and a tag memory that stores a valid bit indicating the validity of data, and which inputs the second part of the virtual address output by the processor as an address. A process identification number generating means is provided for allocating serial process identification numbers to a predetermined number of processes, generating the process identification number of the process that the processor intends to execute, and storing the process identification number from the generating means in the cache. The above-mentioned problem is solved as a configuration in which the address is added as a memory address.

(f) Effect In the present invention, since the process identification number is added as the address of the cache memory, the cache memory is divided and used for each process. In this case, there is no need to flush the contents of the cache even if a context switch occurs. Additionally, since a virtual address cache is basically used, access speed is not compromised.

(F) Embodiment FIG. 1 is a block diagram showing a direct computer cache as an embodiment of the present invention, in which (1> is an MPU that outputs a virtual address VA, and (2) is a main memory that stores data. , (3) converts virtual address VA to physical address RA
The MMU (4) is a cache memory consisting of a data memory (5) that stores a copy of a part of data in the main memory and a tag memo (6).

(7) is the process I assigned by O8 to multiple processes.
Among D, process I that MPU (1) attempts to execute
D is the register A to be set, and in this embodiment O
Since 8 is assigned 256 process IDs, register A consists of 8 bits. The output of this register A is input to MMU (3), and MM
U (3) converts the virtual address VA into a physical address RA according to the process to be executed, and stores it in the main memory (2).
is given as an address. Note that the offset portion of the virtual address VA is given as is as a lower address of the main memory (2>).

Further, in this embodiment, in O8, arbitrary four processes are selected from 256 process IDs, and each process is assigned a serial process identification number '004. '01,1.
'10' and 'll' are assigned, and their correspondence is explained in the fourth section.
As shown in the figure, it is stored in table (8). Then, the process identification number corresponding to the process that the MPU (1) intends to execute is set in the 2-bit register B (9), and the output of this register B (9) is
It is given as an upper address to the data memory (5) and tag memory (6) in the cache memory (4).

The index field in the virtual address VA shown in FIG. 2 is input as the lower address of both memories (5) and (6) of the cache memory (4), and the virtual address VA
The tag field inside is stored as tag information in tag memory (6)
is memorized. This tag memory (6) also stores a valid bit V indicating the validity of the stored data.
By resetting this valid bit, the corresponding cache data is flushed, ie, invalidated.

By the way, in Figure 1, (10) (11) (12)
is the buffer that controls the bus connection, and (13) is the MPU (
a comparator (14) that compares the tag field of the virtual address output by 1) with the tag information read from the tag memory;
) is an AND gate that takes the logical product of the output of the comparator and the read valid bit, and (15) controls the buffers (10), (11), and (12) according to the output of the AND gate, and also controls the tag memory (6). 〉 control logic that resets the valid bit, 〈16) is the control logic only when resetting the valid bit (15〉), a multiplexer MUX that selects the logic address output from 〉, 1) MU that selects the physical address output by
X, and a table (8) is stored in a specific area of the main memory (2).
The O5 containing the MPU (1) is resident, and the O5 is directly accessed by the physical address output by the MPU (1) in the supervisor mode.

This example will be explained in more detail below.

First, since the address of the cache memory (4) is given the process identification number from register B in the upper part and the index of the virtual address VA in the lower part, the data memory (5) and the tag memory (6> As shown in Figure 3, is divided into four areas (5a) to (5d) and (6a) to (6d) corresponding to the process identification number, and within these areas, the entries addressed by the index are Data and tag information are written or read.

For example, as shown in FIG. 4, the process ID 'l'.

'50. ．． '100. ．． '125J (when assigned to bus o(=Sfi specific number r00' to '11'), the MPU (1) attempts to execute the process with process ID '50.' and stores the process ID '50' in register A.
Then, when the process identification number "01." is set in register B and the virtual address VA is output, in the data memory (5), the data addressed by the index of the divided area (5b) is transferred to the buffer (11).
The tag information addressed by the index of the divided area (6b) is read out in the tag memory (6>) and sent to the comparator (13).
It is compared with the tag field of the virtual address output by MPU (1).

As a result of the comparison, if the tags match and the valid bit is set, the cache has been hit and the MPU
In (1), the imported data is determined to be correct and used. When there is no hit, data corresponding to the virtual address is read from the main memory (2) into the MPU (1) via the buffer (10) based on the physical address converted by the MMU (3). Also, this data and the tag field of the corresponding virtual address are stored in divided areas (5b) and (6) in the data memory (5) and tag memory (6), respectively.
b) is written to the end node addressed by the index in b). At this time, if the valid bit of the stored data has been reset, it is validated.

In this way, each divided area of the cache memory (4>) is used by each of the four processes, so when a context switch occurs between these four processes, there is no need to flush the cache contents.

Here, we will explain concretely including the processing contents of O8.
As shown in FIG. 5, when a context switch occurs, O8 searches whether the next process to be executed by MPU (1) is the process assigned to table (8), and If it is a process, its process ID is set in register A, and its process identification number is set in register B, without flushing the cache.

Also, for example, process ID'70. When a process that is not allocated to the table (8) is to be executed, such as the process in the table (8), any one of the four divided areas of the cache memory (4) is completely flushed. That is, set the process identification number corresponding to the area to be flushed in register B, and
gives a flush instruction to the control logic (15). Then, the control logic (15) is
By sequentially outputting logic addresses covering the entire area to the tag memory (6) and outputting a reset signal, all valid bits in the area are reset by hardware and flash is performed.

After flushing one area, the process ID number corresponding to that area is changed to the new process ID to be executed, here "70.", and the following is similarly set to registers A and B. I do.

In the embodiment described above, independent registers A and B are provided to respectively set the process ID and process identification number of the process to be executed. B can also be used as A. For example, the output of the lower two bits of register A is used instead of the output of register B. In this case, process identification number r00,
have process IDs 0, 4, 8 .・・・・・・・・・、
Any one of 252 process IDs must be assigned, and similarly, rol.

For rto, ,'it, the lower two bits are each r
A restriction is added that one of the process IDs "01", "rlo", and "11" is assigned, and the degree of freedom is reduced compared to the above-mentioned embodiment in which it was possible to arbitrarily select a process ID. However, the circuit configuration is simplified.

Furthermore, it goes without saying that the present invention can be applied not only to the above-mentioned direct Matsubutsu cache but also to n-way set associative caches.

(G) Effects of the Invention According to the present invention, it is possible to reduce the number of times cache contents are flushed by context switching while maintaining high-speed access based on a virtual address cache.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG.
Figure 3 shows the field contents of virtual addresses, Figure 3 shows the relationship between cache memory and process identification numbers, Figure 4 shows the correspondence table between process IDs and process identification numbers, and Figure 5 shows the correspondence table between process IDs and process identification numbers. It is a flowchart which shows the processing content of O8 in an Example. (1)...MPU, (2)...Main memory, (3)
...MMU, (4) ...cache memory,
(5)...Data memory, (6)...Tag memory, (7)...Register A1 (8)...Table, (9)...Register B, (13)...Comparison Container, (15)...controller.

Claims (1)

[Claims] (1) A data memory that stores a copy of part of the data in the main memory, and a valid bit that stores the first part of the virtual address of the data stored in the data memory as tag information and indicates the validity of the data. In a cache memory control device, the second part of the virtual address output by the processor is input as an address, and the second part of the virtual address output by the processor is input as an address. A process identification number generation means is provided for assigning a number and generating the process identification number of a process that the processor is to execute, and the process identification number from the generation means is added as an address of the cache memory. Characteristic cache memory control device.