JPH03232246A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPH03232246A JPH03232246A JP2054485A JP5448590A JPH03232246A JP H03232246 A JPH03232246 A JP H03232246A JP 2054485 A JP2054485 A JP 2054485A JP 5448590 A JP5448590 A JP 5448590A JP H03232246 A JPH03232246 A JP H03232246A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- areas
- wires
- area
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、パワートランジスタモジュールなどを対象と
した半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device intended for power transistor modules and the like.
まず、第５図、第６図により、従来におけるプレーナ形
パワートランジスタモジュールの構造を説明する。図に
おいて、１はパワートランジスタチップ、２はトランジ
スタチップｌを実装したパッケージの基板、３，４．５
はトランジスタチップ１のコレクタ、ベース、エミッタ
電極と接続し合うように基板１に形成した導体であり、
それぞれが外部リードのコレクタ、ベース、エミッタ端
子に接続されている。また、トランジスタチップ１は下
面側にはコレクタ電極が、上面側にはそれぞれ方形状に
なるアルミニュウム膜のベース電極６、およびメツシュ
形、＜シ形などのエミッタパターン（図示せず）に対し
複数箇所（図示例では４１所）のボンディングエリア７
ａ〜７ｄに分割したエミッタ電極７が形成されている。First, the structure of a conventional planar power transistor module will be explained with reference to FIGS. 5 and 6. In the figure, 1 is the power transistor chip, 2 is the substrate of the package on which the transistor chip l is mounted, 3, 4.5
is a conductor formed on the substrate 1 so as to be connected to the collector, base, and emitter electrodes of the transistor chip 1,
Each is connected to the collector, base, and emitter terminals of the external leads. In addition, the transistor chip 1 has a collector electrode on the lower surface side, a base electrode 6 of an aluminum film having a rectangular shape on the upper surface side, and multiple locations for an emitter pattern (not shown) such as a mesh shape or square shape. Bonding area 7 (41 locations in the illustrated example)
An emitter electrode 7 divided into parts a to 7d is formed.
そして、トランジスタチップ１はコレクタ電極を下向き
にして基板２の導体３の上にグイボンディングでマウン
トされ、さらにベース電極６．エミッタ電極７と基板側
の導体４．５との間が各ボンディングエリアごとにアル
ミニュウム細線のボンディングワイヤ８を介して個々に
ワイヤボンディングされている。また、９は過電流制限
用ダイオード（リードタイプ）であり、ベース側の導体
４とエミッタ側の導体５との間にまたがって半田付けさ
れている。なお、トランジスタのベース。Then, the transistor chip 1 is mounted on the conductor 3 of the substrate 2 with the collector electrode facing downward, and the base electrode 6. The emitter electrode 7 and the conductor 4.5 on the substrate side are individually wire-bonded via thin aluminum bonding wires 8 for each bonding area. Further, 9 is an overcurrent limiting diode (lead type), which is soldered across between the conductor 4 on the base side and the conductor 5 on the emitter side. In addition, the base of the transistor.
エミッタ間に過電流制限用ダイオードを接続した回路は
、例えば特開昭５８−８１３１３号公報などで公知であ
り、第７図にその回路を示す。A circuit in which an overcurrent limiting diode is connected between emitters is known, for example, from Japanese Patent Application Laid-open No. 81313/1983, and the circuit is shown in FIG.
ところで、前記のようにエミッタ電極７を複数のボンデ
ィングエリア７ａ〜７ｄに−分けて形成したトランジス
タチップ１に対し、各ボンディングエリアごとに基板２
側の導体５との間で個々にワイヤボンディングを施す場
合には、前後に並ぶボンディングエリア７ａと７ｃ、お
よび７ｂと７ｄから引出したボンディングワイヤ８が一
直線上に並んでループ同士が交錯するのを避けるために
、図示のように導体５側でのボンド地点を左右にずらし
、ボンディングワイヤ８をボンディングエリアに対して
斜め方向にボンドするようにしている。By the way, for the transistor chip 1 in which the emitter electrode 7 is divided into a plurality of bonding areas 7a to 7d as described above, the substrate 2 is separated for each bonding area.
When wire bonding is performed individually with the side conductor 5, the bonding wires 8 pulled out from the bonding areas 7a and 7c and 7b and 7d lined up in front and back are lined up in a straight line and the loops intersect with each other. To avoid this, the bonding point on the conductor 5 side is shifted to the left or right as shown in the figure, and the bonding wire 8 is bonded diagonally to the bonding area.
しかして、ワイヤボンディング法では、周知のようにボ
ンディングヘッドを移動しながらキャピラリからワイヤ
８を引出して圧着させる関係から方向性があり、仮にボ
ンディングエリアの面積を必要最小限の幅ｄに規制した
とすると、図示のようにワイヤ８を斜め方向にボンドす
る箇所では僅かなワイヤのずれがボンド不良を誘発して
製品の歩留りを低める。このためにボンディングへラド
の移動操作に高い位置決め精度が要求されるなど、作業
性がすこぶる悪い難点があった。However, as is well known, in the wire bonding method, the wire 8 is pulled out from the capillary and crimped while moving the bonding head, so there is a directionality, and if the area of the bonding area is regulated to the minimum necessary width d, Then, as shown in the figure, at a location where the wire 8 is bonded in an oblique direction, a slight deviation of the wire induces a bonding failure and reduces the yield of the product. For this reason, high positioning accuracy was required for the operation of moving the Rad to the bonding area, resulting in extremely poor workability.
なお、前記の問題に対して、ワイヤボンディングの作業
性（ボンディングヘッドの位置決め条件など）を緩和す
るために、チップ電極の全てのボンディングエリア（第
５図におけるボンディングエリア７ａ〜７ｄ）をあらか
じめ大きな面積に形成したとすると、当然のことながら
ボンディングエリアを拡大した分だけトランジスタとし
て必要な動作領域を確保するためにトランジスタチップ
自身が大形化してコストアップを招く。In order to solve the above problem, in order to ease the workability of wire bonding (bonding head positioning conditions, etc.), all the bonding areas of the chip electrodes (bonding areas 7a to 7d in FIG. 5) have a large area in advance. Naturally, if the bonding area is expanded, the transistor chip itself becomes larger to secure the operating area necessary for the transistor, leading to an increase in cost.
本発明は上記の点にかんがみなされたものであり、先述
のようにトランジスタのエミッタ電極が複数のボンディ
ングエリアに区分されているパワートランジスタを用い
たパワートランジスタモジュールなどの半導体装置を対
象に、半導体素子自身を大形化することなく、ワイヤボ
ンディング作業性の大幅な改善が図れるようにした半導
体装置を提供することを目的とする。The present invention has been made in view of the above points, and is directed to a semiconductor device such as a power transistor module using a power transistor in which the emitter electrode of the transistor is divided into a plurality of bonding areas as described above. An object of the present invention is to provide a semiconductor device that can greatly improve wire bonding workability without increasing its size.
上記課題を解決するために、本発明の半導体装置におい
ては、チップ電極の各ボンディングエリアのうち、ボン
ディングワイヤを斜め方向にボンドする箇所のボンディ
ングエリアを、他のボンディングエリアよりも面積を大
に形成して構成するものとする。あるいは、ステッチボ
ンディングする箇所のボンディングエリアを、他のボン
ディングエリアよりもボンディング方向に縦長に形成し
て構成するものとする。In order to solve the above problems, in the semiconductor device of the present invention, among the bonding areas of the chip electrode, the bonding area where the bonding wire is bonded diagonally is formed to have a larger area than the other bonding areas. It shall be configured as follows. Alternatively, the bonding area where stitch bonding is to be performed is formed to be longer in the bonding direction than other bonding areas.
上記構成のように、複数箇所に区分けされているチップ
電極の各ボンディングエリアのうち、ワイヤを斜め方向
にボンドする箇所のみを多少面積大にして余裕を持たせ
ることで、半導体素子自身を大形化することなしに、他
のボンディングエリアから引出したワイヤとの間でルー
プ干渉を回避するに必要、かつ十分なボンディングエリ
アを確保してワイヤボンディングを安定よく行うことが
できる。As shown in the above configuration, among the bonding areas of the chip electrode that are divided into multiple locations, only the area where the wire is bonded diagonally is slightly enlarged to provide some margin, allowing the semiconductor element itself to be enlarged. It is possible to secure a necessary and sufficient bonding area to avoid loop interference with wires pulled out from other bonding areas, and to perform wire bonding stably without causing problems.
また、前記の面積大なボンディングエリアを利用するこ
とで、例えばトランジスタのベース、エミッタ間に接続
する過電流制限用ダイオードなどの素子を基板上のベー
ス側導体にマウントした状態で、該素子より半導体素子
のエミッタ電極のボンディングエリアを経て基板側の導
体との間にワイヤを連続的にステッチボンディングする
ことも可能である。この場合、ステッチボンディングの
ボンディング方向に面積大であることが望ましい。In addition, by using the large bonding area mentioned above, it is possible to connect an element, such as an overcurrent limiting diode between the base and emitter of a transistor, to the base conductor on the substrate. It is also possible to stitch-bond the wire continuously between the bonding area of the emitter electrode of the device and the conductor on the substrate side. In this case, it is desirable that the stitch bonding has a large area in the bonding direction.
第１図、第２図、および第３図、第４図はそれぞれ本発
明の異なる実施例の構成図であり、第５図１第６図に対
応する同一部材には同じ符号が付しである。1, 2, 3, and 4 are configuration diagrams of different embodiments of the present invention, and the same members corresponding to FIGS. 5, 1, and 6 are given the same reference numerals. be.
まず、第１図、第２図の実施例において、トランジスタ
チップ１のエミッタ電極７としてチップ面上に分散形成
したボンディングエリア７ａ〜７ｄのうち、基板２側の
導体５から見て遠い方に位置するボンディングエリア７
ａ、７ｂの幅りが他のボンディングエリア７ｃ、７ｄの
幅ｄよりも大き（して面積大に形成されている。そして
、前記の各ボンディングエリア７ａ〜７ｄと基板２側の
導体５との間で個々にワイヤ８が一ボンディングされて
いる。ここで、ボンディングエリア７ａと７ｂに対して
はボンディングエリア７ｃ、７ｄを迂回するようにワイ
ヤ８を斜め側方に引出してボンディングし、ボンディン
グエリア７ｃ、７ｄに対してはワイヤ８を真っ直ぐに引
出してボンディングしている。したがって各ボンディン
グエリアから引出したワイヤ８の間でループが交錯、干
渉し合うことがない。しかも、・前記のようにボンディ
ングエリア７ａ、７ｂは幅りを拡大して面積大に形成し
であるので、ワイヤ８を斜め方向にボンドする際に多少
の位置決め誤差があってもワイヤのずれを生じることな
く確実にボンドできる。First, in the embodiments shown in FIGS. 1 and 2, among the bonding areas 7a to 7d dispersedly formed on the chip surface as the emitter electrode 7 of the transistor chip 1, the one farthest from the conductor 5 on the substrate 2 side is located. Bonding area 7
The widths of the bonding areas a and 7b are larger than the width d of the other bonding areas 7c and 7d (thus, they are formed in a larger area. Wires 8 are individually bonded between the bonding areas 7a and 7b.The wires 8 are pulled out diagonally to the side and bonded to the bonding areas 7a and 7b so as to bypass the bonding areas 7c and 7d. , 7d, the wires 8 are pulled straight out for bonding.Therefore, the wires 8 pulled out from each bonding area do not intersect or interfere with each other.Moreover, as mentioned above, the wires 8 pulled out from the bonding areas Since the wires 7a and 7b are formed to have a large area by increasing the width, even if there is a slight positioning error when bonding the wire 8 in an oblique direction, the wire can be reliably bonded without causing any displacement of the wire.
次に、第３図、第４図は前記実施例の構成に過電流制限
用ダイオードを一緒に組み込んだ実施例を示すものであ
る。すなわち、過電流制限用ダイオード９のチップ（マ
ウント型チップ）は基板２側の導体４に直付けしてマウ
ントされ、さらにダイオード９の電極と、トランジスタ
１のエミッタ電極７のボンディングエリア７ｂと、基板
側のも体５との間を連続的に結んでワイヤ８がステラ；
ボンディングされている。かかる構成により、３５図、
第６図に示した従来構造と比べてダイオード９を組み込
むのに要する作業工数を削減してストダウンできる。Next, FIGS. 3 and 4 show an embodiment in which an overcurrent limiting diode is also incorporated into the structure of the above embodiment. That is, the chip (mounted chip) of the overcurrent limiting diode 9 is directly mounted on the conductor 4 on the substrate 2 side, and the electrode of the diode 9 and the bonding area 7b of the emitter electrode 7 of the transistor 1 are connected to the substrate. The wire 8 is connected continuously to the thigh body 5 on the side;
It is bonded. With this configuration, Figure 35,
Compared to the conventional structure shown in FIG. 6, the number of man-hours required to incorporate the diode 9 can be reduced and downtime can be achieved.
なお、ステッチボンディング法はポールボンシイフグ法
などに比べてボンド部の長さが大となべので、これに対
応させるためには前記実施例に−けるボンディングエリ
ア７ｂについて、あらか１め幅寸法と併せてボンディン
グ方向である長さ法りも他のボンディングエリアよりと
比べて多く拡大して形成しておくのがよい。In addition, since the stitch bonding method has a longer bond part length than the pole bonding method, etc., in order to accommodate this, the width dimension of the bonding area 7b in the above embodiment should be adjusted by the first width dimension. In addition, it is preferable that the length dimension in the bonding direction be expanded more than other bonding areas.
なお、半導体装置の回路構成により抵抗、コデンサなど
の素子をトランジスタチップ１に接玲して組み込む場合
でも、前記の過電流制限用ダ・オード９と同様に、面積
大に形成したトランジ。Note that even when elements such as a resistor and a capacitor are mounted on the transistor chip 1 depending on the circuit configuration of the semiconductor device, the transistor is formed with a large area like the overcurrent limiting diode 9 described above.
タチップ１のボンディングエリア７ｂを利用し一連続的
にステッチボンディングすることが可能ある。It is possible to perform continuous stitch bonding using the bonding area 7b of the data chip 1.
本発明の半導体装置は、以上説明したように構成されて
いるので、次記の効果を奏する。Since the semiconductor device of the present invention is configured as described above, it achieves the following effects.
（１）ワイヤを斜めにボンドする箇所のボンディングエ
リアのみを他のボンディングエリアに比べて面積大とし
たことにより、半導体素子を大形化することなく、ワイ
ヤボンディングの作業性が改善できて製品の品質向上化
が図れる。(1) By making only the bonding area where wires are bonded diagonally larger than other bonding areas, the workability of wire bonding can be improved without increasing the size of the semiconductor element. Quality can be improved.
（２）また、半導体素子に他の受動、能動素子を組合せ
て回路を構成する場合でも、半導体素子１こ形成した面
積大なボンディングエリアを利用して他の素子との間を
ステッチボンディングすることができ、これにより組立
作業の簡易化が図れる。(2) Also, even when configuring a circuit by combining a semiconductor element with other passive and active elements, it is possible to perform stitch bonding between the other elements using the large bonding area formed on one semiconductor element. This simplifies the assembly work.
第１図は本発明一実施例の構成を示す平面図、第２図は
第１図の側面図、第３図は第１図と男ＩＪな実施例の平
面図、第４図は第３図の側面図、第５図は従来における
パワートランジスタモジニールの構成の平面図、第６図
は第５図の側面図、第７図は第５図をシンボルで表した
回路図である。図において、
１ トランジスタチップ（半導体素子）、２基板、３，
４．５ 導体、６ ベース電極、７エミツタ電極、７
ａ〜７ｄ ボンディングエリア、ｄ
第１図
第２図Fig. 1 is a plan view showing the configuration of an embodiment of the present invention, Fig. 2 is a side view of Fig. 1, Fig. 3 is a plan view of an embodiment similar to Fig. 1, and Fig. 4 is a side view of Fig. 5 is a plan view of the configuration of a conventional power transistor Modineal, FIG. 6 is a side view of FIG. 5, and FIG. 7 is a circuit diagram representing FIG. 5 with symbols. In the figure, 1 transistor chip (semiconductor element), 2 substrate, 3,
4.5 Conductor, 6 Base electrode, 7 Emitter electrode, 7
a~7d Bonding area, d Figure 1 Figure 2
Claims (1)
ングエリアに区分けされている半導体素子をパッケージ
の基板上にマウントし、かつ前記の各ボンディングエリ
アとこれに対応する基板側の導体との間を個々にワイヤ
ボンディングしてなる半導体装置において、前記チップ
電極の各ボンディングエリアのうち、ボンディングワイ
ヤを斜め方向にボンドする箇所のボンディングエリアを
、他のボンディングエリアよりも面積を大に形成したこ
とを特徴とする半導体装置。 ２）チップ面上に形成したチップ電極が複数のボンディ
ングエリアに区分けされている半導体素子をパッケージ
の基板上にマウントし、かつ前記の各ボンディングエリ
アとこれに対応する基板側の導体との間を個々にワイヤ
ボンディングしてなる半導体装置において、基板側の少
なくとも一方の導体とボンディングワイヤとの間に能動
または受動素子を介在させ、該能動または受動素子と少
なくとも１つの前記ボンディングエリアおよび他方の導
体との間でステッチボンディングが行われる時、該ステ
ッチボンディングする箇所のボンディングエリアを、他
のボンディングエリアよりもボンディング方向に縦長に
面積を大に形成したことを特徴とする半導体装置。[Claims] 1) A semiconductor element in which chip electrodes formed on a chip surface are divided into a plurality of bonding areas is mounted on a substrate of a package, and each bonding area and the corresponding substrate side are mounted on a substrate of a package. In a semiconductor device formed by individual wire bonding between the conductors of the chip electrode, the area of the bonding area where the bonding wire is bonded diagonally among the bonding areas of the chip electrode is larger than that of the other bonding areas. A semiconductor device characterized in that it is formed in. 2) A semiconductor element in which chip electrodes formed on the chip surface are divided into a plurality of bonding areas is mounted on a substrate of a package, and a connection is made between each bonding area and the corresponding conductor on the substrate side. In a semiconductor device formed by individual wire bonding, an active or passive element is interposed between at least one conductor on the substrate side and the bonding wire, and the active or passive element is connected to at least one of the bonding areas and the other conductor. 1. A semiconductor device characterized in that, when stitch bonding is performed between the semiconductor devices, a bonding area where the stitch bonding is performed is formed to be vertically elongated in the bonding direction and have a larger area than other bonding areas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2054485A JPH03232246A (en) | 1989-12-12 | 1990-03-06 | semiconductor equipment |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32207289 | 1989-12-12 | ||
| JP1-322072 | 1989-12-12 | ||
| JP2054485A JPH03232246A (en) | 1989-12-12 | 1990-03-06 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03232246A true JPH03232246A (en) | 1991-10-16 |
Family
ID=26395248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2054485A Pending JPH03232246A (en) | 1989-12-12 | 1990-03-06 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03232246A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014027293A (en) * | 2013-09-11 | 2014-02-06 | Renesas Electronics Corp | Semiconductor device |
| US8796838B2 (en) | 2003-06-30 | 2014-08-05 | Renesas Electronics Corporation | Semiconductor device |
| JP2016040839A (en) * | 2015-10-27 | 2016-03-24 | ルネサスエレクトロニクス株式会社 | Method of manufacturing semiconductor device |
| JP2019153662A (en) * | 2018-03-02 | 2019-09-12 | 日亜化学工業株式会社 | Light emitting device and manufacturing method thereof |
| US11581252B2 (en) | 2020-03-13 | 2023-02-14 | Fuji Electric Co., Ltd. | Semiconductor module and wire bonding method |
-
1990
- 1990-03-06 JP JP2054485A patent/JPH03232246A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8796838B2 (en) | 2003-06-30 | 2014-08-05 | Renesas Electronics Corporation | Semiconductor device |
| US9165901B2 (en) | 2003-06-30 | 2015-10-20 | Renesas Electronics Corporation | Semiconductor device |
| JP2014027293A (en) * | 2013-09-11 | 2014-02-06 | Renesas Electronics Corp | Semiconductor device |
| JP2016040839A (en) * | 2015-10-27 | 2016-03-24 | ルネサスエレクトロニクス株式会社 | Method of manufacturing semiconductor device |
| JP2019153662A (en) * | 2018-03-02 | 2019-09-12 | 日亜化学工業株式会社 | Light emitting device and manufacturing method thereof |
| US11581252B2 (en) | 2020-03-13 | 2023-02-14 | Fuji Electric Co., Ltd. | Semiconductor module and wire bonding method |
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