JPH03231460A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce a cell size, to make a resistance high, to make a density high and to make a power consumption low by installing the following: a diffusion layer, of an opposite conductivity type, which is connected to a gate electrode of a MOS transistor; a plurality of insulating films; and a resistance layer for load element use. CONSTITUTION:A field oxide film 2 and a gate oxide film 3 are formed on a P-type silicon substrate 1; a contact hole 4 is made in the film 3. Then, an N-type diffusion layer 7 is formed; after that, a gate electrode 5 which has been connected to the layer 7 and a silicon oxide film 6 are formed. Then, an N<-> type diffusion layer 8 connected to the layer 7 is formed; after that, a silicon oxide film 9 is deposited on the whole surface; a sidewall part 9a is formed. Then, an N<+> type diffusion layer 10 is formed; only a silicon oxide film 11 is removed by making use of a photoresist film 12 as a mask; a contact hole 13 is made. The film 12 is removed; after that, a high-resistance layer 14 and a power-supply interconnection 14a which is connected to the layer 14 are formed; an interlayer insulating film 15 is deposited on their surface; a contact hole 16 is made; a digit line 17 is formed. Thereby, a cell size is reduced, a resistance is made high, a density is made high and a power consumption is made low.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a static memory element.

[Conventional technology]

As shown in FIGS. 3(a) and 3(b), a conventional semiconductor memory device includes a field oxide film 2 that is selectively provided on a P-type silicon substrate 1 to partition an element formation area, and a field oxide film 2 that is selectively provided on a P-type silicon substrate 1 to partition an element formation area. Gate oxidation on the surface! 113 and gate oxide film 3
A contact hole 4 provided by opening, a gate electrode 5 provided on the gate oxide film 3, and an N-type electrode provided on the surface of the P-type silicon substrate 1 in the contact hole 4 provided on the gate oxide film 3. A gate electrode 5a connected to the diffusion layer 7 and an N
``The silicon oxide film 18 provided on the surface including the type diffusion layer 10 and the gate electrodes 5 and 5a, and the contact hole for opening the silicon oxide film 18 to expose the ends of the N1 type diffusion layer 10 and the gate electrode 5a. 19 and contact hole 19
A high-resistance layer 4 made of a high-resistance polycrystalline silicon film connected to the N3 type diffusion layer 10 and the gate electrode 5a and extending over the silicon oxide film 18, and a power source arrangement provided in connection with the high-resistance layer 4. i 14 a.

[Invention or problem to be solved]

In the conventional semiconductor memory device described above, a contact hole including the diffusion layer and the end of the gate electrode connected to the diffusion layer was provided, and a resistance layer was provided connected to the diffusion layer and the gate electrode, so it was not necessary to open the contact hole. In order to do this, there is a drawback that it is difficult to form micro contact holes using photoresist film processing and dry etching.

[Means to solve the problem]

The semiconductor memory device of the present invention is a semiconductor memory device having a resistive load type static memory element having a MOS transistor provided on a conductive type semiconductor substrate and a resistive layer connected to the MOS transistor and serving as a load element. , a diffusion layer of an opposite conductivity type provided on the semiconductor substrate connected to the gate electrode of the MOS transistor, a first insulating film covering the surface of the gate electrode, and an entire surface including the first insulating film. a second insulating film provided, and a resistance layer for the load element connected to the diffusion layer of the contact hole provided in the second insulating film and extending over the second insulating film. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1F are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to an embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type silicon substrate 1
A field oxide film 2 is selectively provided thereon to define an element formation region, and a gate oxide film 3 is formed on the surface of the element formation region. Next, a contact hole 4 is formed by selectively opening the gate oxide film, a polycrystalline silicon film is deposited to a thickness of 0.3 μm on the surface including the contact hole 4, and phosphor is formed in the polycrystalline silicon film. Atoms are introduced to increase the electrical conductivity of the polycrystalline silicon film, and phosphorus is diffused from the polycrystalline silicon film to the inner surface of the P-type silicon substrate 1 through the contact hole 4 to form an N-type diffusion layer 7. An ohmic contact is formed with the silicon film, and a silicon oxide film is deposited to a thickness of 0.2 μm on the polycrystalline silicon film. next,
A gate electrode 5a made of a polycrystalline silicon film is connected to the gate electrode 5 and the N-type diffusion layer 7 by selectively sequentially etching the silicon oxide film and the polycrystalline silicon film, and gate electrodes 5, 5a are formed on the gate electrodes 5, 5a. A silicon oxide film 6 matching the pattern is formed.

Next, using the gate electrodes 5, 5a and the silicon oxide film 6 as masks, phosphorus ions were implanted at an acceleration energy of 40 keV and a dose of 1×10 CII-2.
An N- type diffusion layer 8 connected to the type diffusion layer 7 is formed.

Next, as shown in FIG. 1<b>, silicon oxide M9 is deposited on the entire surface to a thickness of 0.3 μm.

Next, as shown in FIG. 1(c), the silicon oxide film 9 is etched back by the thickness of the silicon oxide film 9 by anisotropic plasma etching, leaving the silicon oxide film 9 only on the side walls of the gate electrode 5 and the side wall portions 9a. form. Next, using the gate electrode and side wall portion 9a as a mask, arsenic atoms are accelerated with an energy of 70k.
Ion implantation is performed under the conditions of eV and a dose of 5×IQ 15cv−2 to form an N+ type scattering layer 10.

Next, as shown in FIG. 1(d), a silicon oxide film 11 is deposited on the entire surface to a thickness of 0.2 μm, and a photoresist film 12 is applied and patterned.
Using this as a mask, only the silicon oxide film 11 is removed by etching with buffered hydrofluoric acid to form a contact hole 13.
form.

Next, as shown in FIG. 1(e), the photoresist film 1
2, a high resistance polycrystalline silicon film is deposited on the surface including the contact hole 13. It is deposited to a thickness of 1 μm and selectively etched to form the high resistance layer 14. Phosphorus atoms are selectively ion-implanted into a part of the high resistance polycrystalline silicon film to form the high resistance layer 14. A power supply wiring 14a to be connected is formed.

Next, as shown in FIG. 1(f), a glabellar insulating film 15 is deposited to a thickness of 1 μm on the surface including the high resistance layer 14 and the power supply wiring 14a, and this is selectively etched to form contact holes 16. form.

Next, an aluminum layer is deposited on the surface including the contact hole 16 and selectively etched to form the N+ type scattered layer 10.
A digit line 17 for connection is provided.

FIG. 2 is a plan view of FIG. 1(f). However, the digit line 17 is omitted to simplify the drawing.

〔Effect of the invention〕

As explained above, the present invention provides a semiconductor memory device having a resistive load type static memory element, in which a contact hole connected from a power wiring layer to a note electrode of a cell flip-flop via a high resistance element loads the high resistance element. A hole is formed in the surface of the diffusion layer that is connected to the gate electrode of the transistor to form the cell node electrode, and the high resistance element is connected to the gate electrode through the diffusion layer to form contact 1 to hole formation. In the processing of photo-L/cyst film, the cell size can be reduced because there is no need to worry about the alignment margin of the gate electrode, and the diffusion layer region between the underlying wiring layers, which was not used in the past, can be used. can do. Regarding the high resistance layer, by making contact with the cell node electrode at a location farther from the power wiring section, the resistance can be made higher, realizing a semiconductor memory device with a static memory element with higher density and lower power consumption. can do.

Note that a polycide layer may be used instead of the polycrystalline silicon film.

[Brief explanation of drawings]

1(a) to ('f) are plan views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to an embodiment of the present invention, FIG. 2 is a plan view of FIG. 1(f>), Figure 3 (a>, (b)
) is a plan view and a sectional view taken along the line A-A' of a conventional semiconductor memory device. 1...P-type silicon substrate, 2...field oxide film,
3... Gate oxide film, 4... Contact hole, 5
．． 5a... Gate electrode, 6... Silicon oxide film, 7
...N type diffusion layer, 8...N- type diffusion layer, 9...Silicon oxide film, 9a...Side wall portion, 1o...N+ type scattering layer 11...Silicon oxide film , 12... Photoresist film, 13... Contact hole, 14... High resistance layer, 14a power supply wiring, 15... Interlayer insulating film, 16
...Contact hole, 17...Digital line, 1
8-, silicon oxide film, 19... contact hole.

Claims (1)

[Claims] a MOS transistor provided on a semiconductor substrate of one conductivity type;
In a semiconductor memory device having a resistive load type static memory element having a resistive layer connected to the MOS transistor and used as a load element, an opposite conductivity type static memory element connected to the gate electrode of the MOS transistor and provided on the semiconductor substrate. a diffusion layer, a first insulating film covering the surface of the gate electrode, a second insulating film provided on the entire surface including the first insulating film, and a contact hole provided in the second insulating film. A semiconductor memory device comprising: a resistance layer for the load element connected to the diffusion layer and extending over the second insulating film.