JPH03229332A - Microcomputer system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a microcomputer system, and particularly to a microcomputer system in which a non-maskable interrupt processing program is stored in a random access memory.

(Prior art) For example, a 16-bit central processing unit (hereinafter referred to as CPU)
), one of the predefined interrupts
A non-maskable interrupt (Non-Maskable interrupt)
This NMI has the highest priority and is normally used for emergency interrupts such as power failures. This NM() becomes capable of accepting interrupts by releasing the reset of the CPU, and cannot be masked (stopped) by software.

By the way, the N to II processing block processing tecogram system program or initial program loading (hereinafter referred to as IPL)
Random access memory (hereinafter referred to as R)
Conventionally, in a microcomputer system that is stored in a
Since there is no way to prohibit one input, during rPL (that is,
If an NMI is input when the NMI processing program has not yet been set, the CPU may run out of control and the peripheral devices of the microcomputer system may be destroyed.

Also, when inserting the NM (which stores system programs including processing programs) into the floppy disk drive during system setup, errors such as incorrect insertion direction or insufficient insertion may occur. If this occurs, fPL cannot be performed normally after the system starts operating. However, conventionally, there is no way to automatically detect an IPL abnormality and stop the CPU operation or display the abnormality. , notice 72B
, it is necessary to turn off the system illumination at point y,
The microcomputer system is not easy to use.

(The invention attempts to solve the problem.: 1li) As mentioned above, in the conventional microcomputer and Buke system, when l'JM+ is input during IPL, the CPU goes out of control and destroys the peripheral devices of the microcomputer system. There is a problem with putting it away.

In addition, I
If PL cannot be performed normally, there is no means for automatically detecting IPL abnormality and slowing down CPU operation or displaying the abnormality, so there is a problem that the microcombutan stem is not easy to use.

The present invention was made to solve the above problems).

The purpose of this is to prevent the CPU from running even if an NMI is input when the NMI processing program is not yet set during IPL, and to prevent peripheral devices from running when the CPU runs. An object of the present invention is to provide a microcomputer system that can prevent destruction of the computer.

Another object of the present invention is to automatically and immediately detect IPLrAi, stop CPU operation, and display an abnormal state of deafness or generate an alarm even if IPL cannot be performed normally. The object of the present invention is to provide a microcomputer system that enables the use of the system and improves the usability of the system.

[Configuration of the Invention (Means for Solving the Three Problems) The first invention is a data input device that stores a CPU, a ROM in which an initial setting program is written, and a system program including an NMI processing program. In a microcomputer system comprising: a RAM in which a system program stored in the data input device is stored by IPL; and an interrupt input device, during IPL, input of NM [that appears to the CPU from the interrupt input device] f
g11.

Further, in the microcomputer system of the first invention, a second invention further includes detecting whether or not the IPL operation is performed within a certain period of time after the system reset operation; The present invention is characterized in that it includes a control means for forcibly resetting the CPU and displaying an abnormal operation state or issuing an alarm when it is detected that the CPU has failed.

(Function) In the microcombutan stem of the first invention, the IP
Equipped with NM1 input prohibition means that prohibits input of NMI in L, even if NMI is input when the NMI processing program is not yet set during IPL, the CPU is prevented from going out of control. Yes, the CPU! It is possible to prevent damage to peripheral devices due to one run.

Furthermore, in the microcomputer system of the second invention, when it is detected that the IPL operation has not been performed within a certain period of time after the system reset operation, in the microcomputer system of the second invention, Since it is equipped with a control means that forcibly resets the CPU and also displays an abnormal operation state or issues an alarm, it prevents erroneous operations during system setup of data input devices that store system programs including NMI processing programs. Even if IPL cannot be performed normally, it is possible to automatically and immediately detect an IPL abnormality, stop CPU operation, and display the abnormal condition or generate an alarm, improving system usability. .

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Figure 1 shows a 16-bit microcomputer system used as the main controller of bank terminals, tellers, etc., and 10 is a 16-bit CPU.
(For example, Intel 8086 in the United States), 11 and 12 are RAM and ROM connected to CPU10.
It is. As shown in the memory map shown in Figure 2, this RAM II and ROM 12 have space addresses of 0 to 1 Mbytes, and are physically arranged in words from θ to 512, with 16 bits in units of one word. There is. In this case, R.A.
MII has 15 bank segments in 64,
It has address areas 00000(H) to EFFFF(H). In addition, ROMI 2 has one bank segment at 64, and the address area FOOOO(H) to FF
Ladle FFF(H).

An initial setting program including an IPL program (boot program) is written in the ROM 12, and the first instruction (IPL
Direct jump instruction to the program start address)
is placed from address FFFF0 (H).

Further, in RAMI 1, a system program including an NMr processing program (routine) is stored by IPL. In this case, the address Di”l [1nn(H) ~ 0
(A byte area of 1 up to 13FF (H) is allocated as an interrupt pointer table, and address 00
000 (H) to 00013 (H) is a predefined interrupt pointer area, starting at address 00
2 words (4 bytes) from 008 (H) to 0OOOB (H) are the NMI pointer area, and address 003
NM [processing program is placed in a part of the area after FF(H).

On the other hand, 13 is a data input device (in this example, a floppy disk drive device that drives a 3.5-inch floppy disk, for example, which stores a system program including an NMI processing program); is controlled so that it is stored in RAMI 1 from IPLI.

14 is an interrupt input device (for example, a power supply abnormality ejection circuit).

Furthermore, in this embodiment, in the above-mentioned microcomputer system, during IPL, the NMI input from the interrupt input device 14 to the CPU10 is performed at 71. NMI to do
The input inhibiting means 2o detects whether or not an IPL operation has been performed within a certain period of time after the system reset operation, and [
It is equipped with a control means 3o that forcibly resets the CPU10 and displays an abnormal operation state (or may generate an alarm) when it is detected that the PL operation has not been performed within a certain period of time. .

That is, the NM1 input inhibiting means 20 includes a two-input NAND gate 21, an NM1 input inhibiting/cancelling flip-flop circuit 22, and a two-input NAND gate 23. Here, the two-input NAND gate 21 with active L is NMI
The active L" signal MC5OOO is obtained by decoding the interrupt address (00008H) of
8H and an active L° memory write signal MWR supplied from CPU10 are input. NMI input prohibited/
The release flip-flop circuit 22 has an active ``H'' data input terminal and an active LOW set input terminal S connected to the Vcc7T1 source, and has an active ``H'' clock input terminal CP connected to a two-input NAND gate 2.
1 output signal is input, and the active L° system reset signal 5CL is input to the active L° reset input terminal R.
R enters. The active "H" two-input NAND gate 23 receives the NM1 input signal from the interrupt input device 14 and the output signal from the i'F data output terminal Q of the flip-flop circuit 22, and outputs the output signal from the interrupt terminal of the CPU 10. It is input to one active H'' NMI input terminal NMI.

Further, the control means 30 includes a two-person cover gate 24, a timer circuit 25, a two-person cover gate 26, and an IPL error display section 27. Here, the active L1 two-person gate 24 outputs the system reset signal 5CLR and the reverse phase data output terminal Q of the flip-flop circuit 22.
Input the output signal of The timer circuit 25 receives the output signal of the two-person gate 24 or the active H" input terminal Ti.
n, and after a certain period of time has elapsed since the input of the H level, an output signal of the "L" level is generated at the output terminal i'Tout. The output signal of the circuit 25 is input, and the output signal of the two-person gate 26 is input to the active L" input terminal of the CPU10.
At the same time, it is input to the IPL error table section 27 of "active L".

Next, the operation of the above-mentioned microcomputer system will be explained, but the basic operation is the same as the conventional one. That is,
System power supply (on): When this happens, an active low system reset signal 5CLR is generated from the system reset generation circuit (not shown) for a short period of time, and the second system reset signal 5CLR is sent to the CPU via the two-pass gate 26.
1. It is input to the reset input terminal RST of D. C.P.
When Ul0 is initialized by system reset 1; No.5 CLR, each segment register (not shown) and instruction pointer (not shown) in CPU10 are initialized,
The direct jump instruction placed from address FFFF0 (H) in ROM 12 is first executed, IPL is performed, and data is transferred from address 000 of RAM 11 from data input device 13.
Load the system program after 00(H). In this way, at the time of f5 IPL, the program is loaded in an order, and after loading the NMI processing program, the NMI interrupt address (00008H) is specified, the memory write signal MWR is activated, and the start address data of the NMI processing program is written. It's crowded.

Specifically, in this embodiment, the system reset signal 5
NMI input inhibition/cancellation by CLR 7 block 11707
1 The output signal of the data pressure terminal Q becomes "L" level, and the two-input NAND gate 23 receives the CP signal from the interrupt input device 14.
A state is entered in which the input of NMI to the NM1 input terminal NMI of Ul0 is prohibited. After loading the NMI processing program, the NMI interrupt address (
OO008H) decoded 1 = No. M C S 00
When 08H goes to "L level" for a short period of time and the memory write signal LIW R goes to "L level", the output signal of the two-man canand gate 2 goes to "L level" for a short period of time, and after the end of this "L level signal". Since the flip-flop circuit 22 to which the "H" level is input as a tally signal is set and the output signal of its positive phase data output terminal Q becomes "H" level, the two-input NAND gate 23 receives the NMI signal from the interrupt input device 4 to the CPU 10. The state will be such that the inhibition of input is lifted.

Therefore, during IPL, the C
It becomes possible to 'MIF' the input of NMI to P U 1 0.

On the other hand, when the system reset signal 5CLR ends, one input signal (system reset signal 5CLR) of the two-person gate 24 becomes the "H level", and the other input signal (the output of the negative phase data output terminal Q of the 7 lip-flop circuit 22 signal) goes to °H" level, the output signal of the two-man gate 24 goes to "H" level, and the timer circuit 2
5 starts and its output signal becomes "H" level.

Thereafter, within a certain timer period, an active "L" signal MCS O008H decoded from the NMI interrupt address (00008H) is generated, the flip-flop circuit 22 is set as described above, and the reverse phase data is generated. When the output signal of the output terminal Q becomes "L" level, the output signal of the two-person gate 24 becomes "L" level, the operation of the timer circuit 25 is reset, and the output signal becomes "L" level.
H Rubel remains unchanged. If the NMI interrupt address (00008H') is decoded within a certain timer period, the active L signal is activated.

If the signal MC5OOO8H is not generated, the output signal of the reverse phase data output terminal Q of the flip-flop circuit 22 becomes “H”.
“It remains at the level, and the output of the two input nordate 24 is 0.
The signal remains at the "H" level, and after the timer time elapses, the output signal of the timer circuit 25 becomes the "L" level. As a result, the output signal of the two-person gate 26 becomes "L" level, and is inputted to the CPU10 input terminal R8T as a forced reset signal, and is also inputted to the IPL error display section 27 as a display enable signal.

Therefore, it automatically and immediately detects whether or not the IPL operation has been performed within a certain period of time after the system reset operation, and when it is detected that the IPL operation has not been performed within the certain period of time. This makes it possible to forcibly reset the CPU 10 and display an abnormal operation state.

[Effects of the Invention] As described above, according to the microcomputer system of the present invention, even if an NMI is input during IPL when the NMI processing program has not yet been set, the CPU
It is possible to prevent the CPU from running out of control, and it is possible to prevent peripheral devices from being destroyed due to a runaway CPU.

Further, according to the microcomputer system of the present invention, even if 1. PL cannot be performed normally due to an erroneous operation during system setup on a data input device that stores a system program including an NMI processing program, Since it is possible to automatically and immediately detect an iPL abnormality and stop the CPU operation, and also to display an abnormal state or generate an alarm, the usability of the system is improved.

[Brief explanation of drawings]

? ! FIG. 51 is a configuration explanatory diagram showing one embodiment of the microcombutan stem of the present invention, and FIG. 2 is an illustration of the RA in FIG.
FIG. 3 is a diagram showing a memory map using M and ROM. 10...CPU, 11...RAM, 12...RO
M. 13... Data input device (floppy disk drive), 14... Interrupt input device, 20... NMI input pIk-means, 21... Two-input NAND gate, 22...
・NMI input vote stop/release flip-flop circuit, 23・
・Two-input NAND gate, 24...Two-person Kaa gate,
25...Timer circuit, 26...Two person gate,
27... IPL error display unit, 30... Control means.

Claims (2)

[Claims] (1) A central processing unit, a read-only memory in which an initial setting program is written, and a data input device in which a system program including a non-maskable interrupt processing program is stored; In a microcomputer system, the microcomputer system includes a random access memory in which a system program is stored, and an interrupt input device, further comprising means for inhibiting input of non-maskable interrupts from the interrupt input device to the central processing unit during initial program loading. A microcomputer system comprising: (2) Detecting whether the initial program loading operation was performed within a certain period of time after the system reset operation, and if it is detected that the initial program loading operation was not performed within a certain period of time, the above-mentioned 2. The microcomputer system according to claim 1, further comprising control means for forcibly resetting the central processing unit and displaying an abnormal operation state or issuing an alarm.