JPH03229294A - Display controller, display memory controller, and address converting device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display control device that controls the display of a display device.

[Conventional technology]

In document editing devices such as Japanese word processors,
There is a demand for so-called multimedia simultaneous editing in which characters, graphics, and one image are all displayed and edited in a superimposed manner on the same screen. When editing multimedia simultaneously, by assigning and drawing each media to a separate plane and overlapping each plane using hardware, drawing on one media will not affect other media. Therefore, display processing can be simplified and speeded up.

For such superimposed display of a plurality of planes, a conventional display control device uses a 1-port random access memory as a display memory, as described in Japanese Patent Laid-Open No. 12578/1983.

Although it has a single bank configuration, it has multiple planes, performs reading to acquire display data multiple times in one display cycle, and performs superimposed display by ORing the acquired data. In addition, as a display memory element, Japanese Patent Application Laid-Open No. 62-2807
As described in No. 96, in order to achieve high-speed drawing by avoiding conflicts between frequently occurring display data read access and drawing access for updating display data,
Multi-port memories with multiple access ports have been proposed.

Today, memory devices have increased in capacity, and both random access memory and multiport memory are capable of storing a considerable amount of data.

[Problem that the invention seeks to solve]

In the display control device of the above-mentioned prior art, since the display memory is configured with one bank and multiple planes, the number of display memory elements per one can be reduced, and the area where display data is not drawn in the large-capacity memory, i.e. This is effective in that the remaining area is reduced and the display memory can be used efficiently.

However, since the above conventional technology uses a random access memory with a simple one-board configuration, the number of accesses for reading display data is large, the access time is also long, and image display is slow. It wasn't.

Therefore, in order to be able to read a large number of continuous display data with one display data read access, a dedicated port for reading display data is provided in the display memory of the prior art using a multi-port memory. Considering this, the display data read from the serial port is read out with consecutive addresses, so when multiple display data are output to the display device at the same time, such as when multiple display data are superimposed, the display memory It is necessary to read out almost all of the display data in the display before superimposing the display data, which results in a problem that it takes time to output the display data to the display device, which slows down the image display.

The present invention has been made focusing on the above r:J problem, and it is possible to reduce the amount of display memory by providing a plurality of planes in one bank of display memory, and also to use multi-port memory for display memory. By configuring the configuration, the number of read accesses can be reduced, and when multiple pieces of display data are simultaneously output to a display device, such as when multiple pieces of display data are superimposed, it takes less time to output the multiple pieces of display data. It is an object of the present invention to provide a display control device 1, a display memory control device, an address conversion device, and an information processing device that can speed up image display without requiring much time.

[Means to solve the problem]

In order to achieve the above object, the present application provides the following invention.

The invention related to a display control device includes: a display memory configured with a multi-port memory having a random port and a serial port and capable of storing a plurality of display unit data forming a plane for a plurality of planes; address conversion means for converting the memory address of the display unit data at the time of drawing so that one display vehicle position data of each plane is arranged sequentially in the same cycle on the memory; Display data processing means for performing specific processing on the plurality of display unit data read out for each of the plurality of display unit data corresponding to one cycle, and then outputting the resultant data to the display device.

It is characterized by the fact that it is equipped with

The display data processing means includes a display data calculation means that superimposes a plurality of the display unit data sequentially read from the serial port of the display memory for each cycle, and then outputs the superimposed data to the display device. You may.

Further, in a display control device for a display device that divides a display screen into a plurality of parts and simultaneously scans the plurality of divided display screens, the display data processing means may process a display unit data group read from the serial port of the display memory. The display unit data may be separated into one display unit data, and then a plurality of display unit data forming one cycle may be outputted to the display device at the same time for each cycle.

Further, the display control device may include a plurality of the display memories and a display memory specifying means for specifying a display memory to be accessed from among the plurality of display memories.

The invention related to an information processing device is characterized in that it includes the display control device and a central processing device that calculates display data to be output to the display control device.

The invention related to an address conversion device is an address conversion device that converts an address of a display memory capable of storing a plurality of display unit data forming a plane for a plurality of planes, the address conversion device being a boundary between the plurality of planes. and a plane boundary register that stores the boundary plane address.

a comparator that compares the magnitude of the plane boundary address and the address of the display unit data; and a comparison by the comparator so that one display unit data of each plane is sequentially arranged on the display memory in the same cycle. The apparatus is characterized in that it includes an arithmetic unit that multiplies the address of the display unit data by an integer according to the result.

The invention related to a display memory control device is a display memory control device that controls access to a display memory capable of storing a plurality of display unit data forming a plane for a plurality of planes, in which each address conversion means for converting a memory address of the display unit data during drawing so that one display unit data of a plane is sequentially arranged in the same cycle; and a plurality of display unit data read from the display memory; The present invention is characterized by comprising display data processing means that performs specific processing on each of the plurality of display unit data for one cycle.

[Effect]

When display data is drawn on the display memory, the address is converted by the address conversion means, and one display unit data of each of the plurality of planes is sequentially arranged on the display memory in the same cycle.

When reading display data, display unit data is sequentially read out in a drawn state from the serial port of one display memory.

The display unit data that has been read in this way is subjected to specific processing for each of the plurality of display unit data for one cycle by the display data processing means, so that it is simultaneously output to the display device for each cycle. Ru.

Here, in the case where the display data processing means constitutes the display data calculation means, the read display unit data is 1
, are superimposed on a cycle-by-cycle basis and then output to a display device.

Furthermore, for example, in a display control device for a display device that simultaneously scans multiple divided display screens such as a liquid crystal display device, the read display unit data is separated for each display unit data, and then each cycle are simultaneously output to the display device.

Therefore, when outputting multiple pieces of display unit data to a display device at the same time, the display unit data of each plane is read out sequentially in the same cycle, so the display unit data of each plane is processed sequentially in each cycle. Therefore, it does not take much time to output the image to the display device, and the image can be displayed quickly.

(The following is a blank space) [Examples] Below, various embodiments of the present invention will be described using FIGS. 1 to 10. Note that the same parts in the various embodiments are given the same reference numerals and redundant explanations will be omitted.

First, an embodiment of a sentence M editing device equipped with a display control device according to the present invention will be described based on FIG.

This document editing device is a program storage type computer unit (
401 (hereinafter referred to as CPU), ROM 402 which is a non-volatile memory and has a program executed when the power is turned on, main memory 403 which can be read and written at any time, and CPU 40
An auxiliary storage device 404 that stores document information etc. according to the commands of the CPU 401, an input bag W 405 that receives input information according to the commands of the CPU 401, a printing device 406 that prints document information according to the commands of the CPU 401, and a display control bag 1!
407, and a display device 408 that performs display based on signals from the display control device 1F407.

Next, the overall operation of this document editing device will be explained.

When the power of the sentence sh collection device is turned on, the CPU 2O5 moves the document editing program stored in the auxiliary storage device 404 into the main storage device 403 according to the startup program in the ROM 402, and then transfers the document editing program stored in the auxiliary storage device 404 to the main storage device Start the operation according to the editing program.

The CPU 401 inputs data from the input bag W40S, registers and retrieves documents in the auxiliary storage device 404, and processes the printing device 40.
6 to control document printing, etc., and 1 display control bag @4o
7 to display the document on the display device 408.

In this series of operations, the present document editing device creates a document.

Next, a first embodiment of the display control device will be described based on FIGS. 1, 2, and 4 to 6.

As shown in FIG. 1, the display control device 407 includes a VRAM
Controller 101, address converter 102, display memory (hereinafter abbreviated as VRAM) 103, logic operation device 10
4, a video signal converter 105, and an oscillator 106.

VRAMIO3 is composed of a multi-port memory equipped with a random port and a serial port.

The data bus 107 on the random port 1- side is V RA
Connected to the M controller 101 and connected to the address bus 108
is connected to the address converter 102. The data bus 109 on the serial port side is connected to the logical operation unit 104 .

The VRAMIO3 can store display unit data for two planes, the first plane and the second plane. The first plane and the second plane are
Both are formed by 1m pieces of display unit data.

The VRAM controller 101 controls the display data reading memory cycle (DT cycle), the drawing memory cycle, and the refresh cycle (RF cycle) for the VRAM 103 based on instructions from the CPU 401 .

The address converter 102 is a VRAM controller 101
When accessing the VRAM 103, if it is a drawing access, as shown in FIG. 2, display unit data from the CPU controller 101 with consecutive memory addresses for each plane is received.

Converting the address so that the display unit data of the first plane and the display unit data of the second plane are arranged alternately,
In the case of DT cycles and RF cycles other than drawing accesses, the structure is such that access can be made using real memory addresses.

Furthermore, the address converter 102 can be switched between converting and outputting the VRAM controller address and outputting the VRAM controller address as is, according to instructions from the VRAM controller 101.

The oscillator 106 generates a VCLK signal, as shown in FIG.
Oscillates 5CLK signal + 2SCLK signal.

A VCLK signal line 112 from the oscillator 106 is connected to the video signal converter 105. Oscillator 106 f
The 71scLK signal line 111 is connected to the VRAM:1 controller 101 and the logical operation unit 104. The 2SCLK signal line 110 from the oscillator 106 is connected to the VRAM
ml is connected to the controller 101 and the serial port of VRAMIO3.

Note that 1 display data processing means is composed of a logic operation device 104 and a video signal converter 105.

Next, the operation of the display control device of the first embodiment will be explained.

When drawing display data, the CPU controller 101
As for the display unit data from , as shown in FIG. 2, addresses are consecutive for each plane.

This display data is address-converted by the address converter 102 and drawn on the VRAM 103 in a form in which one display unit data of the first plane and one display unit of the second plane are arranged alternately.

Note that from the CPU 401 side, the display data appears to have consecutive addresses for each plane.

When reading display data, it is read from the serial port side of the VRAM 103.

The display data that is read is the drawn state, that is,
As mentioned above, one display unit data of the first plane and one display unit data of the second plane are alternately and sequentially displayed in 2S.
The signal is output to the logical operation unit 104 via the data bus 109 in synchronization with the CLK signal.

In the logical operation device 104, one display unit data of the first plane and one display unit of the second plane, which are display unit data for one cycle, are superimposed for each cycle and output to the video signal converter 105. Ru.

The video signal converter 105 converts the video signal into a video signal based on the specifications of one display device 408 and sends it to the display device 408 .

On the screen of the display device 408, the display data of the first plane and the display data of the second plane are displayed in an overlapping manner.

Next, the configurations of the address converter 102 and the logical operation unit 104 in the display control device of the first embodiment will be described in detail.

First, the address converter 102 will be explained in detail using FIG. 4.

The address converter 102 includes a circuit unit that converts the VRAM controller address, and a circuit unit that switches between converting and not converting the VRAM controller address.

The circuit unit that converts the VRAM controller address has a plane boundary register 601 in which the plane boundary address (m in FIG. 2) of the first plane and the second plane is set, and a plane boundary register 601 that converts the plane boundary address m from the VRAM controller address. A subtracter 602 that performs subtraction, a left shifter A603 that shifts the output from the subtracter 602 to the left by 1 bit, and sets 1 to the least significant bit (AO);
Shift the RAM controller address 1 bit to the left,
Left shifter B6 that puts O in its least significant bit (AO)
05, and a selector 604 that outputs only one of the outputs of left shifter A603 and left shifter B605.

The subtracter 608 outputs a borrow signal B to the sector 604 indicating whether the result of subtracting the VRAM controller address and the plane boundary address m is positive or negative.

The circuit unit that switches between conversion and non-conversion of the VRAM controller address is a display boundary register 607 in which the display boundary address (2m in FIG. 2) between the display data area and the non-display data area of the VRAM 103 is set, and the VRAM controller. a subtractor 608 that subtracts the display boundary address from the address and determines whether the VRAM controller address is greater than the display boundary address;
The output signal from the subtracter 608, the signal indicating RF access (RF multiplication signal, and the signal indicating DT cycle access (DT multiplication signal) are ORed to output a switching signal when any one of them is input. It is comprised of a gate 6o9 and a sector 606 that outputs either the V RAM controller address or the output from the sector 604 in response to the switching signal.

A comparator that compares the magnitude of the plane boundary address and the address of the display unit data is constituted by an arithmetic unit 608, and an arithmetic unit that multiplies the display unit data by an integer according to the comparison result by the comparator is configured on the left side. It is composed of a shifter A603, a sector 604, and a left shifter B605.

In the circuit section that converts the VRAM controller address,
A subtracter 602 subtracts the plane boundary address m from the VRAM controller address from the VRAM=I controller 101, outputs the subtraction result to the left shifter A603, and sends a borrow signal B to the sector 604. Output.

The left shifter A603 shifts the subtraction result to the left by 1 bit, doubles it, and puts 1 in the least significant bit (AO). The address generated in this way becomes the real memory address when drawing access is made to the second plane.

The left shifter B605 shifts the VRAM controller address to the left by one bit, doubles it, and puts O in the least significant bit (AO). The address generated in this way becomes the real memory address when drawing access is made to the first plane.

The real memory addresses for the first plane and the second plane are determined by the selector 60 using the borrow signal B of the subtracter 602.
4, and a real memory address for drawing access to the display data area is generated.

On the other hand, in the circuit section that switches between converting and not converting the VRAM controller address, the subtracter 608 first subtracts the display boundary address from the VRAM controller address, and when the VRAM controller address is larger than the display boundary address, the VRAM controller address A signal indicating that is a drawing access to a non-display data area is output to OR gate 609.

The OR gate 609 outputs a switching signal to the sector 606 when either one of the signal indicating that the VRAM controller address is a drawing access to a non-display data area and the RF multiplied signal and the DT multiplied signal is input.

When the selector 606 receives the switching signal, it selects the unconverted VRAM controller address.

It is output as it is to the VRAM 103 as a real memory address, and when the switching signal is not input, the converted VR
VR using AM controller address as real memory address
Output to AM103.

Therefore, on VRAMIO3, the first plane and the second plane
Since one display unit data of a plane is arranged sequentially in the same cycle, when reading display data from the VRAM 103, one display unit data of the first plane and the second plane are read out alternately from the serial port of the VRAM 103. It turns out.

Next, regarding the logical operation unit 104, FIGS.
This will be explained in detail using figures.

As shown in FIG. 5, the logical operation device 104 includes a data separation latch 501 that separates and latches the m-th display data of the first plane, an OR operation circuit 502, and a synchronization lunch 5.
03.

As for the operation, as shown in Figure 6, from VRAMIO3, one display unit of the first plane and one display unit of the second plane are displayed.
Data that is read out alternately and sequentially with one display unit of the plane is latched by the data separation latch 501 from the display unit data of the second plane by latching the display unit data of the first plane at the falling edge of the 5CLK signal. To separate.

An OR operation circuit 502 performs an OR operation on the separated display unit data of the first plane and display unit data of the second plane, thereby superimposing the display data.

The ORed data is synchronized by a synchronization latch 503 and generated into continuous display data.

As described above, in this embodiment, there are two
Since two brains are provided, the number of VRAMs can be reduced.

Since VRAM is composed of multi-port memory,
The number of read accesses can be reduced, and display data whose addresses have been converted and drawn by the address converter 102 can be divided into one display unit of the first plane and one display unit of the second plane.
Since the display units of the planes are read out alternately and sequentially, the display data of the first plane and the display data of the second plane can be sequentially superimposed, and the display bag 2
It does not take much time to output the image to 408, and the image can be displayed quickly.

In addition, in FIG. 1, the V
RAM controller 101, address converter 102, V
RAM 103, logical operation unit 1o4. Although the video signal converter 105 and the oscillator 106 are drawn independently, this is for convenience's sake in order to explain the functions within the display control device 407, and they are independent in terms of hardware. However, when manufacturing the display control device 407, any one of these may be manufactured as one chip; for example, V
It is as if the display control device 407 other than the RAM 103 is configured on one chip as a VRAM control device.

Furthermore, in this embodiment, display data for two planes is stored in one bank of VRAM, but the present invention does not limit the number of planes in one bank;
Store display data for more than 3 plays in the bank,
These functions may be superimposed using a logical operation unit.

However, if display data for a large number of planes is stored in one bank, there is a limit to the reading speed from the VRAM, so there is a possibility that the reading will not be completed in one time.

This can be solved by increasing the number of banks and decreasing the number of planes per bank.

In this way, a display control device having a plurality of banks can be
An example of this will be described below using FIGS. 7 and 8.

The display control device of this embodiment, as shown in FIG.
AM controller 101, address converter 102,
A logic operation device 104, a video signal converter 105, an oscillator 106, a bank specifying device 1001, a first bank VRAM 1002, a second back VRAM 1003,
It is constituted by a logic operation device 1004.

1st bank VRAM1002 and 2nd bank VRAM1
003 is the same as the VRAMIO3 in the first embodiment, and can each store display unit data for two plays.

Also, a VRAM controller 101, an address converter 1
02, the logic operation unit 104, the video signal converter 105, and the oscillator 106 are also the same as those in the first embodiment.

The bank designation device 1001 is a VRAM 1002゜100.
This device specifies whether to write display data to the first bank, the second bank, or both banks based on a command from the CPU 401. The bank specifying device 1001 specifies both banks when performing read access for display.

The logic operation device 1004 is a device that performs logic operations on display data of four planes in total, two planes each in the first bank and the second bank.

The basic configuration of the logic operation device 1003 is the same as the logic operation device 104 of the first embodiment, but the difference is that the
As shown in the figure, data separation lunches 501 are provided for two banks, and a logic divider circuit 1101 for plane selection is provided.
．． This is because a data inversion circuit 1102 is added.

The plane selection logical product circuit @1101 selects the first plane of the second bank, the second plane of the second bank, and the The first plane of one bank and the second plane of the first bank can be selectively ORed. This means that if only input signal A becomes active (logic=1), only the first plane of the second bank will be displayed, and the other planes will not be displayed. In other words, the display plane is the CPU 401.

You can choose freely.

Data inversion circuit 1102 activates input signal E (
By setting the logic = 0), the display data is inverted and black and white reverse display is performed on the display screen.

With this configuration, even if the number of planes is three or more, the display data of the plane specified by the CPU 401 can be displayed in the same way as in the first embodiment.

Data can be read quickly from the VRAMs 1002 and 1003, and display data can be output quickly.

Note that by configuring each plane in this embodiment with display data of different colors, the display control device of this embodiment can also be used as a display control device of a color display device.

Next, a third embodiment of the one-display control device will be described based on FIG. 9 and FIG. 1o.

This embodiment is a display control device for a liquid crystal display device that divides a display screen into two areas, upper and lower, and performs display by simultaneously scanning each divided display screen in parallel.

The basic configuration of the display control device is almost the same as the display control device of the second embodiment, and includes a VRAM controller 101,
Address converter 102, oscillator 106, bank designation device 1001, first bank VRAM 1002, second bank
Back VRAM 1003, logic operation unit 10o5,
It is composed of two video signal converters 105a and 105b.

Note that the VRAM controller 101 and the address converter 1
025 oscillator 106. Bank designation device 1001, first bank VRAM1o02, second bank VRAM1002,
and video signal converters 105a, ], 05b are the same as those of the second embodiment.

However, the first bank VRAMl002, the second back VR
AM1003 stores display data of the upper divided display screen as display data of the first plane, and display data of the upper divided display screen as display data of the second plane.

As shown in FIG. 9, the logical operation unit 1005 has a first bank VRAM 1002 and a second bag VRAM
1003, data separation latches 501a and 501b separate and latch the display unit data of the upper divided display screen among the display unit data of the upper divided display screen and the display unit data of the upper divided display screen that are read out alternately and sequentially. and the first
Bank VRAM1002 and second back VRAM10
A logical sum operation circuit 502a that superimposes the display unit data of the upper divided display screen of 03, and a first bank VRAM 1002
and an OR operation circuit 502b for superimposing the display unit data of the upper divided display screen of the second back VRAM 1003, and a synchronization latch 503a for synchronizing the outputs from the OR operation circuits 502a and 502b.

503b.

FIG. 10 is a time chart representing the data flow of FIG. 9.

1st bank VRAM 1002 and 2nd back VRAM
From 1003, display unit data of the first plane forming the upper divided display screen and display unit data of the second plane forming the upper divided display screen are read out alternately and sequentially.

Data separation latches 501a and 501b each have 5
At the falling edge of the CLK signal, the first bank VRAMI O
O2, second cross') The display unit data of the first plane from the VRAM 1003 is separated and latched.

The OR operation circuits 502a and 502b each have a first
Bank VRAM1.002 and second back VRAM
The display unit data of the first plane 1003 and the display unit data of the second plane of the first bank VRAMI○02 and the second back VRAM 1003 are superimposed.

Synchronization-77chi503. S03 outputs the outputs from the OR circuits 502a and 502b as upper divided display screen display data and upper divided display screen display data, respectively, at the rising edge of the 5CLK signal.

The video signal converters 105 and 105 respectively convert the upper divided display screen display data and the upper divided display screen display data into video signals based on the specifications of a liquid crystal display device (not shown), and then simultaneously convert the upper divided display screen display data into a video signal based on the specifications of a liquid crystal display device (not shown). send to

In this embodiment, one display unit data of the upper split display screen and one display unit data of the upper split display screen are read out alternately and sequentially from the VRAM 1002.1003.
There is no need to read almost all of the display data in M1, 002, and 1003, divide it into those for the upper split display screen and for the upper split display screen, and then output it to the liquid crystal display device. The display data of the split display screen and the display data of the upper split display screen can be sequentially output.

〔Effect of the invention〕

According to the present invention, since a plurality of planes are provided within one bank of display memory, the number of display memories can be reduced.

Furthermore, since the display memory is configured with a multi-port memory, the number of read accesses can be reduced, and when multiple pieces of display data are output to the display device at the same time, the addresses are converted by the address conversion means and drawn. Since the displayed display data for each plane is read out sequentially in the same cycle, the display unit data for each plane can be processed sequentially in each cycle, and it takes less time to output it to the display device. This allows for faster image display.

[Brief explanation of drawings]

1 to 6 show a first embodiment, in which FIG. 1 is a block diagram of a display control device, FIG. 2 is an explanatory diagram showing a memory address map of a display memory, and FIG. 3 is a block diagram of a display control device. FIG. 4 is a block diagram of the document editing device, FIG. 4 is a block diagram of the address converter, FIG. 5 is a block diagram of the logical operation device, FIG. 6 is a time chart showing the flow of display data read from the display memory, and FIG. 7 and 8 show the second embodiment, FIG. 7 is a block diagram of the display control device, and FIG. FIG. 9 is a block diagram of the logical operation device, and FIG. 10 is a time chart showing the flow of display data read from the display memory. 101...VRAM controller, 102...Address converter, 103-VRAM, 104, 1004° 1005=-Logic operation unit, 105, 105a. 105b... Video signal converter, 106... Oscillator,
401- CPU, 407- Display control device, 40
8 display devices, 501, 501 a, 50 l b
- data isolation latch, 502, 502a, 50
2b-OR operation circuit, 503, 503a,
503 b...Synchronization launch, 601...Boundary plane register, 602°608...Subtractor, 60
3...Left shifter A, 604°606...Sector, 6
05...Left shifter B, 1001...Bank designation device, 1
0o2...First bank VRAM, 1003...Second bank VRAM.

Claims (1)

[Scope of Claims] 1. A display control device that controls the display of a display device, comprising a multi-port memory having a random port and a serial port, and storing a plurality of display unit data forming a plane in a plurality of planes. a display memory capable of storing data for minutes, and an address conversion that converts the memory address of the display unit data during drawing so that one display unit data of each plane is sequentially arranged in the same cycle on the display memory. display data processing that performs specific processing on each of the plurality of display unit data for one cycle, and outputs the plurality of display unit data sequentially read from the serial port of the display memory to the display device; A display control device comprising: means. 2. In a display control device that controls the display of a display device, it is configured with a multi-port memory equipped with a random port and a serial port, and is capable of storing a plurality of display unit data forming a plane for a plurality of planes. Converting the memory address of the display unit data at the time of drawing so that a plurality of display unit data to be simultaneously output to the display device among the display memory and display unit data of each plane are arranged together on the display memory. and display data processing means that performs specific processing on each set of display unit data, and outputs the resultant data to the display device, on a plurality of the display unit data sequentially read out from the serial port of the display memory. A display control device comprising: 3. A display control device that controls the display of a display device is configured with a multi-port memory equipped with a random port and a serial port, and is capable of storing a plurality of display unit data forming a plane for a plurality of planes. a display memory; an address conversion means for converting a memory address of the display unit data at the time of drawing so that one display unit data of each plane is sequentially arranged on the display memory in the same cycle; and the display memory. A display control device comprising display data calculation means for superimposing a plurality of the display unit data sequentially read from the serial port in one cycle and outputting the superimposed data to the display device. 4. In a display control device for a display device that divides a display screen into a plurality of parts and simultaneously scans the plurality of divided display screens, the display control device is configured with a multi-port memory equipped with a random port and a serial port, and is configured to scan the plurality of divided display screens simultaneously. a display memory capable of storing a plurality of display unit data to be formed for a plurality of split display screens; and a display memory capable of storing one display unit data of each split display screen sequentially in the same cycle on the display memory; address converting means for converting a memory address of the display unit data at the time of drawing; and separating a display unit data group read from the serial port of the display memory into one display unit data;
A display control device comprising display data processing means for simultaneously outputting a plurality of the display unit data forming one cycle to the display device in each cycle. 5. The display according to claim 1, 2, 3, or 4, comprising a plurality of said display memories, and further comprising display memory specifying means for specifying a display memory to be accessed from among the plurality of display memories. Control device. 6. An address conversion device for converting addresses of a display memory capable of storing a plurality of display unit data forming a plane for a plurality of planes, the address conversion device storing a boundary plane address serving as a boundary between the plurality of planes. a plane boundary register, a comparator for comparing the magnitude of the plane boundary address and the address of the display unit data, and one display unit data of each plane is arranged sequentially in the same cycle on the display memory, An address conversion device comprising: an arithmetic unit that multiplies the address of the display unit data by an integer according to a comparison result by the comparator. 7. In a display memory control device that controls access to a display memory capable of storing a plurality of display unit data forming a plane for a plurality of planes, one display unit data of each plane is stored on the display memory. an address converting means for converting the memory address of the display unit data during drawing so that the display unit data is sequentially arranged in the same cycle; 1. A display memory control device comprising: display data processing means for performing specific processing on each display unit data. 8. An information processing device comprising: the display control device according to claim 1, 2, 3, 4, or 5; and a central processing unit that calculates display data to be output to the display control device.