JPH03228368A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce power consumption without deterioration of characteristics of an MOSFET, without loss of the speed of a logic circuit by driving at least the MOSFET circuit with a source voltage corresponding to the degree of miniaturization in a hybrid LSI comprising the MOSFET circuits and bipolar transistor logic circuits. CONSTITUTION:In an LSI applied to a memory, circuit blocks are formed on one semiconductor chip like a single crystalline silicon substrate. In the memory, a memory array M-ARY is formed of a MOSFET circuit or a ROM cell, and a peripheral circuit PRP is formed of an NTL logic circuit. Common source voltages Vcc and Vee are supplied to the array M-ARY and the circuit PRP, and the entire memory is driven by a single power supply. As the source voltage, for example, the Vcc is set to a ground potential, and the Vee is set to an optimum level corresponding to the miniaturization level of a MOS circuit. Thus, the constants of an FET can be so set as not to cause a malfunction such as a short-channel effect upon miniaturization.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to semiconductor integrated circuit technology, as well as a plurality of bipolar transistors and a plurality of MOSFETs (metal-oxide-
Regarding technologies that are particularly effective when applied to single-chip LSIs (Large-Scale Integrated Circuits) in which semiconductor field-effect transistors are mixed, for example, technologies that are effective when applied to large-capacity high-speed memories, memories with logic, and logic LSIs. Regarding.

[Prior Art] There are two market demands regarding the characteristics of semiconductor memories: larger capacity and faster speed. Conventionally, memory that uses MOS FET as a semiconductor memory that responds to larger capacity, so-called M
OS memories and so-called bipolar memories using bipolar transistors are provided on the market as semiconductor memories that meet the demands for higher speeds. Furthermore, in order to simultaneously meet the demands for both larger capacity and higher speed, we have developed a bipolar CMO3 (hereinafter referred to as Bi-0MO3) in which each memory cell in the memory array is configured with a MOSFET circuit, and the peripheral circuit is configured with a bipolar ECL circuit. ) memory has been proposed (l'Electronics" Feb, 19
89. ASPEN SHOWSBiCMO3CANY
IELD FASRSRAMS), CMOS is a complementary MO8 circuit, that is, P-channel MOS
It means a combination circuit of FET and N-channel MOSFET.

[Problem to be solved by the invention] Since the above B1-CMOS memory uses an ECL circuit in the peripheral circuit, the standard power supply voltage is 5.2V (]
OK),! Two types of memory using a knee voltage of 4.5V (100K) have been commercialized.

By the way, MO3 integrated circuits are known to suffer from many problems such as short channel effects and an increase in hot carriers as the gate length of each MOSFET becomes smaller. In the process, -5 above
, 2V or -4.5V power supply voltage does not cause much problem even if it is used in the MOS FET circuit, so the conventional B1
-CMOS memory used a single power supply.

However, it is expected that the miniaturization of LSIs will progress further in the future. Therefore, the conventional single power supply type B1-CMOS
In memory, contrary to the scaling law, MOSFE
Since a high voltage will be applied to T, there is a high possibility that various problems such as short channel effects will occur. In addition, with the miniaturization of processes, the capacity of memory will continue to increase, so power consumption will increase if the conventional power supply voltage is maintained.
There is a possibility that increasing the capacity will be hindered.

An object of the present invention is to provide a MOSFET circuit and a bipolar transistor logic circuit in an LSI in which a MOSFET circuit and a bipolar transistor logic circuit are mixed.
The object is to reduce power consumption without deteriorating the characteristics of SFET or impairing the speed of logic circuits.

Another object of the present invention is to increase the operating speed and scale of a logic LSI, a memory LSI, or an LSI with a built-in memory without increasing power consumption.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, the bipolar transistor circuit section and the MOSFE
T circuit section, bipolar transistor and MOSFE
In an LSI in which a composite circuit section consisting of T is mixed, the bipolar transistor circuit section is configured with an NTL (non-threshold logic) logic circuit, and the bipolar transistor circuit section and MOSFET circuit section are constructed with a logic circuit that is lower than the ECL logic circuit. Drive with the same power supply voltage or use MOS
The FET circuit section is driven with a power supply voltage lower than the power supply voltage of the bipolar transistor circuit section.

Note that as the NTL logic circuit, it is desirable to use an NTL circuit with an active pull-down circuit (hereinafter referred to as an SPL circuit).

As methods for providing different power supply voltages, there are a method in which two types of power supply voltage terminals are provided and a method in which a step-up circuit or a step-down circuit is provided inside the LSI.

[Function] According to the above-mentioned means, at least the MOSFET circuit section can be operated at a power supply voltage of -5.2 V or -4.
5V) whose absolute value is lower than the absolute value of the power supply voltage (-
3V or less), it is possible to set the constants of each MOSFET, such as channel length and channel width W, so as not to cause problems associated with miniaturization such as short channel effects. At the same time, since the power consumption of an LSI is proportional to the magnitude of the power supply voltage, the power consumption can be significantly reduced by driving the MOSFET with a power supply voltage lower than that in the past.

Furthermore, since the bipolar transistor circuit section is constituted by an NTL circuit, its power supply voltage can be lower than that of the ECL system, and the same power supply voltage as that of the MOSFET circuit can be used, making it possible to use a single power supply. Moreover, N.T.
The L circuit has a shorter gate delay time than the ECL circuit,
However, since the number of constituent elements is small, it is possible to increase the speed and scale the logic without increasing the power consumption of the semiconductor device.

Furthermore, when an NTL circuit with an active pull-down circuit is used as the NTL logic circuit, current flows only when the input signal changes and a constant current source is not required, further reducing the power consumption of the LSI. I can do it.

In addition, as a technology to increase the signal processing speed of LSI, shorten the data reading time of memory, and reduce power consumption, we used a MOS FET circuit in the input logic section.
A method has been proposed in which a so-called Bi-CMO3 logic circuit using a bipolar push-pull type circuit is used in the output stage. However, the current Bi-CMO3 is used in memory peripheral circuits.
When a logic circuit is used, its output amplitude is (VCC-2
VBE). Therefore, the MO of the next stage gate is
Ves of 3 becomes small, and in the region of low power supply voltage (2 to 3 V), the signal transmission speed of Bi-CMO3 logic circuit becomes CMO
It is slower than that of S gate. Therefore, it is expected that it will be difficult to use the current B i -CMO8 logic circuit in peripheral circuits because there is a risk that the operating speed of the logic gate will deteriorate as the voltage decreases.

[Embodiment] FIGS. 1A and 1B show conceptual diagrams of an embodiment in which the present invention is applied to a memory.

Although not particularly limited, each circuit block surrounded by a dotted chain line A in the figure is formed on one semiconductor chip such as a single crystal silicon substrate.

In the memory shown in FIG. 10(A), the memory array section M-ARY is a CMOS cell as shown in FIG.
A MOSFET circuit such as a high resistance load type NMOS cell as shown in Figure 0 (B), a PMOS cell as shown in Figure 10 (C), a Dyminac type cell as shown in Figure 10 (D), It is composed of ROM cells using nonvolatile memory elements as shown in Figure (E), and the peripheral circuits PRP such as decoders and sense amplifiers are NTL circuits, SPL circuits, or BicMO3 using MOSFETs in part.
It is composed of NTL logic circuits such as NTL circuits and SPL circuits. Common power supply voltages Vcc and Vee are supplied to the memory array section M-ARY and the peripheral circuit PRP, so that the entire memory is driven by a single power supply.

As the power supply voltages Vcc and Vee, for example, Vc
c is the ground potential, and Vee is the optimum level corresponding to the miniaturization level of the MOS circuit (for example, -3 in a 0.5 μm process).
, 3V, -2.5V for a 0.3 μm process).

Here, each memory cell in FIGS. 10(A) to 10(E) will be briefly described.

The memory cell of FIG. 10(A) consists of a pair of inverters (Q m
1, Qm2) and (Qm3.Qm4), and the source and drain were connected between the output terminal of each inverter and the data line pair, and the gate terminal was connected to the word line W. A pair of selection MOSs
FETQm5. Qm6.

The memory cell in FIG. 10(B) is a P-channel MOSFET Qml in the memory cell in FIG. 10(A).

Qm3 is a load resistance Rml made of polysilicon or the like.

It was changed to Rm2. Furthermore, the memory cell in FIG. 10(C) has an N-channel M in the memory cell in FIG. 10(A).
OSFET Qm2. , Qm4 are replaced by load resistors Rml and Rm2 made of polysilicon or the like.

The memory cell in FIG. 10(D) consists of an information charge storage capacitor Cm and a selection MOSFET 0m7.
This is a one-transistor capacitor type DRAM cell.

The memory cell in Figure 10(E) is FAMO3 (floating gate avalanche injection MO3).
Or a non-volatile memory element Qn such as an MNOS (metal-nitride monoxide-semiconductor structure) element and a selection MOSF
This is a ROM cell consisting of ET 0m7.

On the other hand, in the memory shown in FIG. 1(B), the memory array section M-
Power supply voltages Vcc (GND) and Vee are supplied to ARY, and power supply voltages Vcc and Vee' are supplied to peripheral circuit section PRP, so that they are driven by separate power supplies. In this case, vee can be set to a voltage corresponding to the miniaturization level of the MOS circuit, and Vee' can be set to a voltage of -2V suitable for an NTL circuit. This makes it possible to further reduce the power consumption of the peripheral circuits.

As for the supply method of the power supply voltages Vee and Vee', for example, separate external power supply terminals may be provided for vee and Vee', or they may be supplied from the outside as one power supply and internally of the LSI. A power supply circuit such as a step-up circuit or a step-down circuit may be provided.

Further, in the above embodiment, the peripheral circuit is an NTL circuit or an SP circuit.
Although the L circuit is used, the peripheral circuit is not limited thereto, and the peripheral circuit may be configured using a TTL circuit or a Bi-0M03 circuit.

Further, in the above embodiment, the memory array is composed of MOSFET circuits, but memory cells composed of bipolar transistor circuits as shown in FIGS. 11(A) to 11(D) may also be used. In that case, the present invention can be applied if the peripheral circuit is configured with a MOSFET circuit or an 0M03 circuit.

To briefly explain the memory cells in FIGS. 11(A) to 11(D), each memory cell in FIGS. 11(A) to 11(C) has a multi-emitter transistor Qm8. Qm9 and a load resistor Rm3 connected to its collector side. It is basically a flip-flop circuit consisting of Rm4. Among these, the circuit in the same figure (A) is
Transistor Qm8. In order to operate Qm9 in the non-saturation region and increase the speed, load resistance Rm3. An SBD clamp type meko memory cell with Schottky barrier diodes 5BDI and 5BD2 connected in parallel with Rm4.

Furthermore, the memory cell in FIG. 11(B) uses a Schottky barrier diode 5B in order to increase the ratio between the read current IR and the information retention current 1st to reduce power consumption during standby.
An SBD load switch memory cell is formed by connecting low resistances Rcl and Rc2 in series with DI and 5BD2.

The memory cell in FIG. 11(C) has load resistances Rm3 and Rm
In parallel with diodes DI, D2 and pnp transistors Qp1. This is a pnp clamp type memory cell designed with emphasis on reducing the cell area by connecting Qp2.

Furthermore, the memory cell in FIG. 11(D) has a load resistance Rm
3. Rm4 is replaced by a pnp transistor Qp3. Q
By using p4 and cross-coupling two thyristors, I
This is a cross-coupled pnp transistor with a large */Ist ratio and stable operation. However, the formation of the memory cell is not limited to the one described above, and other circuit types may be used.

FIGS. 2A and 2B show an embodiment in which the present invention is applied to a memory with logic.

Of these, in the memory shown in FIG.
It is composed of NTL logic circuits like circuits. In this case, since the power supply voltage can be shared with the memory peripheral circuit section PPP, Vcc and Vee or Vcc and Vee' are used. On the other hand, the memory in FIG. 2(B) has a logic section LGC.
is an ECL circuit as shown in FIG. 12(A) or the first
CMO3 circuit as shown in Figure 2 (B), Figure 12 (C)
i-CMO3 logic circuit as shown in Figure 12 (D)
It is composed of a TTL circuit as shown in FIG.

In this case, since the logic amplitude of the logic section LGC is larger than that of the NTL circuit, a power supply voltage V e ", which is different from that of the peripheral circuit PRP, is used for the logic section LGC, and a level difference between the logic section LGC and the peripheral circuit PRP is used. An interface circuit ITF having a conversion function is provided.Power supply voltage Vcc
may be the same as the memory array section MARY and the peripheral circuit PRP, or may be provided with a separate power supply. Especially when using a TTL circuit, in addition to Vcc and Vee (Vee'), V o
It is also possible to use o. Note that the logic section LG
C may be a dedicated circuit designed in advance, or may be a gate array whose logic is constructed by a mask slicing method.

Although the logic circuits shown in FIGS. 12(A) to 12(D) are already known circuits, their configurations and operations will be briefly explained.

In the ECL logic gate of FIG. 12(A), three input transistors Q41 to Q43 and a reference transistor Q44 have their emitters commonly connected, and a constant current source I is connected between the common emitter and the power supply voltage V e ''.

A current switch C8 is configured by connecting the two. In addition, a resistor Rcl is connected between the common collector terminal of input transistors Q41 to Q43 and power supply voltage Vcc.
However, a resistor Rc2 is connected to the collector terminal of the reference transistor Q44, and the collector voltage of the transistor Q44 is applied to the base terminal of an output transistor Q45 constituting the emitter follower output stage EF. This causes this ECL logic gate to control the input signal INI~I
When one of N3 is changed to high level, the current path of current switch O8 is switched and transistor Q45
is turned on, and the output signal OUT changes to high level, operating as a three-man OR gate.

The CMOS logic gate in FIG. 12(B) has a power supply voltage Vc
3 P-channel MOSFETs between c and output terminal
Qpl to Qp3 are connected in parallel, and three n-channel MOSFETs are connected between the output terminal and the power supply voltage Vee.
Qnl to Qn3 are connected in series.

This causes this 0MO3 logic gate to input the input signal IN
A three-person NAN in which the output signal OUT changes to low level only when all of I to IN3 change to high level.
Operates as a D gate.

The B1-CMOS logic gate in FIG. 12(C) is a P channel) LiMOSFET Qp4 and an Nf'r channel MOS.
A CMO3 logic unit CLG consisting of FET Qn4,
It is constituted by a push-pull output stage PPO formed by two bipolar transistors Q46 and Q47 connected in series. This Bi-0MO3 logic gate is the output stage P
Since one of the PO transistors is always turned off, power consumption is low. Moreover, since the load is driven by a bipolar transistor, it is fast. The logic of the circuit in the same figure (C) is an inverter, but the CMO3 logic section CLG
By changing the configuration of , it is possible to configure a logic ring such as NOR logic or NAND logic.

In the TTL logic gate of FIG. 12(D), the collector terminal of the multi-emitter input transistor Q48 is connected to the series resistor Rf.
It is connected to the base terminal of a phase inverting transistor Q49 that constitutes a phase split circuit FSP together with I and Rf2. Output transistor Q46 . The base terminal of Q47 is connected and configured to alternately turn on and off. This TTL logic gate turns off transistor Q49 and turns on transistor Q46 only when input signals INI and IN2 are both changed to high level, and output signal O.
It operates as an AND gate where UT changes to high level.

FIGS. 3A to 3F show configuration examples of NTL logic gates used in the peripheral circuit PPP.

The circuit shown in FIG. 3(A) is a basic NTL circuit, and here a three-man NOR logic type circuit is shown. The input stage of this circuit consists of three input transistors Qll~
Q13 are connected in parallel to each other, a collector resistor Rc is connected between their common collector terminal and the power supply voltage Vcc, and an emitter resistor Re is connected between their common emitter terminal and the power supply voltage Vee.

In addition, the output stage 2 consists of an emitter follower, and the input stage I
An emitter follower transistor Q is connected to the common collector terminal of
21 base terminals are connected. In this NTL circuit, when one of the three input signals Vinl to Vin3 is changed to a high level, a current flows to the input stage 1, the output transistor Q21 is turned on, and the output signal Vout is changed to a high level. Ru.

FIG. 3(B) shows an example of an SPL circuit. The input stage 1 of the SPL circuit of this embodiment is the same as the circuit shown in FIG. It is tiered.

The base terminal of a pull-up transistor Q21 constituting the output stage 2 is connected to a connection node n1 between the common collector of the input transistors Qll-Q13 and the resistor Rc.

Further, the transistor Q31 is connected between the power supply voltage Vcc and Vee.
and resistor R1 are connected in series, and their connection node n
3, the pull-down transistor Q22 of the output stage 2
base terminal is connected. The above transistor Q3
1 has a constant voltage VBI applied to its base terminal, and functions as a biasing means for the transistor Q22. In this case, the bias point of transistor Q22 is determined by the base voltage Val and the value of resistor R1. Along with this, a capacitor C1 is connected between a connection node n3 between the bias transistor Q31 and the resistor R1 and a common emitter terminal n2 of the input stage l. This capacitor C1 and the resistor R1 constitute a differentiating circuit that detects a change in the voltage level of the node n2, and this differentiating circuit detects a change in the voltage level of the node n2 from low to high, and temporarily pulls down the transistor. Turn on Q22 to make the output fall faster.

Furthermore, in this embodiment, the clamping transistor Q32 for fixing the high level of the output is connected to the power supply voltage terminal V
cc and the output terminal OUT. A constant voltage VB2 is applied to the base terminal of the transistor Q32, whereby the high level of the output signal Vout is clamped to a potential lower than VB2 by the base-emitter voltage VBE of the transistor Q32.

The SPL circuit of FIG. 3(B) has three input signals Vinl
~ When one of Vin3 is changed to high level, current flows to input stage 1, output transistor Q31 is turned on, and output signal Vout is changed to high level.NOR
Acts as a gate. Moreover, since this SPL circuit is an active pull-down type, the NT shown in Fig. 3(A)
Compared to the L circuit, the rise of the output signal Vout is made as fast as the fall.

FIG. 3(C) shows the bias transistor Q31 of the circuit of FIG. 3(B). Q32, resistor R2 and differential circuit (CI and R
This is a simplified gate in which 1) is omitted, and the output stage 2 is a totem pole type. FIG. 3(D) also shows each of the output polar transistors Q21. of FIG. 3(C). Q22 and output MOSFET Q33. This is a replacement for Q34.

Furthermore, the circuits of FIGS. 3(E) and 3(F) have emitter resistances Re of the input stage 1 and output stage 2 of the circuit of FIG. 3(A).

RE (7) substitute) MOSFET in J Q35. Q36
In this example, the circuit shown in FIG. 3(E) uses two load MOSFETs Q35. Q36 (7) Constant voltage Vref 1. Vref2 is applied to operate as a constant current source, and in the circuit of Fig. 3(F), the load MOSFE
Only TQ35 is used as a constant current source, MOSFET
Q36 has its gate applied with the potential of node n1 of input stage 1, and operates as a pull-down transistor.

In each gate circuit of FIGS. 3(C) to (F), when one of the three input signals Vinl to Vin3 is changed to a high level, a current flows to the input stage 1, and the output transistor Q2
1 or Q33 is turned on, and the output signal Vout is changed to a high level.

FIGS. 4A to 4D show an example of a level conversion circuit provided in the interface circuit section TF when the logic section LGC is constituted by an ECL circuit. Of these, (A) in the same figure is input from the logic section LGC -0.8~
An example of a level conversion circuit that converts an ECL level signal such as -1.7v into an NTL level signal such as -0°8v to -1,2V suitable for an NTL circuit and supplies it to the peripheral circuit section PRP. , and in the same figure (C) conversely, the NTL level signal output from the peripheral circuit PPP to the logic section LGC is
An example of a circuit for level conversion is shown.

Furthermore, FIG. 4(B) shows a level conversion circuit when the input signal is in a differential format, and FIG. 4(D) shows a level conversion circuit when the output signal is in a differential format.

Each level conversion circuit converts a current change into a voltage change in the previous stage, and receives the level change in an emitter follower to convert the NTL
It outputs a signal with a low amplitude of about 400 mV suitable for the circuit.

That is, the level conversion circuit of FIG. 4(A) includes a level shift stage LSI in which a resistor Rcl, a bipolar transistor Qbl, and a constant current source Icl are connected in series between the power supply voltage Vcc and the bipolar transistor Qb.
A transistor Q with a collector voltage of l applied to its base
el and an emitter follower EFI consisting of a constant current source Ic3 connected between its emitter terminal -700. This level conversion circuit connects 10, 5 to the base terminal of the transistor Qbl of the level shift stage LSI.
A constant voltage VB such as V is applied, and when a signal with an amplitude of -0.8 to -1.7V is input to its emitter terminal, the current flowing through the transistor Qbl changes depending on the level of the signal. , the amount of voltage drop across the resistor Rcl changes.

As a result, the output terminal OU of the emitter follower EFI
A signal at an NTL level such as -0.8 to 1.2 is output from T.

The level conversion circuit of FIG. 4(B) includes two level shift stages LSI and LS2 having the same configuration as the level shift stage LSI of the level conversion circuit of FIG. 4(A), and two emitter followers EFI and EF2. . This level conversion circuit is E
CL level differential signals IN and IN are level-converted into NTL level differential signals OUT and OUT, respectively, and output.

In the level shift stage LSI, a resistor Rcl, a bipolar transistor Qbl, and a constant current source Icl are connected to a power supply voltage terminal Vc.
c - V ee are connected in series.

The level shift stage LS2 has a resistor Rc2, a bipolar transistor Qb2, and a constant current source Ic2 connected to a power supply voltage terminal Vc.
c - V ee are connected in series.

The emitter follower EFI is a bipolar transistor Q
el and constant current source Ic3 are connected to power supply voltage terminal Vcc-Vee
are connected in series between them.

The emitter follower EF2 is a bipolar transistor Q
e2 and constant current source Ic4 are connected to the power supply voltage terminal Vcc-Vee
are connected in series between them.

Transistor Qbl in level shift stage LSI and LSZ
, Qb2 are biased with a common constant voltage VB.

The level conversion circuit of FIG. 4(C) has a power supply voltage Vcc and a
A level shift stage L in which a resistor Rc3, a bipolar transistor Qb3, and a constant current source Icl are connected in series between 00 and 00.
S3 and a constant current source Ic3 connected between the transistor Qel, whose base is applied with the collector voltage of the bipolar transistor Qb3, and its emitter terminal -700.
and an emitter follower EFI. This level conversion circuit includes a level shift stage LS3.
10 to the base terminal of transistor Qb3.

When a signal with an amplitude of 8 to -1.2 V is input, the current flowing through the transistor Qb3 changes depending on the level of the signal, and the amount of voltage drop across the resistor Rc3 changes. by this,
-0,8 from output terminal OUT of emitter follower EFI
An ECL level signal such as ~1.7V is output.

The level conversion circuit in FIG. 4(D) has two level shift stages LS3. LS4 and two emitter followers EFI and EF2. This level conversion circuit is N
TL level differential signals IN and IN are level-converted into ECL level differential signals OUT and 0tJT, respectively, and output.

The level shift stage LS3 has a resistor Rc3, a bipolar transistor Qb3, and a constant current source Icl connected to a power supply voltage terminal VCc-.
vee are connected in series.

The level shift stage LS4 has a resistor Rc4, a bipolar transistor Qb4, and a constant current source Ic2 connected to a power supply voltage terminal Vcc-
It is connected in series between Vee and Vee.

The emitter follower EFI is a bipolar transistor Q
el and constant current source Ic'3 are connected to the power supply voltage terminal Vcc-V
connected in series between ee and ee.

The emitter follower EF2 is a bipolar transistor Q
e2 and constant current source Ic4 are connected to the power supply voltage terminal Vcc-Vee
are connected in series between them.

Level shift stage LS3 and constant current sources in LSA ■c1 and I
c2 can be shared.

Note that the constant current source Ic in each level conversion circuit may be a combination of a general constant current transistor and a resistor, or may simply be a resistor or a constant current source Ic with a constant voltage applied to the gate.
It may be an OSFET or a variable impedance MOSFET.

FIGS. 5A to 5D show an example of a level conversion circuit provided in the interface circuit ITF when the logic section LGC is composed of an MO8 circuit or a TTL circuit. Of these, (A) in the same figure shows the MOS level or TTL level signal input from the logic section LGC.
Convert it to a signal with an amplitude suitable for the L circuit and send it to the peripheral circuit section PRP.
FIG. 3C shows an example of a level conversion circuit for converting a signal output from the peripheral circuit PRP to the logic section LGC to a MOS level or a TTL level.

Furthermore, FIG. 5(B) shows a level conversion circuit when the input signal is differential, and FIG. 5(D) shows a level conversion circuit when the output signal is differential.

The level conversion circuit in FIG. 5(A) is a P-channel MOSFET.
A first-stage inverter INV in which an ET Q51 and an N-channel MOS FET Q52 are connected in series between power supply voltages Vcc and Vee, a MOSFET Q53 whose gate terminal receives the output voltage of this inverter, and a constant voltage Vb at its base terminal. are applied to the bipolar transistor Q54, these transistors Q53 . Q5
4 and a common constant current source Ic5. A differential level shift stage LS5 consisting of a drain resistance Rd of FET Q53, a collector resistance Rc5 of transistor Q54, and a transistor Q
Emitter follower EF consisting of e3 and constant current source Ic6
3.

This level conversion circuit changes the output voltage of the first stage inverter INV to Vee when an input signal IN such as OV is supplied.
Therefore, FET Q53 of level shift stage LS5 is turned off, current flows to the transistor Q54 side, its collector voltage is lowered by the voltage drop across resistor Rc5, and transistor Qe3 is turned off. As a result, the emitter follower E
A signal OUT at a level of -1, 2V is output from the output terminal of F3. On the other hand, when an input signal IN such as -5V is supplied, the output voltage of the first stage inverter INV is Vcc
(OV), and FET Q of level shift stage LS5
53 is turned on, the current on the transistor Q54 side is cut off, a base voltage of Vcc level is applied to the emitter follower transistor Qe3, and Qe3 is turned on.

As a result, a signal UT having a level of -0°8V is output from the output terminal of the emitter follower EF3.

Note that the first-stage inverter INV in FIG. 5(A) can be omitted.

The level conversion circuit of FIG. 5(B) omits the first stage inverter INV in the level conversion circuit of FIG. 5(A), and uses the bipolar transistor Q5 of the differential level shift stage LS5.
MOSFETQ54' is used in place of MOSFET 4. Further, a second emitter follower EF4 consisting of a transistor Qe4 and a constant current source 1c7 is also connected to the drain terminal side of the FET Q53.

This level conversion circuit has CMOS level or TTL level differential input signals IN and MOSFET Q5.
3. It is designed to be input to the gate terminal of Q54', and when either Q53 or Q54' is turned on and the other is turned off, the emitter flower EF3
．． -0,8 to -1,2v NTL from the output terminal of EF4
Level signals OUT and OUT are output.

The level conversion circuit of FIG. 5(C) uses a P channel 9MO instead of the emitter follower output stage EFI in the NTL-ECL level conversion circuit shown in FIG. 4(C).
SFET Qp5 and N-channel MOSFET Qn
This circuit type uses a CMOS push-pull type output stage PP5 consisting of a resistor Re6 and a transistor Q55.
The level shift stage LS6 includes a constant current Ic8, and the output stage PP5. Output stage PP5
Since a MOSFET is used for the output signal, the output signal can be fully varied from the power supply voltage Vcc to Vee. In this level conversion circuit, when an input signal IN at a level of -0.8V is input, transistor Qb3 is turned on and its collector voltage and emitter voltage are lowered. Then, the output stage MOS FET Qp5 turns on, Qn5 turns off, and V
An output signal OUT having a level of cc (OV) is output. On the other hand, when the input signal IN at the level of -1 or 2V is input, the transistor Qb3 is turned off and its collector voltage and emitter voltage rise. Then, M of the output stage
OSFET Qp5 is off, Qn5 is on, Vee
An output signal OUT having a level of (-5V) is output.

The level conversion circuit of FIG. 5(D) uses bipolar transistors Q53'' and Q54 in place of the MOSFETs Q53 and Q54' in the level conversion circuit of FIG. 5(B), and also uses the output stage transistors Qe3 and Qe4. Instead, the circuit format uses MOSFETs Q56 and Q57.

This level conversion circuit uses an NTL level differential input signal I.
N, IN are input to the base terminals of transistors Q53' and Q54, and Q53' or Q5
4 is turned on and the other is turned off,
One of MOSFET Q56 or Q57 is turned on and the output signal OUT, OU at 0MO3 or TTL level
T is output.

FIG. 6 shows an example of a circuit configuration in which the memory of the type shown in FIG. 1(A) is shown in a block configuration, and FIG. 7 shows a specific circuit example of the main part thereof.

In FIG. 6, LAXO to LAXi are address latch circuits that take in externally supplied X-system addresses AXO-AXi in synchronization with clock CK;
Similarly, j is a Y address latch circuit that takes in the Y system address AYO-AYj.

Further, LC3 and LWE are latch circuits that take in the chip select signal O8 and write control signal WE supplied from the outside in synchronization with the clock CK.

Furthermore, LDi is a data latch circuit that takes in the write data signal Di.

The X-related address signals AXO-AXi latched by the X-address latch circuits LAXO-LAXi are supplied to the X-address buffer XADB, and internal complementary addresses axo, a
xO~axi, axi are formed, and the X decoder XDCR
is supplied to In addition, in the figure, aXO and aXO are aX
It is shown as O. One of the word lines WO to Wm in the memory array section M-ARY is driven to the selection level by the X decoder XDCR.

On the other hand, the Y-system address signal AYO-AYj latched by the Y-system address circuit AYO-AYj is supplied to the Y-address buffer YADB and internal complementary addresses ayo, ayo
~ayjt ayj is formed, Y decoder YDCR
is supplied to In addition, in the figure, ayO and TyO are ay
It is shown as O. When reading data, Y decoder YDCR forms selection signal Y1xYn to drive one of sense amplifiers SAI to SAn connected to each bit line pair in memory array section M-ARY.

Sense amplifiers 5AI-8An are common bit line pairs CBL,
It is connected to the clamp circuit CLP via CBL.

The minute level difference between the bit lines caused by the data held in the selected memory cell MC is detected by the corresponding sense amplifier SAi.
and is supplied to the data output buffer DOB via the clamp circuit CLP. The read data held in the data output buffer DOB is controlled by control signals C3 and W.
A control signal φo is output at an appropriate timing from a timing control circuit TC that forms an internal control signal based on E.
e is supplied to the data latch LDO, latched, and then output to the outside.

On the other hand, during data writing when the write control signal WE is set to low level, the decoder DLB receives the control signal φwe output from the timing control circuit TC and the selection signals Y1 to Yn from the Y address decoder YDCR as input signals.
1 to DLBn, D
One of the charge circuits DLI-DLn connected to the bit line is driven to charge the selected bit line to the Vcc level. Further, the write amplifier WA is driven by the internal control signal φwe output from the timing control circuit TC, and one of the selected bit line pair is powered on according to the write data Din latched in the data latch LDi at that time. Pull the voltage vee. As a result, the memory cell MC connected to the selected word line is inverted and data is written.

In the above embodiment, the memory cell MC is, for example,
Although the CMOS type cell shown in FIG. 10(A) is used, FIG. 10(B) to (E) and FIG. 11(A) to
Other memory cells shown in (D) can also be used.

Note that in the above embodiment, the power supply voltage V of the memory cell MC
When a bipolar transistor is used as a pull-up transistor at the final stage of the X decoder XDCR, the CCM preferably uses a level −VBE lower than Vcc, corresponding to the word line selection level. This is because if the selection level of the word line is lower than the power supply voltage VCCM of the memory cell, a write failure may occur.

Figure 7 shows the X decoder XD of the memory shown in Figure 6.
A specific circuit example of a part of CR, memory cell MC, sense amplifier SA, and charge circuit (data line load circuit) DL is shown.

Figure 7 shows NC)R gates Gl and G2 connected in two stages as part of the X decoder XDCR, and each NOR gate Gl and G2 is equipped with an active pull-down circuit as shown in Figure 3(B). NTL circuit and its modified NTL circuit (MO in place of transistor Q23)
SFET Q22').

The input transistor Q12 of the NOR gate G2 in the subsequent stage. Q
13, other pre-decoding NOR gates G1'', Gl
” (not shown) is input.

In addition, in FIG. 7, a MOSFET is used as a pull-down transistor Q22' in the output stage of the NTL gate G2 in the subsequent stage.
The reason why ET is used is to increase the amplitude of the word line to prevent erroneous writing to memory cells. It goes without saying that the NOR gates G1 and G2 can be constructed by other types of NTL circuits shown in FIGS. 3(A) to 3(F).

The sense amplifier SAI - for example, for each bit line pair, D
differential type transistors Qsl and Qs2 whose respective base terminals are connected to
The collectors of differential transistors Qsl and Qs2 are connected to the emitters of transistors Qcl and Qc2 forming a clamp circuit via common bit lines CBL and CBL. Since the differential transistors of a plurality of sense amplifiers are connected to the common bit line in a collector-dot manner, the parasitic capacitance is large. Therefore, if a load resistor is directly connected to the common bit line, the time constant of the common bit line becomes large and the delay time increases.

As in the embodiment, the common bit line is ramped by transistors Qcl and Qc2 constituting the clamp circuit CLP,
If load resistors Rcl and RC2 are connected to the collectors of the transistors Qcl and Qc2, which have small parasitic capacitances, and a read signal is taken out, a high-speed sense circuit can be realized.

M connected to the emitters of transistors Qcl and Qc2
O3Qc3. Qc4 is a constant current source.

Note that MSI is a column switch that is controlled on/off by the selection signal Y1 from the Y decoder.
to supply its operating current to.

QPI and QP2 are precharge transistors forming a precharge circuit DL during writing.

Qwl and 0w2 are write transistors connected between the bit line D and Vee, and when one of them is turned on by a signal obtained by ANDing the write timing signal φwe and the write data Din and Di5, One of the bit lines is connected to Vee and the memory cell MC is inverted.

FIG. 8 shows an example of a latch circuit using an NTL circuit. This latch circuit consists of four NTL gates G11
- It is composed of Gl4. When configuring this circuit,
Since two output terminals are required for each NTL circuit, a circuit with two emitter followers EFI and EF2 connected to node n1 of input stage l as shown in Figure 9 (however, the number of inputs is limited to three 2 people can do it).

Any of the circuit formats shown in FIGS. 3(A) to 3(F) may be used.

As explained above, in the above embodiment, in an LSI in which bipolar transistor circuits and MOSFET circuits coexist, the bipolar transistor circuit section is configured with an NTL (non-threshold logic) type logic circuit, and the bipolar transistor circuit section and MOSFET circuit are configured. Department, EC
Although it is driven by the same power supply voltage lower than the L logic circuit,
Since the MOSFET circuit section is driven with a power supply voltage lower than that of the bipolar transistor circuit section, at least the MOSFET circuit section has a lower power supply voltage than the conventional ECL system power supply voltage (-5.2V or -4.5V). Since it is driven with a low power supply voltage (3V or less), the constant of the FET can be set to avoid problems associated with miniaturization such as short channel effects, and power consumption can be significantly reduced.

In addition, since the bipolar transistor circuit section is configured with an NTL circuit, even if the power supply voltage is lower than that of the ECL system, MO
It can be driven with the same power supply voltage as the SFET circuit, making it possible to use a single power supply.

Moreover, since the NTL circuit has a shorter gate delay time and fewer components than the ECL circuit, it is possible to increase the speed and scale the logic without increasing power consumption.

Furthermore, when an NTL circuit with an active pull-down circuit is used as the NTL circuit, current flows only when the input signal changes, and there is no need for a constant current source, which further reduces power consumption.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, although the above embodiment is applied to a memory with a clock-based latch, it goes without saying that it can be applied to a memory that does not have a latch circuit for external input. In addition, NTL circuits are not limited to those powered by two or three people, but can be powered by one person or any number of inputs.
It can be a TL circuit.

In the above explanation, the invention made by the present inventor was mainly applied to memory, which is the field of application that formed the background of the invention. Microcontrollers and other bipolar transistor circuits and MOS F
Can be used in general LSIs that include ET circuits.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, in an LSI in which MOSFET circuits and bipolar transistor logic circuits are mixed, MOS FET circuits and bipolar transistor logic circuits are mixed.
Power consumption can be reduced without deteriorating the characteristics of the ET or reducing the speed of the logic circuit.

[Brief explanation of drawings]

FIGS. 1(A) and (B) are conceptual diagrams showing an embodiment of the present invention applied to a memory, and FIGS. 2(A) and (B) are conceptual diagrams showing an embodiment of the present invention applied to a memory with logic. Conceptual diagram showing one embodiment, FIGS. 3(A) to (F)
) is a circuit diagram showing a configuration example of an NTL logic circuit, and Figures 4 (A) to (D) are ECL-N of the interface section.
A circuit diagram showing a configuration example of a TL level conversion circuit, Figures 5 (A) to (D) are MC3-N of the interface section.
A circuit diagram showing a configuration example of a TL level conversion circuit, FIG. 6 is a block configuration diagram showing an example of a suitable memory to which the present invention is applied, FIG. 7 is a circuit diagram showing a specific circuit example of the main part, Fig. 8 is a logic circuit diagram showing an example of a latch circuit, Fig. 9 is a circuit diagram showing an example of an NTL circuit suitable for the latch circuit configuration, and Figs. 10 (A) to (E) are MO8 type memory cells. 11(A) to (D) are circuit diagrams showing an example of the structure of a bipolar memory cell. FIG. 12(A) is a circuit diagram showing an example of the structure of an ECL logic circuit. Figure 12 (B) is a circuit diagram showing an example of a configuration of a CMOS logic circuit, Figure 12 (C) is a circuit diagram showing an example of a configuration of a B1-CMOS logic circuit, and Figure 12 (D) is an example of a configuration of a TTL logic circuit. FIG. l...Input stage, 2...Output stage, M-ARY...
...Memory array, PPP...Peripheral circuit, LAX. LAY: Address latch circuit, MC: Memory cell, SA: Sense amplifier. Fig. 2 IT) I-11'? and Figure (B) (C) (E) ee ee Figure (D) (F) ee ee Figure 8 Figure ee ee Figure 0 Figure (A) (8) Figure (A) (C) ee Figure (B) ) (D)ee

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device in which a bipolar transistor circuit and a MOSFET circuit are formed on the same substrate, at least the MOSFET circuit is driven by a power supply voltage corresponding to the degree of miniaturization thereof. A semiconductor integrated circuit device comprising: 2. The above-mentioned bipolar transistor circuit is constructed based on a non-threshold logic type logic circuit, and is sufficient to maintain the operation of the logic circuit and is a MOS transistor.
The above-mentioned bipolar transistor circuit and MOSFET
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is configured to be driven. 3. The memory array section is composed of a MOSFET circuit, and its peripheral circuit is composed of a bipolar transistor circuit,
At least the memory array section includes MOs constituting it.
A semiconductor memory characterized in that it is configured to be driven with a power supply voltage corresponding to the degree of miniaturization of SFETs. 4. The above-mentioned peripheral circuit is basically configured with a non-threshold logic type logic circuit, and is powered by a power supply voltage that is sufficient to maintain the operation of the logic circuit and corresponds to the degree of miniaturization of the MOSFET circuit section. 4. The semiconductor memory according to claim 3, wherein the bipolar transistor circuit and the MOSFET circuit are configured to be driven. 5. It is composed of a bipolar transistor circuit and has a data logic section, and the memory array section is composed of a MOSFET circuit,
Its peripheral circuit is composed of a bipolar transistor circuit, and at least the memory array section is
5. The semiconductor memory with logic according to claim 4, wherein the semiconductor memory is configured to be driven with a power supply voltage corresponding to the degree of miniaturization of the OSFET. 6. The logic section is composed of logic circuits of a different type from the peripheral circuits, and is driven by a different power supply voltage, and there is no signal level conversion between the logic section and the peripheral circuits. 6. The semiconductor memory with logic according to claim 5, further comprising an interface circuit for mutually transmitting the data.